Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830446
Omid Ghadami, Hongyu Lu, Matthew R. Chan, Mila Tan, Saeromi Chung, Sang Heon Lee, Matthew T. Holden, Ryan de Ridder, Barry Merriman, D. Hall
This work describes the highest feature density CMOS-based DNA synthesizer, where individually addressable sub-μm pixels generate acid in situ for deprotection. A new redox chemistry enables this at low voltages. Implemented in 65nm CMOS, electrodes as small as 0.6μm2 were implemented, and oligos up to 100 nucleotides (nt) were synthesized.
{"title":"Helix: An Electrochemical CMOS DNA Synthesizer","authors":"Omid Ghadami, Hongyu Lu, Matthew R. Chan, Mila Tan, Saeromi Chung, Sang Heon Lee, Matthew T. Holden, Ryan de Ridder, Barry Merriman, D. Hall","doi":"10.1109/vlsitechnologyandcir46769.2022.9830446","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830446","url":null,"abstract":"This work describes the highest feature density CMOS-based DNA synthesizer, where individually addressable sub-μm pixels generate acid in situ for deprotection. A new redox chemistry enables this at low voltages. Implemented in 65nm CMOS, electrodes as small as 0.6μm2 were implemented, and oligos up to 100 nucleotides (nt) were synthesized.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134051583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830425
Juhyuk Park, Dae-Myeong Geum, Woojin Baek, J. Shieh, Sanghyeon Kim
This work demonstrated the monolithic 3D (M3D) integrated red micro-LED display on Si CMOS driver IC. We achieved a very high pixel density of 1600 PPI by epitaxial layer engineering and low-temperature process design for the micro- display application. M3D sequential integration on pre- fabricated Si CMOS driver IC allows lithographic alignment for the pixel definition, providing high-resolution and the largest emission area per pixel pitch. Furthermore, the low-temperature process provided the lowest standby power among ever reported micro-LED displays. We believe that this work would be one of the milestones for future ultra-high-resolution displays.
{"title":"Monolithic 3D sequential integration realizing 1600-PPI red micro-LED display on Si CMOS driver IC","authors":"Juhyuk Park, Dae-Myeong Geum, Woojin Baek, J. Shieh, Sanghyeon Kim","doi":"10.1109/vlsitechnologyandcir46769.2022.9830425","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830425","url":null,"abstract":"This work demonstrated the monolithic 3D (M3D) integrated red micro-LED display on Si CMOS driver IC. We achieved a very high pixel density of 1600 PPI by epitaxial layer engineering and low-temperature process design for the micro- display application. M3D sequential integration on pre- fabricated Si CMOS driver IC allows lithographic alignment for the pixel definition, providing high-resolution and the largest emission area per pixel pitch. Furthermore, the low-temperature process provided the lowest standby power among ever reported micro-LED displays. We believe that this work would be one of the milestones for future ultra-high-resolution displays.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131930136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830418
Woyu Zhang, Shaocong Wang, Yi Li, Xiaoxin Xu, Danian Dong, Nanjia Jiang, Fei Wang, Zeyu Guo, Renrui Fang, C. Dou, Kai Ni, Zhongrui Wang, Dashan Shang, Meilin Liu
Learning graph structured data from limited examples on-the-fly is a key challenge to smart edge devices. Here, we present the first chip-level demonstration of few-shot graph learning which homogeneously implements both the controller and associative memory of a memory-augmented graph neural network using a 1T1R resistive random-access memory (RRAM). Leveraging the in-memory computing paradigm, we validated the high end-to-end accuracy of 78% (GPU baseline 80%) and robustness on node classification of CORA dataset, while achieved 70-fold reduction in latency and 60-fold reduction in energy consumption compared with conventional digital systems.
{"title":"Few-shot graph learning with robust and energy-efficient memory-augmented graph neural network (MAGNN) based on homogeneous computing-in-memory","authors":"Woyu Zhang, Shaocong Wang, Yi Li, Xiaoxin Xu, Danian Dong, Nanjia Jiang, Fei Wang, Zeyu Guo, Renrui Fang, C. Dou, Kai Ni, Zhongrui Wang, Dashan Shang, Meilin Liu","doi":"10.1109/vlsitechnologyandcir46769.2022.9830418","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830418","url":null,"abstract":"Learning graph structured data from limited examples on-the-fly is a key challenge to smart edge devices. Here, we present the first chip-level demonstration of few-shot graph learning which homogeneously implements both the controller and associative memory of a memory-augmented graph neural network using a 1T1R resistive random-access memory (RRAM). Leveraging the in-memory computing paradigm, we validated the high end-to-end accuracy of 78% (GPU baseline 80%) and robustness on node classification of CORA dataset, while achieved 70-fold reduction in latency and 60-fold reduction in energy consumption compared with conventional digital systems.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134269303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830322
Hechen Wang, Renzhi Liu, R. Dorrance, D. Dasalukunte, Xiaosen Liu, D. Lake, B. Carlton, May Wu
This paper presents an SRAM-based analog Compute-in-Memory (CiM) macro in 22 nm CMOS process. By introducing a C-2C capacitor ladder-based charge domain computing scheme, the CiM prototype chip demonstrates 2k multiply-accumulation (MAC) operations in one clock cycle and achieves 32.2 TOPS/W peak energy efficiency and 4.0 TOPS/mm2 peak area efficiency with 8-bit precision in both input activation and weight. A variety of analog impairment factors were analyzed during the testchip implementation to ensure sufficiently high multibit linearity.
{"title":"A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference","authors":"Hechen Wang, Renzhi Liu, R. Dorrance, D. Dasalukunte, Xiaosen Liu, D. Lake, B. Carlton, May Wu","doi":"10.1109/vlsitechnologyandcir46769.2022.9830322","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830322","url":null,"abstract":"This paper presents an SRAM-based analog Compute-in-Memory (CiM) macro in 22 nm CMOS process. By introducing a C-2C capacitor ladder-based charge domain computing scheme, the CiM prototype chip demonstrates 2k multiply-accumulation (MAC) operations in one clock cycle and achieves 32.2 TOPS/W peak energy efficiency and 4.0 TOPS/mm2 peak area efficiency with 8-bit precision in both input activation and weight. A variety of analog impairment factors were analyzed during the testchip implementation to ensure sufficiently high multibit linearity.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133116149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830279
Pai-Ying Liao, S. Alajlouni, M. Si, Zhuocheng Zhang, Zehao Lin, J. Noh, Calista Wilk, A. Shakouri, P. Ye
In this work, we investigate the thermal issues of top-gated (TG), ultrathin, atomic layer deposition (ALD) grown, back-end-of-line (BEOL) compatible indium oxide (In2O3) transistors by observation and visualization of the self-heating effect (SHE) using high-resolution thermo-reflectance (TR) measurement. SHE is alleviated by highly resistive silicon (HR Si) substrate with high thermal conductivity (κSi). The increased temperature (ΔT) of the devices on HR Si substrate is roughly 6 times lower than that with SiO2/Si substrate. Furthermore, thermal simulation with a finite-element method exhibits exceptional agreement to ΔT distribution with experimental results. By thermal engineering, TG In2O3 transistors with channel thickness (Tch) of 1.8 nm and high drain current (ID) up to 2.65 mA/µm are achieved.
{"title":"Thermal Studies of BEOL-compatible Top-Gated Atomically Thin ALD In2O3 FETs","authors":"Pai-Ying Liao, S. Alajlouni, M. Si, Zhuocheng Zhang, Zehao Lin, J. Noh, Calista Wilk, A. Shakouri, P. Ye","doi":"10.1109/vlsitechnologyandcir46769.2022.9830279","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830279","url":null,"abstract":"In this work, we investigate the thermal issues of top-gated (TG), ultrathin, atomic layer deposition (ALD) grown, back-end-of-line (BEOL) compatible indium oxide (In2O3) transistors by observation and visualization of the self-heating effect (SHE) using high-resolution thermo-reflectance (TR) measurement. SHE is alleviated by highly resistive silicon (HR Si) substrate with high thermal conductivity (κSi). The increased temperature (ΔT) of the devices on HR Si substrate is roughly 6 times lower than that with SiO2/Si substrate. Furthermore, thermal simulation with a finite-element method exhibits exceptional agreement to ΔT distribution with experimental results. By thermal engineering, TG In2O3 transistors with channel thickness (Tch) of 1.8 nm and high drain current (ID) up to 2.65 mA/µm are achieved.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133538099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ultra-low temperature wafer-level Cu-Cu direct bonding with wetting/passivation scheme has been successfully demonstrated at (1) room temperature with post-annealing at 100 ℃, or (2) 40 ℃ bonding without the post-annealing process. In this bonding structure, a wetting layer and a passivation layer were deposited on the Cu surface to improve the surface conditions and enhance the diffusion behavior of Cu atoms. In addition, the wetting layer can prevent formation of AuCu3 between passivation and Cu, which is beneficial for Cu bonding at a lower temperature. The proposed bonding structure provides the breakthrough to realize wafer-level Cu-Cu direct bonding with an almost thermal stress-free process, which is key to improve reliability and broaden applications of 3D integration and advanced packaging.
{"title":"Room Temperature Cu-Cu Direct Bonding Using Wetting/Passivation Scheme for 3D Integration and Packaging","authors":"Zhong-Jie Hong, Demin Liu, S. Hsieh, Han-Wen Hu, Ming-Wei Weng, Chih-I Cho, Jui-Han Liu, Kuan-Neng Chen","doi":"10.1109/vlsitechnologyandcir46769.2022.9830175","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830175","url":null,"abstract":"Ultra-low temperature wafer-level Cu-Cu direct bonding with wetting/passivation scheme has been successfully demonstrated at (1) room temperature with post-annealing at 100 ℃, or (2) 40 ℃ bonding without the post-annealing process. In this bonding structure, a wetting layer and a passivation layer were deposited on the Cu surface to improve the surface conditions and enhance the diffusion behavior of Cu atoms. In addition, the wetting layer can prevent formation of AuCu3 between passivation and Cu, which is beneficial for Cu bonding at a lower temperature. The proposed bonding structure provides the breakthrough to realize wafer-level Cu-Cu direct bonding with an almost thermal stress-free process, which is key to improve reliability and broaden applications of 3D integration and advanced packaging.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115927660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830206
D. Truesdell, Xinjian Liu, J. Breiholz, Shourya Gupta, Shuo Li, B. Calhoun
This work presents NanoWattch, a self-powered SoC in 65-nm CMOS with integrated temperature sensing for miniaturized IoT applications. NanoWattch can cold-start and sustain operation directly from ambient light with a photovoltaic input as low as 160mV. A performance-scalable RISC-V processor with 6kB SRAM and DVFS subsystem enable system power consumption to continuously adapt to ambient energy conditions down to a minimum total system power of 3nW to provide always-on operation in a mm-scale form factor.
{"title":"NanoWattch: A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling","authors":"D. Truesdell, Xinjian Liu, J. Breiholz, Shourya Gupta, Shuo Li, B. Calhoun","doi":"10.1109/vlsitechnologyandcir46769.2022.9830206","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830206","url":null,"abstract":"This work presents NanoWattch, a self-powered SoC in 65-nm CMOS with integrated temperature sensing for miniaturized IoT applications. NanoWattch can cold-start and sustain operation directly from ambient light with a photovoltaic input as low as 160mV. A performance-scalable RISC-V processor with 6kB SRAM and DVFS subsystem enable system power consumption to continuously adapt to ambient energy conditions down to a minimum total system power of 3nW to provide always-on operation in a mm-scale form factor.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115539217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a 12-bit 8GS/s RF sampling current-steering DAC in a 5nm FinFET process. To minimize code-dependent nonlinearity caused by the timing differences between switch drivers, the proposed timing mismatch compensation (TMC) architecture is presented. For high static linearity with small size current cell, an on-chip current cell calibration scheme is implemented with absolute DAC (0.0625LSB/code accuracy). The proposed DAC achieves 72.2dBc SFDR, while consuming 169mW at 8GS/s sampling frequency.
{"title":"A 12-bit 8GS/s RF Sampling DAC with Code-Dependent Nonlinearity Compensation and Intersegmental Current-Mismatch Calibration in 5nm FinFET","authors":"Byeongwoo Koo, SungHan Do, Sang-Gyu Nam, H. Shin, Sungno Lee, Eunhye Oh, Jaemin Hong, Jungho Lee, Young-Sae Cho, Michael Choi, Jongshin Shin","doi":"10.1109/vlsitechnologyandcir46769.2022.9830442","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830442","url":null,"abstract":"This paper presents a 12-bit 8GS/s RF sampling current-steering DAC in a 5nm FinFET process. To minimize code-dependent nonlinearity caused by the timing differences between switch drivers, the proposed timing mismatch compensation (TMC) architecture is presented. For high static linearity with small size current cell, an on-chip current cell calibration scheme is implemented with absolute DAC (0.0625LSB/code accuracy). The proposed DAC achieves 72.2dBc SFDR, while consuming 169mW at 8GS/s sampling frequency.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114122433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, we report bottom-gate amorphous indium-gallium-zinc-oxide (a-IGZO) transistors with extremely scaled channel length (LCH) down to 12.3 nm enabled by a novel Al2O3/HSQ dual-layer lift-off technique. Thanks to the smallest LCH of 12.3 nm among all bottom-gate IGZO transistors, a record high peak extrinsic transconductance (Gm,ext) of 479.5 μS/μm at VDS = 1 V was realized among all IGZO-based transistors. In addition to the capability of realizing ultra-scaled feature sizes, the Al2O3/HSQ dual-layer lift-off process can achieve a reduced patterning variation as compared with that of the conventional lift-off process due to the better line edge roughness of hydrogen silsesquioxane (HSQ) electron-beam (E-beam) resist. The highest cut-off frequency (fT) of 18.3 GHz at VDS of 3 V was also achieved with a LCH of 38 nm among all a-IGZO transistors.
{"title":"Extremely Scaled Bottom Gate a-IGZO Transistors Using a Novel Patterning Technique Achieving Record High Gm of 479.5 μS/μm (VDS of 1 V) and fT of 18.3 GHz (VDS of 3 V)","authors":"Chengkuan Wang, Annie Kumar, Kaizhen Han, Chen Sun, Haiwen Xu, Jishen Zhang, Yuye Kang, Qiwen Kong, Zijie Zheng, Yuxuan Wang, Xiao Gong","doi":"10.1109/vlsitechnologyandcir46769.2022.9830393","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830393","url":null,"abstract":"In this work, we report bottom-gate amorphous indium-gallium-zinc-oxide (a-IGZO) transistors with extremely scaled channel length (L<inf>CH</inf>) down to 12.3 nm enabled by a novel Al<inf>2</inf>O<inf>3</inf>/HSQ dual-layer lift-off technique. Thanks to the smallest L<inf>CH</inf> of 12.3 nm among all bottom-gate IGZO transistors, a record high peak extrinsic transconductance (G<inf>m,ext</inf>) of 479.5 μS/μm at V<inf>DS</inf> = 1 V was realized among all IGZO-based transistors. In addition to the capability of realizing ultra-scaled feature sizes, the Al<inf>2</inf>O<inf>3</inf>/HSQ dual-layer lift-off process can achieve a reduced patterning variation as compared with that of the conventional lift-off process due to the better line edge roughness of hydrogen silsesquioxane (HSQ) electron-beam (E-beam) resist. The highest cut-off frequency (f<inf>T</inf>) of 18.3 GHz at V<inf>DS</inf> of 3 V was also achieved with a L<inf>CH</inf> of 38 nm among all a-IGZO transistors.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115763516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830265
Seok-Hee Lee
Innovation in the memory semiconductor industry has continued to provide a number of key solutions to address the challenges of ever-changing, data-driven computing. However, besides the demand for high performance, low power, low cost, and high capacity, there is also an increasing demand for more smart functionalities in or near memory to minimize the data movement.In this paper, we will share our vision of memory innovation. First, we begin the journey with memory extension, in which the conventional scaling in both DRAM and NAND can be pushed further to defy the device scaling limits. Then, the journey will ultimately lead to the memory-centric transformation. The memory-centric transformation has just begun with PIM (Processing-In-Memory) and is expected to evolve by bringing memory and logic closer together with advanced packaging techniques in order to achieve optimal system performance.In addition, new solutions enabled by new interfaces such as CXL (Compute Express Link) will be introduced to enhance the current value proposition of the memory technology.Last but not least, our endeavors as a responsible member of the global community will be introduced. Our ongoing efforts are focused on reducing carbon emissions, water usage, and power consumption in all our products and manufacturing processes.SK hynix truly believes that the journey of Memory would only be possible when the ICT industry as a whole embraces open innovation to create a better and more sustainable world.
{"title":"The Rise of Memory in the Ever-Changing AI Era – From Memory to More-Than-Memory","authors":"Seok-Hee Lee","doi":"10.1109/vlsitechnologyandcir46769.2022.9830265","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830265","url":null,"abstract":"Innovation in the memory semiconductor industry has continued to provide a number of key solutions to address the challenges of ever-changing, data-driven computing. However, besides the demand for high performance, low power, low cost, and high capacity, there is also an increasing demand for more smart functionalities in or near memory to minimize the data movement.In this paper, we will share our vision of memory innovation. First, we begin the journey with memory extension, in which the conventional scaling in both DRAM and NAND can be pushed further to defy the device scaling limits. Then, the journey will ultimately lead to the memory-centric transformation. The memory-centric transformation has just begun with PIM (Processing-In-Memory) and is expected to evolve by bringing memory and logic closer together with advanced packaging techniques in order to achieve optimal system performance.In addition, new solutions enabled by new interfaces such as CXL (Compute Express Link) will be introduced to enhance the current value proposition of the memory technology.Last but not least, our endeavors as a responsible member of the global community will be introduced. Our ongoing efforts are focused on reducing carbon emissions, water usage, and power consumption in all our products and manufacturing processes.SK hynix truly believes that the journey of Memory would only be possible when the ICT industry as a whole embraces open innovation to create a better and more sustainable world.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115854684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：