Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830157
Sanquan Song, S. Tell, B. Zimmer, Sudhir S. Kudva, N. Nedovic, C. T. Gray
The rapid complexity growth of electronic systems nowadays increases their vulnerability to hacking, such as fault injection, including insertion of glitches into the system clock to corrupt internal state through timing errors. As a countermeasure, a frequency locked loop (FLL) based clock glitch detector is proposed in this paper. Regulated from an external supply voltage, this FLL locks at 16-36X of the system clock, creating four phases to measure the system clock by oversampling at 64-144X. The samples are then used to sense the frequency and close the frequency locked loop, as well as to detect glitches through pattern matching. Implemented in a 5nm FINFET process, it can detect the glitches or pulse width variations down to 3.125% of the input 40MHz clock cycle with the supply varying from 0.5 to 1.0V.
{"title":"An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process","authors":"Sanquan Song, S. Tell, B. Zimmer, Sudhir S. Kudva, N. Nedovic, C. T. Gray","doi":"10.1109/vlsitechnologyandcir46769.2022.9830157","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830157","url":null,"abstract":"The rapid complexity growth of electronic systems nowadays increases their vulnerability to hacking, such as fault injection, including insertion of glitches into the system clock to corrupt internal state through timing errors. As a countermeasure, a frequency locked loop (FLL) based clock glitch detector is proposed in this paper. Regulated from an external supply voltage, this FLL locks at 16-36X of the system clock, creating four phases to measure the system clock by oversampling at 64-144X. The samples are then used to sense the frequency and close the frequency locked loop, as well as to detect glitches through pattern matching. Implemented in a 5nm FINFET process, it can detect the glitches or pulse width variations down to 3.125% of the input 40MHz clock cycle with the supply varying from 0.5 to 1.0V.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133491824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830446
Omid Ghadami, Hongyu Lu, Matthew R. Chan, Mila Tan, Saeromi Chung, Sang Heon Lee, Matthew T. Holden, Ryan de Ridder, Barry Merriman, D. Hall
This work describes the highest feature density CMOS-based DNA synthesizer, where individually addressable sub-μm pixels generate acid in situ for deprotection. A new redox chemistry enables this at low voltages. Implemented in 65nm CMOS, electrodes as small as 0.6μm2 were implemented, and oligos up to 100 nucleotides (nt) were synthesized.
{"title":"Helix: An Electrochemical CMOS DNA Synthesizer","authors":"Omid Ghadami, Hongyu Lu, Matthew R. Chan, Mila Tan, Saeromi Chung, Sang Heon Lee, Matthew T. Holden, Ryan de Ridder, Barry Merriman, D. Hall","doi":"10.1109/vlsitechnologyandcir46769.2022.9830446","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830446","url":null,"abstract":"This work describes the highest feature density CMOS-based DNA synthesizer, where individually addressable sub-μm pixels generate acid in situ for deprotection. A new redox chemistry enables this at low voltages. Implemented in 65nm CMOS, electrodes as small as 0.6μm2 were implemented, and oligos up to 100 nucleotides (nt) were synthesized.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134051583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830425
Juhyuk Park, Dae-Myeong Geum, Woojin Baek, J. Shieh, Sanghyeon Kim
This work demonstrated the monolithic 3D (M3D) integrated red micro-LED display on Si CMOS driver IC. We achieved a very high pixel density of 1600 PPI by epitaxial layer engineering and low-temperature process design for the micro- display application. M3D sequential integration on pre- fabricated Si CMOS driver IC allows lithographic alignment for the pixel definition, providing high-resolution and the largest emission area per pixel pitch. Furthermore, the low-temperature process provided the lowest standby power among ever reported micro-LED displays. We believe that this work would be one of the milestones for future ultra-high-resolution displays.
{"title":"Monolithic 3D sequential integration realizing 1600-PPI red micro-LED display on Si CMOS driver IC","authors":"Juhyuk Park, Dae-Myeong Geum, Woojin Baek, J. Shieh, Sanghyeon Kim","doi":"10.1109/vlsitechnologyandcir46769.2022.9830425","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830425","url":null,"abstract":"This work demonstrated the monolithic 3D (M3D) integrated red micro-LED display on Si CMOS driver IC. We achieved a very high pixel density of 1600 PPI by epitaxial layer engineering and low-temperature process design for the micro- display application. M3D sequential integration on pre- fabricated Si CMOS driver IC allows lithographic alignment for the pixel definition, providing high-resolution and the largest emission area per pixel pitch. Furthermore, the low-temperature process provided the lowest standby power among ever reported micro-LED displays. We believe that this work would be one of the milestones for future ultra-high-resolution displays.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131930136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830418
Woyu Zhang, Shaocong Wang, Yi Li, Xiaoxin Xu, Danian Dong, Nanjia Jiang, Fei Wang, Zeyu Guo, Renrui Fang, C. Dou, Kai Ni, Zhongrui Wang, Dashan Shang, Meilin Liu
Learning graph structured data from limited examples on-the-fly is a key challenge to smart edge devices. Here, we present the first chip-level demonstration of few-shot graph learning which homogeneously implements both the controller and associative memory of a memory-augmented graph neural network using a 1T1R resistive random-access memory (RRAM). Leveraging the in-memory computing paradigm, we validated the high end-to-end accuracy of 78% (GPU baseline 80%) and robustness on node classification of CORA dataset, while achieved 70-fold reduction in latency and 60-fold reduction in energy consumption compared with conventional digital systems.
{"title":"Few-shot graph learning with robust and energy-efficient memory-augmented graph neural network (MAGNN) based on homogeneous computing-in-memory","authors":"Woyu Zhang, Shaocong Wang, Yi Li, Xiaoxin Xu, Danian Dong, Nanjia Jiang, Fei Wang, Zeyu Guo, Renrui Fang, C. Dou, Kai Ni, Zhongrui Wang, Dashan Shang, Meilin Liu","doi":"10.1109/vlsitechnologyandcir46769.2022.9830418","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830418","url":null,"abstract":"Learning graph structured data from limited examples on-the-fly is a key challenge to smart edge devices. Here, we present the first chip-level demonstration of few-shot graph learning which homogeneously implements both the controller and associative memory of a memory-augmented graph neural network using a 1T1R resistive random-access memory (RRAM). Leveraging the in-memory computing paradigm, we validated the high end-to-end accuracy of 78% (GPU baseline 80%) and robustness on node classification of CORA dataset, while achieved 70-fold reduction in latency and 60-fold reduction in energy consumption compared with conventional digital systems.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134269303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830322
Hechen Wang, Renzhi Liu, R. Dorrance, D. Dasalukunte, Xiaosen Liu, D. Lake, B. Carlton, May Wu
This paper presents an SRAM-based analog Compute-in-Memory (CiM) macro in 22 nm CMOS process. By introducing a C-2C capacitor ladder-based charge domain computing scheme, the CiM prototype chip demonstrates 2k multiply-accumulation (MAC) operations in one clock cycle and achieves 32.2 TOPS/W peak energy efficiency and 4.0 TOPS/mm2 peak area efficiency with 8-bit precision in both input activation and weight. A variety of analog impairment factors were analyzed during the testchip implementation to ensure sufficiently high multibit linearity.
{"title":"A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference","authors":"Hechen Wang, Renzhi Liu, R. Dorrance, D. Dasalukunte, Xiaosen Liu, D. Lake, B. Carlton, May Wu","doi":"10.1109/vlsitechnologyandcir46769.2022.9830322","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830322","url":null,"abstract":"This paper presents an SRAM-based analog Compute-in-Memory (CiM) macro in 22 nm CMOS process. By introducing a C-2C capacitor ladder-based charge domain computing scheme, the CiM prototype chip demonstrates 2k multiply-accumulation (MAC) operations in one clock cycle and achieves 32.2 TOPS/W peak energy efficiency and 4.0 TOPS/mm2 peak area efficiency with 8-bit precision in both input activation and weight. A variety of analog impairment factors were analyzed during the testchip implementation to ensure sufficiently high multibit linearity.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133116149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830279
Pai-Ying Liao, S. Alajlouni, M. Si, Zhuocheng Zhang, Zehao Lin, J. Noh, Calista Wilk, A. Shakouri, P. Ye
In this work, we investigate the thermal issues of top-gated (TG), ultrathin, atomic layer deposition (ALD) grown, back-end-of-line (BEOL) compatible indium oxide (In2O3) transistors by observation and visualization of the self-heating effect (SHE) using high-resolution thermo-reflectance (TR) measurement. SHE is alleviated by highly resistive silicon (HR Si) substrate with high thermal conductivity (κSi). The increased temperature (ΔT) of the devices on HR Si substrate is roughly 6 times lower than that with SiO2/Si substrate. Furthermore, thermal simulation with a finite-element method exhibits exceptional agreement to ΔT distribution with experimental results. By thermal engineering, TG In2O3 transistors with channel thickness (Tch) of 1.8 nm and high drain current (ID) up to 2.65 mA/µm are achieved.
{"title":"Thermal Studies of BEOL-compatible Top-Gated Atomically Thin ALD In2O3 FETs","authors":"Pai-Ying Liao, S. Alajlouni, M. Si, Zhuocheng Zhang, Zehao Lin, J. Noh, Calista Wilk, A. Shakouri, P. Ye","doi":"10.1109/vlsitechnologyandcir46769.2022.9830279","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830279","url":null,"abstract":"In this work, we investigate the thermal issues of top-gated (TG), ultrathin, atomic layer deposition (ALD) grown, back-end-of-line (BEOL) compatible indium oxide (In2O3) transistors by observation and visualization of the self-heating effect (SHE) using high-resolution thermo-reflectance (TR) measurement. SHE is alleviated by highly resistive silicon (HR Si) substrate with high thermal conductivity (κSi). The increased temperature (ΔT) of the devices on HR Si substrate is roughly 6 times lower than that with SiO2/Si substrate. Furthermore, thermal simulation with a finite-element method exhibits exceptional agreement to ΔT distribution with experimental results. By thermal engineering, TG In2O3 transistors with channel thickness (Tch) of 1.8 nm and high drain current (ID) up to 2.65 mA/µm are achieved.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133538099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830307
K. Cai, S. V. Beek, S. Rao, K. Fan, M. Gupta, V. Nguyen, G. Jayakumar, G. Talmelli, S. Couet, G. Kar
We demonstrate a multi-pillar (MP) spin-orbit torque (SOT)-MRAM concept, which enables lower write current and high-density integration. We experimentally demonstrate the selective write operation of multi-bits in CMOS-compatible 300mm integrated top-pinned perpendicular MTJs. Multiple MTJs on a shared SOT track can be individually selected by gate voltages and independently switched by sub-ns pulses with 30% reduction in operation current. Our concept of selective operations with less transistors and lower writing energy will significantly enhance the density and energy efficiency of SOT-MRAM.
{"title":"Selective operations of multi-pillar SOT-MRAM for high density and low power embedded memories","authors":"K. Cai, S. V. Beek, S. Rao, K. Fan, M. Gupta, V. Nguyen, G. Jayakumar, G. Talmelli, S. Couet, G. Kar","doi":"10.1109/vlsitechnologyandcir46769.2022.9830307","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830307","url":null,"abstract":"We demonstrate a multi-pillar (MP) spin-orbit torque (SOT)-MRAM concept, which enables lower write current and high-density integration. We experimentally demonstrate the selective write operation of multi-bits in CMOS-compatible 300mm integrated top-pinned perpendicular MTJs. Multiple MTJs on a shared SOT track can be individually selected by gate voltages and independently switched by sub-ns pulses with 30% reduction in operation current. Our concept of selective operations with less transistors and lower writing energy will significantly enhance the density and energy efficiency of SOT-MRAM.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"533 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115847773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830204
Tomohiro Akazawa, D. Wu, Kai Sumita, N. Sekine, M. Okano, K. Toprasertpong, Shinichi Takagi, M. Takenaka
We proposed a Si/III-V hybrid waveguide photodetector consisting of an ultrathin InGaAs membrane and Si slot waveguide, enabling low capacitance and high responsivity simultaneously. The strong optical confinement in a Si slot waveguide enhanced optical absorption in the InGaAs membrane. As a result, we successfully demonstrated high responsivity of 1 A/W and sufficiently small capacitance of 1.9 fF to realize a receiver-less (TIA-less) system.
我们提出了一种由超薄InGaAs薄膜和Si槽波导组成的Si/III-V混合波导光电探测器，同时实现了低电容和高响应。硅槽波导中的强光约束增强了InGaAs膜的光吸收。因此，我们成功地展示了1 a /W的高响应性和1.9 fF的足够小的电容，以实现无接收器(TIA-less)系统。
{"title":"Low-capacitance Ultrathin InGaAs Membrane Photodetector on Si Slot Waveguide towards Receiver-less System","authors":"Tomohiro Akazawa, D. Wu, Kai Sumita, N. Sekine, M. Okano, K. Toprasertpong, Shinichi Takagi, M. Takenaka","doi":"10.1109/vlsitechnologyandcir46769.2022.9830204","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830204","url":null,"abstract":"We proposed a Si/III-V hybrid waveguide photodetector consisting of an ultrathin InGaAs membrane and Si slot waveguide, enabling low capacitance and high responsivity simultaneously. The strong optical confinement in a Si slot waveguide enhanced optical absorption in the InGaAs membrane. As a result, we successfully demonstrated high responsivity of 1 A/W and sufficiently small capacitance of 1.9 fF to realize a receiver-less (TIA-less) system.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124385139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830498
A. Khanna, H. Ye, Y. Luo, G. Bajpai, M. Jose, W. Chakraborty, Shimeng Yu, P. Fay, S. Datta
Compute-in-memory (CIM) accelerators based on run-time reconfigurable designs have shown great promise in speeding up deep neural network (DNN) inferencing. Here, we present back-end-of-the-line (BEOL) compatible Indium Tungsten Oxide channel ferroelectric transistors (IWO FeFET) as signal routing switches (RS) for monolithic 3D (M3D) CIM accelerator. We demonstrate 2.45 GHz measured cutoff frequency (fT) for the transistor and greater than 11.5 GHz intrinsic fT by de-embedding transistor extrinsic parasitics obtained through developed small-signal equivalent circuit model. Pass-transistor configuration measurements show less than 250ps of added delay and 15dB of isolation at 2.5GHz between programmed and erased states. Run-time reconfigurable operation of a 4-way routing switch is experimentally demonstrated with excellent selectivity and endurance greater than 1010 cycles. System level benchmarking of a M3D CIM accelerator employing IWO FeFET RS and weights performed on real-word DNN models shows 2.5x improvement in energy efficiency and >10% gain in area efficiency compared to 7nm SRAM design.
{"title":"BEOL Compatible Ferroelectric Routers for Run-time Reconfigurable Compute-in-Memory Accelerators","authors":"A. Khanna, H. Ye, Y. Luo, G. Bajpai, M. Jose, W. Chakraborty, Shimeng Yu, P. Fay, S. Datta","doi":"10.1109/vlsitechnologyandcir46769.2022.9830498","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830498","url":null,"abstract":"Compute-in-memory (CIM) accelerators based on run-time reconfigurable designs have shown great promise in speeding up deep neural network (DNN) inferencing. Here, we present back-end-of-the-line (BEOL) compatible Indium Tungsten Oxide channel ferroelectric transistors (IWO FeFET) as signal routing switches (RS) for monolithic 3D (M3D) CIM accelerator. We demonstrate 2.45 GHz measured cutoff frequency (fT) for the transistor and greater than 11.5 GHz intrinsic fT by de-embedding transistor extrinsic parasitics obtained through developed small-signal equivalent circuit model. Pass-transistor configuration measurements show less than 250ps of added delay and 15dB of isolation at 2.5GHz between programmed and erased states. Run-time reconfigurable operation of a 4-way routing switch is experimentally demonstrated with excellent selectivity and endurance greater than 1010 cycles. System level benchmarking of a M3D CIM accelerator employing IWO FeFET RS and weights performed on real-word DNN models shows 2.5x improvement in energy efficiency and >10% gain in area efficiency compared to 7nm SRAM design.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124735902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830432
S. Venkatesan, James Lee, S. Goh, B. Pile, Daniel Meerovich, J. Mo, Yang Jing, Lucas Soldano, Baochang Xu, Yu Zhang, A. Thean, Yeow Kheng Lim
In this paper, we present a unique hybrid integration platform for wafer scale passive assembly of electronics and photonics devices using a CMOS based Optical Interposer. Our optical interposer enables seamless communications between electronics and photonics chips that are assembled on it using visually assisted passive flip chip bonding techniques. This unique integration platform is the first such platform in the industry adapted to directly modulated lasers and enables the world’s smallest single chip Transmit/Receive Optical engine for 100G-400G optical engines.
{"title":"A Wafer Scale Hybrid Integration Platform for Co-packaged Photonics using a CMOS based Optical InterposerTM","authors":"S. Venkatesan, James Lee, S. Goh, B. Pile, Daniel Meerovich, J. Mo, Yang Jing, Lucas Soldano, Baochang Xu, Yu Zhang, A. Thean, Yeow Kheng Lim","doi":"10.1109/vlsitechnologyandcir46769.2022.9830432","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830432","url":null,"abstract":"In this paper, we present a unique hybrid integration platform for wafer scale passive assembly of electronics and photonics devices using a CMOS based Optical Interposer. Our optical interposer enables seamless communications between electronics and photonics chips that are assembled on it using visually assisted passive flip chip bonding techniques. This unique integration platform is the first such platform in the industry adapted to directly modulated lasers and enables the world’s smallest single chip Transmit/Receive Optical engine for 100G-400G optical engines.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124889461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：