Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830492
P. Schuddinck, F. M. Bufler, Y. Xiang, A. Farokhnejad, G. Mirabelli, A. Vandooren, B. Chehab, A. Gupta, C. Neve, G. Hellings, J. Ryckaert
We evaluate Power-Performance-Area & Cost (PPAC) for nanosheet (NS), forksheet (FS), monolithic & sequential Complementary FET (CFET) at 5 & 4 track (T) designs with tight gate pitch (CPP) & metal pitch (MP). While NS & FS prove unsuitable for 4T designs, CFETs provide a performant & cost-effective 4T solution.
{"title":"PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch","authors":"P. Schuddinck, F. M. Bufler, Y. Xiang, A. Farokhnejad, G. Mirabelli, A. Vandooren, B. Chehab, A. Gupta, C. Neve, G. Hellings, J. Ryckaert","doi":"10.1109/vlsitechnologyandcir46769.2022.9830492","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830492","url":null,"abstract":"We evaluate Power-Performance-Area & Cost (PPAC) for nanosheet (NS), forksheet (FS), monolithic & sequential Complementary FET (CFET) at 5 & 4 track (T) designs with tight gate pitch (CPP) & metal pitch (MP). While NS & FS prove unsuitable for 4T designs, CFETs provide a performant & cost-effective 4T solution.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124684005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830498
A. Khanna, H. Ye, Y. Luo, G. Bajpai, M. Jose, W. Chakraborty, Shimeng Yu, P. Fay, S. Datta
Compute-in-memory (CIM) accelerators based on run-time reconfigurable designs have shown great promise in speeding up deep neural network (DNN) inferencing. Here, we present back-end-of-the-line (BEOL) compatible Indium Tungsten Oxide channel ferroelectric transistors (IWO FeFET) as signal routing switches (RS) for monolithic 3D (M3D) CIM accelerator. We demonstrate 2.45 GHz measured cutoff frequency (fT) for the transistor and greater than 11.5 GHz intrinsic fT by de-embedding transistor extrinsic parasitics obtained through developed small-signal equivalent circuit model. Pass-transistor configuration measurements show less than 250ps of added delay and 15dB of isolation at 2.5GHz between programmed and erased states. Run-time reconfigurable operation of a 4-way routing switch is experimentally demonstrated with excellent selectivity and endurance greater than 1010 cycles. System level benchmarking of a M3D CIM accelerator employing IWO FeFET RS and weights performed on real-word DNN models shows 2.5x improvement in energy efficiency and >10% gain in area efficiency compared to 7nm SRAM design.
{"title":"BEOL Compatible Ferroelectric Routers for Run-time Reconfigurable Compute-in-Memory Accelerators","authors":"A. Khanna, H. Ye, Y. Luo, G. Bajpai, M. Jose, W. Chakraborty, Shimeng Yu, P. Fay, S. Datta","doi":"10.1109/vlsitechnologyandcir46769.2022.9830498","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830498","url":null,"abstract":"Compute-in-memory (CIM) accelerators based on run-time reconfigurable designs have shown great promise in speeding up deep neural network (DNN) inferencing. Here, we present back-end-of-the-line (BEOL) compatible Indium Tungsten Oxide channel ferroelectric transistors (IWO FeFET) as signal routing switches (RS) for monolithic 3D (M3D) CIM accelerator. We demonstrate 2.45 GHz measured cutoff frequency (fT) for the transistor and greater than 11.5 GHz intrinsic fT by de-embedding transistor extrinsic parasitics obtained through developed small-signal equivalent circuit model. Pass-transistor configuration measurements show less than 250ps of added delay and 15dB of isolation at 2.5GHz between programmed and erased states. Run-time reconfigurable operation of a 4-way routing switch is experimentally demonstrated with excellent selectivity and endurance greater than 1010 cycles. System level benchmarking of a M3D CIM accelerator employing IWO FeFET RS and weights performed on real-word DNN models shows 2.5x improvement in energy efficiency and >10% gain in area efficiency compared to 7nm SRAM design.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124735902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830432
S. Venkatesan, James Lee, S. Goh, B. Pile, Daniel Meerovich, J. Mo, Yang Jing, Lucas Soldano, Baochang Xu, Yu Zhang, A. Thean, Yeow Kheng Lim
In this paper, we present a unique hybrid integration platform for wafer scale passive assembly of electronics and photonics devices using a CMOS based Optical Interposer. Our optical interposer enables seamless communications between electronics and photonics chips that are assembled on it using visually assisted passive flip chip bonding techniques. This unique integration platform is the first such platform in the industry adapted to directly modulated lasers and enables the world’s smallest single chip Transmit/Receive Optical engine for 100G-400G optical engines.
{"title":"A Wafer Scale Hybrid Integration Platform for Co-packaged Photonics using a CMOS based Optical InterposerTM","authors":"S. Venkatesan, James Lee, S. Goh, B. Pile, Daniel Meerovich, J. Mo, Yang Jing, Lucas Soldano, Baochang Xu, Yu Zhang, A. Thean, Yeow Kheng Lim","doi":"10.1109/vlsitechnologyandcir46769.2022.9830432","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830432","url":null,"abstract":"In this paper, we present a unique hybrid integration platform for wafer scale passive assembly of electronics and photonics devices using a CMOS based Optical Interposer. Our optical interposer enables seamless communications between electronics and photonics chips that are assembled on it using visually assisted passive flip chip bonding techniques. This unique integration platform is the first such platform in the industry adapted to directly modulated lasers and enables the world’s smallest single chip Transmit/Receive Optical engine for 100G-400G optical engines.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124889461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830334
Yunlong Li, G. Karve, P. Malinowski, J. Kim, Epimitheas Georgitzikis, V. Pejović, M. Lim, L. M. Hagelsieb, R. Puybaret, I. Lieberman, Jiwon Lee, D. Cheyns, P. Heremans, H. Osman, D. Tezcan
Monolithic integration of colloidal quantum dot (CQD) thin-film on 200 mm CMOS wafers is demonstrated. Full pixelation of CQD thin-film photodiodes at wafer level is presented for the first time. We show a low-temperature process flow compatible with standard CMOS fab equipment. The self-aligned pixelation approach is an improvement over a conventional way of having a thin-film absorber layer on pixelated bottom electrodes, and it enables crosstalk reduction as well as multi-stack arrays.
{"title":"Wafer Level Pixelation of Colloidal Quantum Dot Image Sensors","authors":"Yunlong Li, G. Karve, P. Malinowski, J. Kim, Epimitheas Georgitzikis, V. Pejović, M. Lim, L. M. Hagelsieb, R. Puybaret, I. Lieberman, Jiwon Lee, D. Cheyns, P. Heremans, H. Osman, D. Tezcan","doi":"10.1109/vlsitechnologyandcir46769.2022.9830334","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830334","url":null,"abstract":"Monolithic integration of colloidal quantum dot (CQD) thin-film on 200 mm CMOS wafers is demonstrated. Full pixelation of CQD thin-film photodiodes at wafer level is presented for the first time. We show a low-temperature process flow compatible with standard CMOS fab equipment. The self-aligned pixelation approach is an improvement over a conventional way of having a thin-film absorber layer on pixelated bottom electrodes, and it enables crosstalk reduction as well as multi-stack arrays.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123299568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830445
Honam Yoo, Jong-Won Back, Nam-Hun Kim, D. Kwon, Byung-Gook Park, Jong-Ho Lee
We propose for the first time a method for erasing one selected cell in Vertical NAND (VNAND) flash memory. By controlling the voltage applied to the terminals (switch devices and cells) of the VNAND string array, 1-bit erase (GIDL generation) of one selected cell and erase inhibition (GIDL suppression) of unselected cells are successfully verified. Compared to the existing method, the 1-bit erase method reduces the current fluctuation by 17 times at an IBL of 50 nA and reduces the Vth dispersion of >2 V to ~0.2 V or less.
{"title":"First Demonstration of 1-bit Erase in Vertical NAND Flash Memory","authors":"Honam Yoo, Jong-Won Back, Nam-Hun Kim, D. Kwon, Byung-Gook Park, Jong-Ho Lee","doi":"10.1109/vlsitechnologyandcir46769.2022.9830445","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830445","url":null,"abstract":"We propose for the first time a method for erasing one selected cell in Vertical NAND (VNAND) flash memory. By controlling the voltage applied to the terminals (switch devices and cells) of the VNAND string array, 1-bit erase (GIDL generation) of one selected cell and erase inhibition (GIDL suppression) of unselected cells are successfully verified. Compared to the existing method, the 1-bit erase method reduces the current fluctuation by 17 times at an IBL of 50 nA and reduces the Vth dispersion of >2 V to ~0.2 V or less.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123610924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830220
Haiwen Xu, R. Khazaka, Jishen Zhang, Zijie Zheng, Yue Chen, Xiao Gong
For the first time, we have developed a novel growth technique of Si1-xGex having active boron (B) doping concentration (NA) higher than 2×1021 cm-3. We achieve (1) uniform B doping and Ge composition in the epi-growth direction, (2) excellent uniformities in Si1-xGex thickness and resistivity across the entire 300 mm wafer, (3) an ultra-low as-deposited specific contact resistivity (ρc) of 5.1×10-10 Ω-cm2 on the sample with the highest NA of 2.5×1021 cm-3, and (4) successful selective growth on the advanced 3D structures with excellent conformality and thickness controllability.
{"title":"300 mm Wafer-scale In-situ CVD Growth Achieving 5.1×10-10 Ω-cm2 P-Type Contact Resistivity: Record 2.5×1021 cm-3 Active Doping and Demonstration on Highly-Scaled 3D Structures","authors":"Haiwen Xu, R. Khazaka, Jishen Zhang, Zijie Zheng, Yue Chen, Xiao Gong","doi":"10.1109/vlsitechnologyandcir46769.2022.9830220","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830220","url":null,"abstract":"For the first time, we have developed a novel growth technique of Si<inf>1-x</inf>Ge<inf>x</inf> having active boron (B) doping concentration (N<inf>A</inf>) higher than 2×10<sup>21</sup> cm<sup>-3</sup>. We achieve (1) uniform B doping and Ge composition in the epi-growth direction, (2) excellent uniformities in Si<inf>1-x</inf>Ge<inf>x</inf> thickness and resistivity across the entire 300 mm wafer, (3) an ultra-low as-deposited specific contact resistivity (ρ<inf>c</inf>) of 5.1×10<sup>-10</sup> Ω-cm<sup>2</sup> on the sample with the highest N<inf>A</inf> of 2.5×10<sup>21</sup> cm<sup>-3</sup>, and (4) successful selective growth on the advanced 3D structures with excellent conformality and thickness controllability.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122644789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830416
Dong-Jin Chang, S. Ryu
An on-chip background skew calibration technique for time-interleaved (TI) ADCs with relative-prime rotation (RPR) based autocorrelation computation is presented, with which more flexible choice of number of channels and no residual skew accumulation are realized. An 8 × TI 10b 1.4GS/s prototype ADC with fully on-chip calibration achieves an SNDR of 48.2dB at over Nyquist input and a FoM of 33 fJ/c-s in 28-nm FDSOI. The on-chip calibration circuitry takes only 24% of the ADC-core power consumption.
提出了一种基于相对素旋转(RPR)自相关计算的时间交错(TI) adc的片上背景偏度校准技术，该技术可以更灵活地选择通道数，且不存在残余偏度积累。采用全片上校准的8 × TI 10b 1.4GS/s原型ADC在Nyquist输入下的SNDR为48.2dB，在28纳米FDSOI中FoM为33 fJ/c-s。片上校准电路仅占adc核心功耗的24%。
{"title":"A Relative-Prime Rotation Based Fully On-Chip Background Skew Calibration for Time-Interleaved ADCs","authors":"Dong-Jin Chang, S. Ryu","doi":"10.1109/vlsitechnologyandcir46769.2022.9830416","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830416","url":null,"abstract":"An on-chip background skew calibration technique for time-interleaved (TI) ADCs with relative-prime rotation (RPR) based autocorrelation computation is presented, with which more flexible choice of number of channels and no residual skew accumulation are realized. An 8 × TI 10b 1.4GS/s prototype ADC with fully on-chip calibration achieves an SNDR of 48.2dB at over Nyquist input and a FoM of 33 fJ/c-s in 28-nm FDSOI. The on-chip calibration circuitry takes only 24% of the ADC-core power consumption.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124225151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830400
A. Vandooren, N. Parihar, J. Franco, R. Loo, H. Arimura, R. Rodriguez, F. Sebaai, S. Iacovo, K. Vandersmissen, W. Li, G. Mannaert, D. Radisic, E. Rosseel, A. Hikavyy, A. Jourdain, O. Mourey, G. Gaudin, S. Reboh, L. Van-Jodin, G. Besnard, C. Neve, Bich-Yen Nguyen, I. Radu, E. Litta, N. Horiguchi
3D sequential stacking is demonstrated using top tier FDSOI devices on bottom tier bulk finFETs. 3D integration and top-bottom layer interconnectivity is validated through functional 3D via chains, 3D CMOS single inverters and inverter chain with transistors built in the top and bottom layers. Three different Si layer transfer flows, including a low temperature Smart Cut™, are investigated and compared electrically for top tier planar devices. Transfer of bi-axial tensile strained silicon is demonstrated with a 60-80% performance boost of the top tier nMOS device over the unstrained silicon devices. Further process optimization of the low temperature Smart Cut™ transfer provided significant electron and hole mobility recovery of the top tier devices. Impact of the stacking on bottom tier finFET devices is also studied for various bottom gate stacks.
{"title":"Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections","authors":"A. Vandooren, N. Parihar, J. Franco, R. Loo, H. Arimura, R. Rodriguez, F. Sebaai, S. Iacovo, K. Vandersmissen, W. Li, G. Mannaert, D. Radisic, E. Rosseel, A. Hikavyy, A. Jourdain, O. Mourey, G. Gaudin, S. Reboh, L. Van-Jodin, G. Besnard, C. Neve, Bich-Yen Nguyen, I. Radu, E. Litta, N. Horiguchi","doi":"10.1109/vlsitechnologyandcir46769.2022.9830400","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830400","url":null,"abstract":"3D sequential stacking is demonstrated using top tier FDSOI devices on bottom tier bulk finFETs. 3D integration and top-bottom layer interconnectivity is validated through functional 3D via chains, 3D CMOS single inverters and inverter chain with transistors built in the top and bottom layers. Three different Si layer transfer flows, including a low temperature Smart Cut™, are investigated and compared electrically for top tier planar devices. Transfer of bi-axial tensile strained silicon is demonstrated with a 60-80% performance boost of the top tier nMOS device over the unstrained silicon devices. Further process optimization of the low temperature Smart Cut™ transfer provided significant electron and hole mobility recovery of the top tier devices. Impact of the stacking on bottom tier finFET devices is also studied for various bottom gate stacks.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125771863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830350
Wei Zhu, Jian Zhang, Jiawen Wang, Ruitao Wang, Chenguang Li, Kaiyang Wang, Yan Wang
This work presents a packaged 90-to-96GHz 16-Element transceiver phased array. It is constructed using 4-channel silicon beamformers in 65nm CMOS process, external power amplifiers (PAs) and low noise amplifiers in 100nm GaN process as well as Vivaldi antennas on a tsm-ds3 based printed circuit board (PCB). A transformer-and coupled-line-based 8-to-1 power combine technique is proposed in the silicon beamformer to achieve a measured Psat of +18.8dBm with an OP1dB of +15.8dBm and a peak PAE of 14.8% in CMOS. With external GaN PAs, the 16-Element transceiver phased array demonstrates a measured 26° 3-dB beamwidth, +51dBm peak EIRP at Psat and the ability to scan to ±30° in all planes.
{"title":"A Packaged 90-to-96GHz 16-Element Phased Array with 18.8/15.8dBm Psat/OP1dB, 14.8% TX PAE in 65nm CMOS Process and +51dBm Array EIRP","authors":"Wei Zhu, Jian Zhang, Jiawen Wang, Ruitao Wang, Chenguang Li, Kaiyang Wang, Yan Wang","doi":"10.1109/vlsitechnologyandcir46769.2022.9830350","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830350","url":null,"abstract":"This work presents a packaged 90-to-96GHz 16-Element transceiver phased array. It is constructed using 4-channel silicon beamformers in 65nm CMOS process, external power amplifiers (PAs) and low noise amplifiers in 100nm GaN process as well as Vivaldi antennas on a tsm-ds3 based printed circuit board (PCB). A transformer-and coupled-line-based 8-to-1 power combine technique is proposed in the silicon beamformer to achieve a measured Psat of +18.8dBm with an OP1dB of +15.8dBm and a peak PAE of 14.8% in CMOS. With external GaN PAs, the 16-Element transceiver phased array demonstrates a measured 26° 3-dB beamwidth, +51dBm peak EIRP at Psat and the ability to scan to ±30° in all planes.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125925635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830307
K. Cai, S. V. Beek, S. Rao, K. Fan, M. Gupta, V. Nguyen, G. Jayakumar, G. Talmelli, S. Couet, G. Kar
We demonstrate a multi-pillar (MP) spin-orbit torque (SOT)-MRAM concept, which enables lower write current and high-density integration. We experimentally demonstrate the selective write operation of multi-bits in CMOS-compatible 300mm integrated top-pinned perpendicular MTJs. Multiple MTJs on a shared SOT track can be individually selected by gate voltages and independently switched by sub-ns pulses with 30% reduction in operation current. Our concept of selective operations with less transistors and lower writing energy will significantly enhance the density and energy efficiency of SOT-MRAM.
{"title":"Selective operations of multi-pillar SOT-MRAM for high density and low power embedded memories","authors":"K. Cai, S. V. Beek, S. Rao, K. Fan, M. Gupta, V. Nguyen, G. Jayakumar, G. Talmelli, S. Couet, G. Kar","doi":"10.1109/vlsitechnologyandcir46769.2022.9830307","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830307","url":null,"abstract":"We demonstrate a multi-pillar (MP) spin-orbit torque (SOT)-MRAM concept, which enables lower write current and high-density integration. We experimentally demonstrate the selective write operation of multi-bits in CMOS-compatible 300mm integrated top-pinned perpendicular MTJs. Multiple MTJs on a shared SOT track can be individually selected by gate voltages and independently switched by sub-ns pulses with 30% reduction in operation current. Our concept of selective operations with less transistors and lower writing energy will significantly enhance the density and energy efficiency of SOT-MRAM.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115847773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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