Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706507
M. Deloge, B. Allard, P. Candelier, J. Damiens, E. Le-Roux, M. Rafik
Using TBD and Iwearout characterization and modeling, the influence of antifuse bitcell dimensions is evaluated. An analytical model based on silicon measurements and reliability laws allows the comparison of three bitcell architectures fabricated in standard CMOS 40nm (no extra processing). The model yields the time-to-breakdown and the wearout current as a function of the programming voltage and the dimensions of the antifuse bitcell. As a main result, it is demonstrated that a device with a small capacitor area exhibits shorter TBD, lower Iwearout, and hence a lower programming energy. Characterization and modeling are performed for a programming voltage range from 3.5V to 7V with a minimum TBD of 9ns.
{"title":"Understanding the influence of antifuse bitcell dimensions the programming time and energy using an analytical model","authors":"M. Deloge, B. Allard, P. Candelier, J. Damiens, E. Le-Roux, M. Rafik","doi":"10.1109/IIRW.2010.5706507","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706507","url":null,"abstract":"Using TBD and Iwearout characterization and modeling, the influence of antifuse bitcell dimensions is evaluated. An analytical model based on silicon measurements and reliability laws allows the comparison of three bitcell architectures fabricated in standard CMOS 40nm (no extra processing). The model yields the time-to-breakdown and the wearout current as a function of the programming voltage and the dimensions of the antifuse bitcell. As a main result, it is demonstrated that a device with a small capacitor area exhibits shorter TBD, lower Iwearout, and hence a lower programming energy. Characterization and modeling are performed for a programming voltage range from 3.5V to 7V with a minimum TBD of 9ns.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"365 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122923259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706479
C. Slayman
Soft errors from alpha particles and terrestrial neutrons have been an issue in commercial electronic systems for over three decades. Measurement and mitigation techniques are well developed, but recent work highlights new issues that will need to be addressed for deep sub-micrometer technologies. The contribution of thermal neutrons does not appear to be eliminated with BPSG-free processing. In addition, neutrons in the spectral range of 1–10MeV appear to be significant for soft error rates. Charge sharing and multi-node effects will negate some of the redundant circuit designs. As low power devices gain in applications, the impact of soft errors in the sub-threshold region of operation will be important.
{"title":"Soft errors — Past history and recent discoveries","authors":"C. Slayman","doi":"10.1109/IIRW.2010.5706479","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706479","url":null,"abstract":"Soft errors from alpha particles and terrestrial neutrons have been an issue in commercial electronic systems for over three decades. Measurement and mitigation techniques are well developed, but recent work highlights new issues that will need to be addressed for deep sub-micrometer technologies. The contribution of thermal neutrons does not appear to be eliminated with BPSG-free processing. In addition, neutrons in the spectral range of 1–10MeV appear to be significant for soft error rates. Charge sharing and multi-node effects will negate some of the redundant circuit designs. As low power devices gain in applications, the impact of soft errors in the sub-threshold region of operation will be important.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130428323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706480
Shi-Jie Wen, S. Pai, R. Wong, Michael Romain, N. Tam
In this paper, we report the presence of B10 based on SIMS analysis in SRAM arrays in the 90nm to 45nm technology nodes. The physical presence of B10 correlated very well with the thermal neutron soft error rate (SER) sensitivity of SRAM cells. This result confirmed that without BPSG layer in advanced Si technologies, there is still a high possibility of B10 contamination from the Fab process. Furthermore, a root cause of possible B10 source is suggested based on SIMS results.
{"title":"B10 finding and correlation to thermal neutron soft error rate sensitivity for SRAMs in the sub-micron technology","authors":"Shi-Jie Wen, S. Pai, R. Wong, Michael Romain, N. Tam","doi":"10.1109/IIRW.2010.5706480","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706480","url":null,"abstract":"In this paper, we report the presence of B10 based on SIMS analysis in SRAM arrays in the 90nm to 45nm technology nodes. The physical presence of B10 correlated very well with the thermal neutron soft error rate (SER) sensitivity of SRAM cells. This result confirmed that without BPSG layer in advanced Si technologies, there is still a high possibility of B10 contamination from the Fab process. Furthermore, a root cause of possible B10 source is suggested based on SIMS results.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133051149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706503
M. Bashir, Daehyun Kim, S. Lim, L. Milor
Backend time dependent dielectric breakdown (TDDB) degrades the reliability of circuits with copper interconnects. We use test data to develop a methodology to evaluate chip lifetimes, because of backend TDDB, from layout statistics. We identify features in a layout that are critical to backend reliability, present a model to incorporate those features in determining chip lifetimes, and study the effect of different layout optimizations on chip lifetime.
{"title":"TDDB chip reliability in copper interconnects","authors":"M. Bashir, Daehyun Kim, S. Lim, L. Milor","doi":"10.1109/IIRW.2010.5706503","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706503","url":null,"abstract":"Backend time dependent dielectric breakdown (TDDB) degrades the reliability of circuits with copper interconnects. We use test data to develop a methodology to evaluate chip lifetimes, because of backend TDDB, from layout statistics. We identify features in a layout that are critical to backend reliability, present a model to incorporate those features in determining chip lifetimes, and study the effect of different layout optimizations on chip lifetime.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122469090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706472
Tibor Grasser, T. Aichinger, Hans Reisinger, Jacopo Franco, P. Wagner, Michael Nelhiebel, C. Ortolland, B. Kaczer
A number of recent publications explain NBTI to be due to a recoverable and a more permanent component. While a lot of information has been gathered on the recoverable component, the permanent component has been somewhat elusive. We demonstrate that oxide defects commonly linked to the recoverable component also form an important contribution to the permanent component of NBTI. As such, they can contribute to both the threshold voltage shift as well as the charge pumping current. Under favorable conditions, the permanent component can show recovery rates comparable to that of the recoverable component.
{"title":"On the ‘permanent’ component of NBTI","authors":"Tibor Grasser, T. Aichinger, Hans Reisinger, Jacopo Franco, P. Wagner, Michael Nelhiebel, C. Ortolland, B. Kaczer","doi":"10.1109/IIRW.2010.5706472","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706472","url":null,"abstract":"A number of recent publications explain NBTI to be due to a recoverable and a more permanent component. While a lot of information has been gathered on the recoverable component, the permanent component has been somewhat elusive. We demonstrate that oxide defects commonly linked to the recoverable component also form an important contribution to the permanent component of NBTI. As such, they can contribute to both the threshold voltage shift as well as the charge pumping current. Under favorable conditions, the permanent component can show recovery rates comparable to that of the recoverable component.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123870442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706487
Y. M. Randriamihaja, A. Bravaix, V. Huard, D. Rideau, M. Rafik, D. Roy
Degradation modeling is based usually on macroscopic parameters which can yield to wrong conclusions, since similar degradation might result from very different microscopic situations. The focus on degradation modeling at a microscopic level is proposed. Other authors only compare results from different characterization methods on their common measurement area. This paper proposes to use their complementarities to extend the probed areas. A more accurate determination of defects is obtained with multiple characterization method cross-fertilization allowing 1) ascertaining defect localizations, 2) extending probed areas and 3) identifying microscopic differences between similar macroscopic parameters. The tested devices are NMOS transistors with a 5 nm SiO2 gate oxide and with various gate geometries.
{"title":"Multiple microscopic defects characterization methods to improve macroscopic degradation modeling of MOSFETs","authors":"Y. M. Randriamihaja, A. Bravaix, V. Huard, D. Rideau, M. Rafik, D. Roy","doi":"10.1109/IIRW.2010.5706487","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706487","url":null,"abstract":"Degradation modeling is based usually on macroscopic parameters which can yield to wrong conclusions, since similar degradation might result from very different microscopic situations. The focus on degradation modeling at a microscopic level is proposed. Other authors only compare results from different characterization methods on their common measurement area. This paper proposes to use their complementarities to extend the probed areas. A more accurate determination of defects is obtained with multiple characterization method cross-fertilization allowing 1) ascertaining defect localizations, 2) extending probed areas and 3) identifying microscopic differences between similar macroscopic parameters. The tested devices are NMOS transistors with a 5 nm SiO2 gate oxide and with various gate geometries.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124846912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706491
N. Alimardani, J. F. Conley, E. W. Cowell, J. Wager, M. Chin, S. Kilpatrick, M. Dubey
The performance and stability of metal/insulator/metal tunnel diodes was investigated as a function of interfacial roughness using Al, Ir, Pt, and ultra-smooth amorphous multi-metal (ZrCuAlNi) bottom electrodes with uniform Al2O3 tunnel dielectrics deposited via atomic layer deposition. Current density versus field behavior and device yield were found to be a function of interfacial roughness with smoother electrodes exhibiting more ideal behavior and higher percentages of working devices. A preliminary investigation of DC bias stressed devices suggests that interfacial roughness plays a large role in stability and reliability as well.
{"title":"Stability and bias stressing of metal/insulator/metal diodes","authors":"N. Alimardani, J. F. Conley, E. W. Cowell, J. Wager, M. Chin, S. Kilpatrick, M. Dubey","doi":"10.1109/IIRW.2010.5706491","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706491","url":null,"abstract":"The performance and stability of metal/insulator/metal tunnel diodes was investigated as a function of interfacial roughness using Al, Ir, Pt, and ultra-smooth amorphous multi-metal (ZrCuAlNi) bottom electrodes with uniform Al2O3 tunnel dielectrics deposited via atomic layer deposition. Current density versus field behavior and device yield were found to be a function of interfacial roughness with smoother electrodes exhibiting more ideal behavior and higher percentages of working devices. A preliminary investigation of DC bias stressed devices suggests that interfacial roughness plays a large role in stability and reliability as well.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127295849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706484
P. Lamontagne, D. Ney, Y. Wouters
As the interconnect cross-sections are ever scaled down, a particular care must be taken on the tradeoff between increase of current density in the back end of line and reliability to prevent electromigration (EM). Some lever exists as the well-known Blech effect [1]. One can take advantage of the EM induced backflow flux that counters the EM flux. As a consequence, the total net flux in the line is reduced and additional current density in designs can be allowed in short lines. However, the immortality condition is most of the time addressed with a standard test structures ended by two vias [2]–[3]. Designs present complex configurations far from this typical case and the Blech product (jL)c can be deteriorated or enhanced [4]. In the present paper, we present our study of EM performances of short lines ended by an inactive end of line (EOL) at one end of the test structure. Significant differences on the median time to failure (MTF) are observed with respect to the current direction, from a quasi deletion of failure to a significant reduction of the Blech effect. Based on the resistance saturation, a method is proposed to determine effective lengths of inactive EOL configurations corresponding to the standard case.
{"title":"Effect of reservoir on electromigration of short interconnects","authors":"P. Lamontagne, D. Ney, Y. Wouters","doi":"10.1109/IIRW.2010.5706484","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706484","url":null,"abstract":"As the interconnect cross-sections are ever scaled down, a particular care must be taken on the tradeoff between increase of current density in the back end of line and reliability to prevent electromigration (EM). Some lever exists as the well-known Blech effect [1]. One can take advantage of the EM induced backflow flux that counters the EM flux. As a consequence, the total net flux in the line is reduced and additional current density in designs can be allowed in short lines. However, the immortality condition is most of the time addressed with a standard test structures ended by two vias [2]–[3]. Designs present complex configurations far from this typical case and the Blech product (jL)c can be deteriorated or enhanced [4]. In the present paper, we present our study of EM performances of short lines ended by an inactive end of line (EOL) at one end of the test structure. Significant differences on the median time to failure (MTF) are observed with respect to the current direction, from a quasi deletion of failure to a significant reduction of the Blech effect. Based on the resistance saturation, a method is proposed to determine effective lengths of inactive EOL configurations corresponding to the standard case.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126209343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706504
E. Douglas, Chih-Yang Chang, T. Anderson, J. Hite, Liu Lu, C. Lo, B. Chu, D. Cheney, B. Gila, F. Ren, G. Via, P. Whiting, R. Holzworth, K. Jones, Soohwan Jang, S. Pearton
GaN High Electron mobility transistors (HEMTs) were electrically step-stressed under high reverse gate bias conditions. Once a threshold voltage is reached, gate current increases about two orders of magnitude. Though critical voltage was determined to be linear with increasing gate length, electrical simulations show that the maximum electric field was similar at the critical voltage (∼2 MV.cm−1). Electroluminescence and photoluminescence performed on the degraded samples exhibited a decrease in intensity along the periphery of the gate. Transmission electron microscopy shows a thin native oxide layer present under that gate before stressing, and the first stages of gate metal reacting with the underlying AlGaN after stressing.
{"title":"Degradation of sub-micron gate AlGaN/GaN HEMTs due to reverse gate bias","authors":"E. Douglas, Chih-Yang Chang, T. Anderson, J. Hite, Liu Lu, C. Lo, B. Chu, D. Cheney, B. Gila, F. Ren, G. Via, P. Whiting, R. Holzworth, K. Jones, Soohwan Jang, S. Pearton","doi":"10.1109/IIRW.2010.5706504","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706504","url":null,"abstract":"GaN High Electron mobility transistors (HEMTs) were electrically step-stressed under high reverse gate bias conditions. Once a threshold voltage is reached, gate current increases about two orders of magnitude. Though critical voltage was determined to be linear with increasing gate length, electrical simulations show that the maximum electric field was similar at the critical voltage (∼2 MV.cm−1). Electroluminescence and photoluminescence performed on the degraded samples exhibited a decrease in intensity along the periphery of the gate. Transmission electron microscopy shows a thin native oxide layer present under that gate before stressing, and the first stages of gate metal reacting with the underlying AlGaN after stressing.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125305015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706508
F. Cacho, S. Ighilahriz, M. Diop, D. Roy, V. Huard
250GHz SiGe(C) Heterojunction Bipolar Transistor (HBT) is a high performance device with low noise figure and high transconductance particularly required in power RF circuits. Applications are various: 77GHz automotive radars, non invasive imaging in airport for example. In order to achieve such specification, aggressive design leads to use of HBT at high collector current and sometime with VCE bias higher than collector emitter breakdown voltage with open base BVCEo. This last bias condition is known to induce progressive degradation with time and must be taken into account in Design-in-Reliability model. While reverse mode has been widely investigated, reliability of direct mode biased HBT is a new research field. It has been recently investigated [1,2], the underlying damage physics is now identified, the integrity of EB and BC junctions is known to be impacted as illustrated in the simulation of Fig. 1. The present paper aims at presenting a methodology for characterizing the aging of HBT in time and translating the parameters change of its model card.
{"title":"Insights about reliability of Heterojunction Bipolar Transistor under DC stress","authors":"F. Cacho, S. Ighilahriz, M. Diop, D. Roy, V. Huard","doi":"10.1109/IIRW.2010.5706508","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706508","url":null,"abstract":"250GHz SiGe(C) Heterojunction Bipolar Transistor (HBT) is a high performance device with low noise figure and high transconductance particularly required in power RF circuits. Applications are various: 77GHz automotive radars, non invasive imaging in airport for example. In order to achieve such specification, aggressive design leads to use of HBT at high collector current and sometime with VCE bias higher than collector emitter breakdown voltage with open base BVCEo. This last bias condition is known to induce progressive degradation with time and must be taken into account in Design-in-Reliability model. While reverse mode has been widely investigated, reliability of direct mode biased HBT is a new research field. It has been recently investigated [1,2], the underlying damage physics is now identified, the integrity of EB and BC junctions is known to be impacted as illustrated in the simulation of Fig. 1. The present paper aims at presenting a methodology for characterizing the aging of HBT in time and translating the parameters change of its model card.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123541356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：