Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706486
R. Arora, K. Moen, A. Madan, J. Cressler, E. Zhang, D. Fleetwood, peixiong zhao, A. Sutton, H. Nayfeh
We report the hot carrier reliability (HCR) of 45-nm SOI CMOS technology. Body contacted devices are shown to be more reliable than floating-body devices. Two different body-contacting schemes are investigated (T-body and notched T- body). The effects of total dose irradiation on reliability are investigated. Body contacted devices are shown to be more tolerant to radiation than floating-body devices. Asymmetric halo doping devices show less hot carrier degradation than symmetric halo doping devices. In addition, we investigate the dependence of hot carrier reliability on the metal contact spacing of the Source/Drain (S/D) terminals, the PC-PC spacing, and the RF device performance trade-offs that result.
{"title":"Impact of body tie and Source/Drain contact spacing on the hot carrier reliability of 45-nm RF-CMOS","authors":"R. Arora, K. Moen, A. Madan, J. Cressler, E. Zhang, D. Fleetwood, peixiong zhao, A. Sutton, H. Nayfeh","doi":"10.1109/IIRW.2010.5706486","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706486","url":null,"abstract":"We report the hot carrier reliability (HCR) of 45-nm SOI CMOS technology. Body contacted devices are shown to be more reliable than floating-body devices. Two different body-contacting schemes are investigated (T-body and notched T- body). The effects of total dose irradiation on reliability are investigated. Body contacted devices are shown to be more tolerant to radiation than floating-body devices. Asymmetric halo doping devices show less hot carrier degradation than symmetric halo doping devices. In addition, we investigate the dependence of hot carrier reliability on the metal contact spacing of the Source/Drain (S/D) terminals, the PC-PC spacing, and the RF device performance trade-offs that result.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114375674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706488
Andreas Martin, R. Vollertsen, H. Reisinger
The influence of interconnects and the pad stack on measured Metal-Oxide-Semiconductor (MOS) transistor parameter and their reliability degradation cannot always be neglected. The underlying effect is Plasma-Induced-Damage (PID) from the parasitic antennas connected to the MOS gate electrode. Usually, a protection diode is employed to avoid this. However, for some stress and measurement sequences a diode at the gate is not desirable. An alternative method - a layout optimisation is presented and discussed.
{"title":"MOS transistor characteristics and its dependence of plasma charging degradation on the test structure layout for a 0.13µm CMOS technology","authors":"Andreas Martin, R. Vollertsen, H. Reisinger","doi":"10.1109/IIRW.2010.5706488","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706488","url":null,"abstract":"The influence of interconnects and the pad stack on measured Metal-Oxide-Semiconductor (MOS) transistor parameter and their reliability degradation cannot always be neglected. The underlying effect is Plasma-Induced-Damage (PID) from the parasitic antennas connected to the MOS gate electrode. Usually, a protection diode is employed to avoid this. However, for some stress and measurement sequences a diode at the gate is not desirable. An alternative method - a layout optimisation is presented and discussed.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125769720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706483
Jonggook Kim, B. O'Connell, W. K. Teng, M. Poulter
The equation of resistance drift governing oxidation is derived in this paper for Copper-Top (Cu-Top) interconnects to assess reliability of Cu-Top. Our equation is not only demonstrated by thermal storage tests at various temperatures but also characterized by dependence of time, temperature, metal width, and additional dielectric & conductive layers over Cu-Top. As a result, this approach enables the prediction of the accumulated resistance drift under any conditions for a lifetime operation.
{"title":"Copper - top interconnect reliability for mixed signal applications","authors":"Jonggook Kim, B. O'Connell, W. K. Teng, M. Poulter","doi":"10.1109/IIRW.2010.5706483","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706483","url":null,"abstract":"The equation of resistance drift governing oxidation is derived in this paper for Copper-Top (Cu-Top) interconnects to assess reliability of Cu-Top. Our equation is not only demonstrated by thermal storage tests at various temperatures but also characterized by dependence of time, temperature, metal width, and additional dielectric & conductive layers over Cu-Top. As a result, this approach enables the prediction of the accumulated resistance drift under any conditions for a lifetime operation.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131052746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706490
M. Bukhori, T. Grasser, B. Kaczer, H. Reisinger, A. Asenov
We investigate the experimentally observed gate voltage dependence of the step heights induced by charged defects. Taking into account the intrinsic variability source of random dopants, our simulations confirm that the location of the defect with respect to the critical current percolation path affects the response of the trap to the applied gate bias. However, the details of the bias dependence of this response depend on the exact location relative to the percolation path. Furthermore, the impact of the various charge states of the defect on the step heights is investigated.
{"title":"‘Atomistic’ simulation of RTS amplitudes due to single and multiple charged defect states and their interactions","authors":"M. Bukhori, T. Grasser, B. Kaczer, H. Reisinger, A. Asenov","doi":"10.1109/IIRW.2010.5706490","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706490","url":null,"abstract":"We investigate the experimentally observed gate voltage dependence of the step heights induced by charged defects. Taking into account the intrinsic variability source of random dopants, our simulations confirm that the location of the defect with respect to the critical current percolation path affects the response of the trap to the applied gate bias. However, the details of the bias dependence of this response depend on the exact location relative to the percolation path. Furthermore, the impact of the various charge states of the defect on the step heights is investigated.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"80 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128715858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706495
Ben A. Schmid, J. Jia, J. Wolfman, Yu Wang, F. Dhaoui, Huan-Chung Tseng, Sung-Rae Kim, Kin-Sing Lee, Patty Liu, K. Han, C. Hu
We present a study of cycling induced degradation of a two transistor Flash memory cell with a shared floating gate. The cell directly serves as a configurable interconnection switch in a Field Programmable Gate Array (FPGA) fabricated with a 65 nm embedded-Flash process. By optimizing the poly re-oxidation, LDD implant and spacer module, the cell endurance is significantly improved at both the single cell and 1 Mbit test-array levels.
{"title":"Cycling induced degradation of a 65nm FPGA flash memory switch","authors":"Ben A. Schmid, J. Jia, J. Wolfman, Yu Wang, F. Dhaoui, Huan-Chung Tseng, Sung-Rae Kim, Kin-Sing Lee, Patty Liu, K. Han, C. Hu","doi":"10.1109/IIRW.2010.5706495","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706495","url":null,"abstract":"We present a study of cycling induced degradation of a two transistor Flash memory cell with a shared floating gate. The cell directly serves as a configurable interconnection switch in a Field Programmable Gate Array (FPGA) fabricated with a 65 nm embedded-Flash process. By optimizing the poly re-oxidation, LDD implant and spacer module, the cell endurance is significantly improved at both the single cell and 1 Mbit test-array levels.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123173355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706500
B. Devlin, M. Ikeda, K. Asada
The reliable operation against PVT (process, voltage, and temperature) variation and aging effects has been measured of a Gate-Level Pipelined Self Synchronous FPGA (SSFPGA) design in 65nm CMOS. The SSFPGA employs a 38×38 array of 4-input, 3-stage Self Synchronous Configurable Logic blocks. Throughput has been measured at 2.97GHz at 1.2V, with correct operation from 750mV to 1.6V at 25°C. The operation with errors being inserted into the SSFPGA was compared to a conventional synchronous FPGA, which showed the SSFPGA had 4.2 times error free operation. The effect of aging was also measured on the SSFPGA using accelerated cycle between 0 °C and 120 °C at 2V, which showed the SSFPGA has 8% longer correct operation before chip malfunction past a 10% delay margin commonly used in synchronous systems‥
{"title":"Evaluation on the reliable operation of a Gate-Level Pipelined Self Synchronous system against PVT and aging","authors":"B. Devlin, M. Ikeda, K. Asada","doi":"10.1109/IIRW.2010.5706500","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706500","url":null,"abstract":"The reliable operation against PVT (process, voltage, and temperature) variation and aging effects has been measured of a Gate-Level Pipelined Self Synchronous FPGA (SSFPGA) design in 65nm CMOS. The SSFPGA employs a 38×38 array of 4-input, 3-stage Self Synchronous Configurable Logic blocks. Throughput has been measured at 2.97GHz at 1.2V, with correct operation from 750mV to 1.6V at 25°C. The operation with errors being inserted into the SSFPGA was compared to a conventional synchronous FPGA, which showed the SSFPGA had 4.2 times error free operation. The effect of aging was also measured on the SSFPGA using accelerated cycle between 0 °C and 120 °C at 2V, which showed the SSFPGA has 8% longer correct operation before chip malfunction past a 10% delay margin commonly used in synchronous systems‥","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131869537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706485
Andreas Martin, Ludger Borucki, H. Reisinger, C. Schlunder
Introducing a through-silicon-via (TSV) process into an existing technology node additional degradation mechanisms can be expected. The focus of the investigation was on mechanical stress from the TSV on near by MOS devices and plasma charging effects from the processing of the TSV connected to MOS devices. The significance of these additional effects on the MOS transistor reliability is assessed. It is shown that a TSV-process can introduce severe reliability degradation for MOS transistors.
{"title":"Investigation into the effect of a “through silicon via”-process on the MOS transistor reliability of a standard 0.13µm CMOS technology","authors":"Andreas Martin, Ludger Borucki, H. Reisinger, C. Schlunder","doi":"10.1109/IIRW.2010.5706485","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706485","url":null,"abstract":"Introducing a through-silicon-via (TSV) process into an existing technology node additional degradation mechanisms can be expected. The focus of the investigation was on mechanical stress from the TSV on near by MOS devices and plasma charging effects from the processing of the TSV connected to MOS devices. The significance of these additional effects on the MOS transistor reliability is assessed. It is shown that a TSV-process can introduce severe reliability degradation for MOS transistors.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126566993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706501
Soonyoung Lee, S. Baeg, P. Reviriego
The soft error rate of memories is increased by high-energy particles as technology shrinks. Single-error correction codes (SEC), scrubbing techniques and interleaving schemes are the most common approaches for protecting memories from soft errors. It is essential to employ analytical models to guide the selection of interleaving distance; relying on rough estimates may lead to unreasonable design choices. The analytic model proposed in this paper includes row clustering effects of accumulated upsets and was able to estimate the failure probability with only a difference of 0.41% compared to the test data for a 45nm SRAM design.
{"title":"Memory reliability model for accumulated and clustered soft errors","authors":"Soonyoung Lee, S. Baeg, P. Reviriego","doi":"10.1109/IIRW.2010.5706501","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706501","url":null,"abstract":"The soft error rate of memories is increased by high-energy particles as technology shrinks. Single-error correction codes (SEC), scrubbing techniques and interleaving schemes are the most common approaches for protecting memories from soft errors. It is essential to employ analytical models to guide the selection of interleaving distance; relying on rough estimates may lead to unreasonable design choices. The analytic model proposed in this paper includes row clustering effects of accumulated upsets and was able to estimate the failure probability with only a difference of 0.41% compared to the test data for a 45nm SRAM design.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126850691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706514
Hyunho Park, Kyosuk Chae, S. Yamada, Hyung-Suk Kuh, Byoungdeok Choi
In this study we have measured and analyzed characteristics of real transistors on dynamic random access memories (DRAM) including cell transistor by using nano-probing system for improved failure analysis. Measuring results of the conventional pad probing and nano-probing were compared on test element group (TEG) patterns of large transistors. The transistor characteristics of nano-probing results were evaluated for the each layer of DRAM structure with comparing the TEGs pad probing results. We also have measured sheet resistance (Rs) and contact resistance (Rc) on source and drain of real transistor bit line contacts (BLC) by nano-probing with transmission line model (TLM) method. We could find the effect of floating BLC was negligible and the effective resistance was only depending on the facing length of the contact plug bottom.
{"title":"Improved evaluation of DRAM transistors and accurate resistance measurement for real chip contacts by nano-probing technique","authors":"Hyunho Park, Kyosuk Chae, S. Yamada, Hyung-Suk Kuh, Byoungdeok Choi","doi":"10.1109/IIRW.2010.5706514","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706514","url":null,"abstract":"In this study we have measured and analyzed characteristics of real transistors on dynamic random access memories (DRAM) including cell transistor by using nano-probing system for improved failure analysis. Measuring results of the conventional pad probing and nano-probing were compared on test element group (TEG) patterns of large transistors. The transistor characteristics of nano-probing results were evaluated for the each layer of DRAM structure with comparing the TEGs pad probing results. We also have measured sheet resistance (Rs) and contact resistance (Rc) on source and drain of real transistor bit line contacts (BLC) by nano-probing with transmission line model (TLM) method. We could find the effect of floating BLC was negligible and the effective resistance was only depending on the facing length of the contact plug bottom.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129629606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706498
Yao Wang, S. Cotofana
Mean Time To Failure (MTTF) is widely accepted as the main reliability metric in industry. However, several works indicate that MTTF does not accurately capture the reliability characteristics of Integrated Circuits (ICs) and systems given their relatively short operating lifetime. To overcome the MTTF weakness, this paper proposes a novel virtual age based reliability model, which is able to predict the electronic systems Time-To-Failure (TTF). The aging and degrading factors that have an influence on the system's reliability are modeled as cumulative increments of the system's virtual age, and the system's failure point is defined as a proper cut-off cumulative failure rate during its operating lifetime. Thus, system's TTF can be easily estimated based on its virtual age, which reflects the current and historical reliability status of the system. The proposed model is computationally recursive and provides real-time reliability status and prediction, which are critical requirements for enabling reliability-aware resource management and computing.
{"title":"A novel virtual age reliability model for Time-to-Failure prediction","authors":"Yao Wang, S. Cotofana","doi":"10.1109/IIRW.2010.5706498","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706498","url":null,"abstract":"Mean Time To Failure (MTTF) is widely accepted as the main reliability metric in industry. However, several works indicate that MTTF does not accurately capture the reliability characteristics of Integrated Circuits (ICs) and systems given their relatively short operating lifetime. To overcome the MTTF weakness, this paper proposes a novel virtual age based reliability model, which is able to predict the electronic systems Time-To-Failure (TTF). The aging and degrading factors that have an influence on the system's reliability are modeled as cumulative increments of the system's virtual age, and the system's failure point is defined as a proper cut-off cumulative failure rate during its operating lifetime. Thus, system's TTF can be easily estimated based on its virtual age, which reflects the current and historical reliability status of the system. The proposed model is computationally recursive and provides real-time reliability status and prediction, which are critical requirements for enabling reliability-aware resource management and computing.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115468321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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