Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706513
Jae-Gyung Ahn, Ping-Chin Yeh, Jane Sowards, Nick Lo, Jonathan Chang
We present the FEOL reliability checking flow in advanced technology especially with over drive applications. We check gate bias values obtained from SPICE transient simulation against the maximum allowed value, Vg_max, to make sure robust gate dielectric reliability. We set up HSPICE MOSRA simulation procedure to let designers check the impact of BTI and HCI to each MOSFET device and the circuit performance at End-of-Lifetime (EOL). From HCI degradation analysis from HSPICE MOSRA, we obtained a good correlation between HCI damage and slew rate and conditions in which HCI degradation is negligible. We discuss on the selection of the stress conditions and monitor conditions to be checked. We applied HSPICE MOSRA to several over drive applications and were able to successfully justify them with careful modeling for HCI and NCHC in addition to BTI.
{"title":"Design-in reliability for over drive applications in advanced technology","authors":"Jae-Gyung Ahn, Ping-Chin Yeh, Jane Sowards, Nick Lo, Jonathan Chang","doi":"10.1109/IIRW.2010.5706513","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706513","url":null,"abstract":"We present the FEOL reliability checking flow in advanced technology especially with over drive applications. We check gate bias values obtained from SPICE transient simulation against the maximum allowed value, Vg_max, to make sure robust gate dielectric reliability. We set up HSPICE MOSRA simulation procedure to let designers check the impact of BTI and HCI to each MOSFET device and the circuit performance at End-of-Lifetime (EOL). From HCI degradation analysis from HSPICE MOSRA, we obtained a good correlation between HCI damage and slew rate and conditions in which HCI degradation is negligible. We discuss on the selection of the stress conditions and monitor conditions to be checked. We applied HSPICE MOSRA to several over drive applications and were able to successfully justify them with careful modeling for HCI and NCHC in addition to BTI.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124220001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706497
Praveen Navuduri, W. Melton, A. Oen, S. Eilert, C. Abraham, S. Wen
In this work, 65nm NOR flash memory is used for an evaluation of data retention and impact on cell charge based on varying levels of exposure to x-ray waves. A sample of 100 fully tested and configured units were programmed with a physical checkerboard pattern (half programmed, half erased) and exposed to conditions found in industrial x-ray stations. Readouts of the data pattern were done at various stages throughout the experiment and a comparison of cell Vt was performed on a population of worst case cells (lowest Vt on programmed cells, highest Vt on erased cells). Data was collected on a bit by bit basis and plotted as a cumulative probability function. Bakes were also performed to introduce any potential defects not seen initially as part of the exposure - and the readout data was collected for this stage as well. Results indicated there is a correlation on the amount of charge gain and loss seen based on the amount of total radiation incident upon the cells in extreme conditions.
{"title":"Evaluation of x-ray irradiation on 65nm Multi-Level Cell NOR flash technologies","authors":"Praveen Navuduri, W. Melton, A. Oen, S. Eilert, C. Abraham, S. Wen","doi":"10.1109/IIRW.2010.5706497","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706497","url":null,"abstract":"In this work, 65nm NOR flash memory is used for an evaluation of data retention and impact on cell charge based on varying levels of exposure to x-ray waves. A sample of 100 fully tested and configured units were programmed with a physical checkerboard pattern (half programmed, half erased) and exposed to conditions found in industrial x-ray stations. Readouts of the data pattern were done at various stages throughout the experiment and a comparison of cell Vt was performed on a population of worst case cells (lowest Vt on programmed cells, highest Vt on erased cells). Data was collected on a bit by bit basis and plotted as a cumulative probability function. Bakes were also performed to introduce any potential defects not seen initially as part of the exposure - and the readout data was collected for this stage as well. Results indicated there is a correlation on the amount of charge gain and loss seen based on the amount of total radiation incident upon the cells in extreme conditions.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"179 48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122388960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706515
A. Keshavarz, Gregory S. Spawn, Nelson Delos Reyes, Rogelio Mincitar, Laurent F. Dion
This paper shows the sensitivity of the non-volatile memory reliability test to the test structure design and the pad sharing with other devices. Detailed results are presented to show how other devices on the same test structure can interfere with the EEPROM endurance test results and cause dramatic shifts in the data.
{"title":"Complexities of the non-volatile memory reliability testing caused by the test structure","authors":"A. Keshavarz, Gregory S. Spawn, Nelson Delos Reyes, Rogelio Mincitar, Laurent F. Dion","doi":"10.1109/IIRW.2010.5706515","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706515","url":null,"abstract":"This paper shows the sensitivity of the non-volatile memory reliability test to the test structure design and the pad sharing with other devices. Detailed results are presented to show how other devices on the same test structure can interfere with the EEPROM endurance test results and cause dramatic shifts in the data.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"2274 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130258462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706502
T. Melde, R. Hoffmann, E. Yurchuk, J. Paul, T. Mikolajick
In this publication a formula is developed to describe the program level dependent charge loss of charge trapping memory cells. We demonstrate that the retention loss can be calculated using 5 parameters with an excellent agreement to the measured results. The increasing non-linearity of the retention loss for thicker nitride layers is evaluated using this model. In addition, the strong temperature dependency of the TANOS stack is clarified.
{"title":"An empirical model describing the MLC retention of charge trap flash memories","authors":"T. Melde, R. Hoffmann, E. Yurchuk, J. Paul, T. Mikolajick","doi":"10.1109/IIRW.2010.5706502","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706502","url":null,"abstract":"In this publication a formula is developed to describe the program level dependent charge loss of charge trapping memory cells. We demonstrate that the retention loss can be calculated using 5 parameters with an excellent agreement to the measured results. The increasing non-linearity of the retention loss for thicker nitride layers is evaluated using this model. In addition, the strong temperature dependency of the TANOS stack is clarified.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124457395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706510
J. Heidecker, M. White, M. Cooper, D. Sheldon, F. Irom, D. Nguyen
Screening and qualification of a 128 Gb multi-level-cell (MLC) NAND Flash device for the Soil Moisture Passive Active (SMAP) mission (http://smap.jpl.nasa.gov/) is presented here. The MLC technology used in this high density device requires testing above and beyond the typical space test flow.
{"title":"Qualification of 128 Gb MLC NAND Flash for SMAP space mission","authors":"J. Heidecker, M. White, M. Cooper, D. Sheldon, F. Irom, D. Nguyen","doi":"10.1109/IIRW.2010.5706510","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706510","url":null,"abstract":"Screening and qualification of a 128 Gb multi-level-cell (MLC) NAND Flash device for the Soil Moisture Passive Active (SMAP) mission (http://smap.jpl.nasa.gov/) is presented here. The MLC technology used in this high density device requires testing above and beyond the typical space test flow.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128095059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706474
H. Reisinger, Tibor Grasser, K. Hofmann, W. Gustin, C. Schlunder
BTI is shown to be the most important device degradation mechanism for combinational logic. Significant benefits regarding lifetime predictions and the total effort in measurement time can be expected from measurements minimizing recovery by a short measuring delay or/and assessments being done with AC stress for applications ensuring AC operation only.
{"title":"The impact of recovery on BTI reliability assessments","authors":"H. Reisinger, Tibor Grasser, K. Hofmann, W. Gustin, C. Schlunder","doi":"10.1109/IIRW.2010.5706474","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706474","url":null,"abstract":"BTI is shown to be the most important device degradation mechanism for combinational logic. Significant benefits regarding lifetime predictions and the total effort in measurement time can be expected from measurements minimizing recovery by a short measuring delay or/and assessments being done with AC stress for applications ensuring AC operation only.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114957112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706489
L. Negre, D. Roy, S. Boret, P. Scheer, N. Kauffmann, D. Gloria, G. Ghibaudo
RF reliability is becoming an increasing concern for actual technology platforms. In this context, small signal equivalent circuit degradation under hot carrier stress is investigated. It is shown that some lumped elements such as the conductance, the transconductance, the gate-to-drain capacitance, and series resistances are degraded. The application of corrections based on physical phenomenon explains the major part of the hot carrier impact on the small signal equivalent circuit. Furthermore, the overlap gate-to-drain capacitance degradation is emphasized.
{"title":"Hot carrier impact on the small signal equivalent circuit","authors":"L. Negre, D. Roy, S. Boret, P. Scheer, N. Kauffmann, D. Gloria, G. Ghibaudo","doi":"10.1109/IIRW.2010.5706489","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706489","url":null,"abstract":"RF reliability is becoming an increasing concern for actual technology platforms. In this context, small signal equivalent circuit degradation under hot carrier stress is investigated. It is shown that some lumped elements such as the conductance, the transconductance, the gate-to-drain capacitance, and series resistances are degraded. The application of corrections based on physical phenomenon explains the major part of the hot carrier impact on the small signal equivalent circuit. Furthermore, the overlap gate-to-drain capacitance degradation is emphasized.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116483040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706512
T. Gupta, C. Bertolini, O. Héron, N. Ventroux, T. Zimmer, F. Marc
In semiconductor industry, designing a SoC is a complex process. Designing reliable SoCs includes study of various configurations involving different operating conditions and considering both hard and soft errors. Designers at higher level of abstraction already have many ways to remove or handle soft errors. This paper aims at analyzing hard errors at functional level. We propose a methodology using state of the art failure models and simulators to provide the cumulative failure rate for a processor simulated at functional level.
{"title":"RAAPS: Reliability Aware ArchC based Processor Simulator","authors":"T. Gupta, C. Bertolini, O. Héron, N. Ventroux, T. Zimmer, F. Marc","doi":"10.1109/IIRW.2010.5706512","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706512","url":null,"abstract":"In semiconductor industry, designing a SoC is a complex process. Designing reliable SoCs includes study of various configurations involving different operating conditions and considering both hard and soft errors. Designers at higher level of abstraction already have many ways to remove or handle soft errors. This paper aims at analyzing hard errors at functional level. We propose a methodology using state of the art failure models and simulators to provide the cumulative failure rate for a processor simulated at functional level.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"256 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122856407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706481
R. Wong, Shi-Jie Wen, P. Su, B. Dwyer-McNally
Measured alpha particle emissions from packaging materials have been used to calculate the Soft Error Rate of silicon components. The packaging materials have been assumed to be the only alpha emitter and the layers on top of the silicon have been assumed to be the alpha attenuators. This paper measures the alpha emission of the fully processed wafers from different vendors and shows that these wafers are significant alpha emitters. Because the alpha emitters in this case are very close to the silicon, there are no shielding layers to attenuate the lower energy alpha particle. The entire alpha particle energy spectrum, from both package materials to the inside wafers, must be considered, when calculating the alpha flux at the silicon die.
{"title":"Alpha emission of fully processed silicon wafers","authors":"R. Wong, Shi-Jie Wen, P. Su, B. Dwyer-McNally","doi":"10.1109/IIRW.2010.5706481","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706481","url":null,"abstract":"Measured alpha particle emissions from packaging materials have been used to calculate the Soft Error Rate of silicon components. The packaging materials have been assumed to be the only alpha emitter and the layers on top of the silicon have been assumed to be the alpha attenuators. This paper measures the alpha emission of the fully processed wafers from different vendors and shows that these wafers are significant alpha emitters. Because the alpha emitters in this case are very close to the silicon, there are no shielding layers to attenuate the lower energy alpha particle. The entire alpha particle energy spectrum, from both package materials to the inside wafers, must be considered, when calculating the alpha flux at the silicon die.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121892019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706505
Jongsun Bae, S. Baeg, S. Wen, R. Wong
The capacitance between adjacent SRAM cells due to defectivity can increase in smaller geometry technologies. However, the abnormal behaviors due to such defective capacitance in SRAM are often neglected and can cause NTF (No Trouble Found) failures. The effective testing or calibration methods for such capacitance due to defects are not easily available in today's manufacturing. In this paper, a 3-D field solver was used to see the potential ranges of the defective capacitance. The crosstalk AC current through the coupling capacitance, which is referred to as cell coupling capacitor (CCCP) is newly modeled as a current source to build modified SNM (Static Noise Margin). The two metrics, SNM and VDDMIN show that the reliability under the CCCP can be significantly degraded during memory operations. Even with a marginal CCCP, SNM variation is 40mV at a read operation and VDDMIN shift is 110mV at a write operation in a 65nm SRAM cell.
{"title":"SRAM cell reliability degradations due to cell crosstalk","authors":"Jongsun Bae, S. Baeg, S. Wen, R. Wong","doi":"10.1109/IIRW.2010.5706505","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706505","url":null,"abstract":"The capacitance between adjacent SRAM cells due to defectivity can increase in smaller geometry technologies. However, the abnormal behaviors due to such defective capacitance in SRAM are often neglected and can cause NTF (No Trouble Found) failures. The effective testing or calibration methods for such capacitance due to defects are not easily available in today's manufacturing. In this paper, a 3-D field solver was used to see the potential ranges of the defective capacitance. The crosstalk AC current through the coupling capacitance, which is referred to as cell coupling capacitor (CCCP) is newly modeled as a current source to build modified SNM (Static Noise Margin). The two metrics, SNM and VDDMIN show that the reliability under the CCCP can be significantly degraded during memory operations. Even with a marginal CCCP, SNM variation is 40mV at a read operation and VDDMIN shift is 110mV at a write operation in a 65nm SRAM cell.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131291092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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