Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410638
S. Bose, P. Agrawal, V. Agrawal
The authors present an algorithmic derivation of logic systems for solving path delay test problems. In these logic systems, the state of a signal represents any possible situation that can occur during two consecutive vectors. Starting from a set of valid input states, a state transition graph is constructed to enumerate all possible states produced by Boolean gates. Specifics of the test problem are used for distinguishability criteria and to minimize the number of states. For test generation in combinational or sequential circuits, the authors use the algorithm to obtain optimal logic systems. They define optimality as to the smallest number of logic states that provide the least possible ambiguity. The ten-value logic of Fuchs et al. is found to be optimal for generating tests for single path delay faults but gives ambiguous results for multiple path activation. A new 23-value logic is derived as an optimal system for solving the multiple path problem as well as the delay test generation problem of sequential circuits. The limitations and capabilities of various logic systems are illustrated.<>
{"title":"Logic systems for path delay test generation","authors":"S. Bose, P. Agrawal, V. Agrawal","doi":"10.1109/EURDAC.1993.410638","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410638","url":null,"abstract":"The authors present an algorithmic derivation of logic systems for solving path delay test problems. In these logic systems, the state of a signal represents any possible situation that can occur during two consecutive vectors. Starting from a set of valid input states, a state transition graph is constructed to enumerate all possible states produced by Boolean gates. Specifics of the test problem are used for distinguishability criteria and to minimize the number of states. For test generation in combinational or sequential circuits, the authors use the algorithm to obtain optimal logic systems. They define optimality as to the smallest number of logic states that provide the least possible ambiguity. The ten-value logic of Fuchs et al. is found to be optimal for generating tests for single path delay faults but gives ambiguous results for multiple path activation. A new 23-value logic is derived as an optimal system for solving the multiple path problem as well as the delay test generation problem of sequential circuits. The limitations and capabilities of various logic systems are illustrated.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122242987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410685
W. Damm, B. Josko, R. Schlör
The VHDL standard gives only an informal description of the semantics of VHDL. To apply formal verification techniques, a precise semantics definition is necessary. A formal semantics for VHDL based on interpreted Petri nets is defined. The presented semantics is compositional and provides a link to automatic verification methods for VHDL based designs.<>
{"title":"A net-based semantics for VHDL","authors":"W. Damm, B. Josko, R. Schlör","doi":"10.1109/EURDAC.1993.410685","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410685","url":null,"abstract":"The VHDL standard gives only an informal description of the semantics of VHDL. To apply formal verification techniques, a precise semantics definition is necessary. A formal semantics for VHDL based on interpreted Petri nets is defined. The presented semantics is compositional and provides a link to automatic verification methods for VHDL based designs.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126686554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410659
C. Munk, Pierre Ukelo, A. Vachoux, D. Mlynek
This paper presents a software environment for the rapid prototyping of CAD systems, the Global Control Environment (GCE). It basically provides a mechanism to define the user interface and to study possible interactions between internal applications without having to cope with a programming language. The GCE tool is currently used for the design of the MODES system, an environment for the automatic generation of behavioral models from high-level specifications.<>
{"title":"The MODES Global Control Environment - A tool for rapid prototyping","authors":"C. Munk, Pierre Ukelo, A. Vachoux, D. Mlynek","doi":"10.1109/EURDAC.1993.410659","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410659","url":null,"abstract":"This paper presents a software environment for the rapid prototyping of CAD systems, the Global Control Environment (GCE). It basically provides a mechanism to define the user interface and to study possible interactions between internal applications without having to cope with a programming language. The GCE tool is currently used for the design of the MODES system, an environment for the automatic generation of behavioral models from high-level specifications.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125236053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410675
M. Masud, M. Karunaratne
Modern complex ASIC chips contain numerous registers, counters, and control units (state sequencers), making it extremely difficult for gate level sequential circuit test generation techniques to generate good test vectors in a reasonable time. The authors present a methodology which uses functional information extracted from a VHDL behavior model to drive the test generation process. As opposed to various behavior test generation systems proposed recently which use behavior fault models, the proposed system uses the standard stuck-at fault model of logic elements. Thus, the fault coverage figures reported by the system can readily be verified by other commercially available fault simulators.<>
{"title":"Test generation based on synthesizable VHDL descriptions","authors":"M. Masud, M. Karunaratne","doi":"10.1109/EURDAC.1993.410675","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410675","url":null,"abstract":"Modern complex ASIC chips contain numerous registers, counters, and control units (state sequencers), making it extremely difficult for gate level sequential circuit test generation techniques to generate good test vectors in a reasonable time. The authors present a methodology which uses functional information extracted from a VHDL behavior model to drive the test generation process. As opposed to various behavior test generation systems proposed recently which use behavior fault models, the proposed system uses the standard stuck-at fault model of logic elements. Thus, the fault coverage figures reported by the system can readily be verified by other commercially available fault simulators.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125080809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410672
Gregory Schulte, P. Tong, S. Rusu, Stuart Taylor
A unified timing database for VLSI (very large scale integration) design is presented. The approach has been successfully used for the design of a three million transistor microprocessor. The database and timing methodology are oriented towards, but not restricted to, the top-down design style. Emphasis is placed upon integration with other timing tools such as circuit simulators, logic synthesis tools, and static timing analyzers.<>
{"title":"TONIC: A timing database for VLSI design","authors":"Gregory Schulte, P. Tong, S. Rusu, Stuart Taylor","doi":"10.1109/EURDAC.1993.410672","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410672","url":null,"abstract":"A unified timing database for VLSI (very large scale integration) design is presented. The approach has been successfully used for the design of a three million transistor microprocessor. The database and timing methodology are oriented towards, but not restricted to, the top-down design style. Emphasis is placed upon integration with other timing tools such as circuit simulators, logic synthesis tools, and static timing analyzers.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134396037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410649
M. J. Aguado, M. Corbalan, E. D. L. Torre, C. López-Barrio
The structure of the distributed computing ATPG system DPLATON is presented, with special emphasis on the distribution strategy basis and the communication structures implemented. The proposed system is based on a dynamic fault list partition criterion. The standard remote procedure call (RPC) and external data representation (XDR) mechanisms have been adapted to construct an efficient dynamic distributed implementation. Reduced test sets and important CPU time speedup factors are reported.<>
{"title":"A dynamic communication strategy for the distributed ATPG system DPLATON","authors":"M. J. Aguado, M. Corbalan, E. D. L. Torre, C. López-Barrio","doi":"10.1109/EURDAC.1993.410649","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410649","url":null,"abstract":"The structure of the distributed computing ATPG system DPLATON is presented, with special emphasis on the distribution strategy basis and the communication structures implemented. The proposed system is based on a dynamic fault list partition criterion. The standard remote procedure call (RPC) and external data representation (XDR) mechanisms have been adapted to construct an efficient dynamic distributed implementation. Reduced test sets and important CPU time speedup factors are reported.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"418 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134635726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410631
M. Brielmann, B. Kleinjohann
One of the main challenges of information technology is the development of heterogeneous systems consisting of digital and analog parts. A technique for the common modeling of the different system parts and their interfaces that allows development all parts of the system in a consistent manner is shown. This technique is based on extensions of predicate/transition nets. Based on this model tools for the specification and evaluation of heterogeneous systems are built.<>
{"title":"A formal model for coupling computer based system and physical systems","authors":"M. Brielmann, B. Kleinjohann","doi":"10.1109/EURDAC.1993.410631","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410631","url":null,"abstract":"One of the main challenges of information technology is the development of heterogeneous systems consisting of digital and analog parts. A technique for the common modeling of the different system parts and their interfaces that allows development all parts of the system in a consistent manner is shown. This technique is based on extensions of predicate/transition nets. Based on this model tools for the specification and evaluation of heterogeneous systems are built.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133085526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410644
U. Prabhu, B. Pangrle
This paper addresses the following problem: given a set of functional units and a data introduction interval, find a pipelined schedule for the given behavioral description (which may contain conditionals) that minimizes the number of pipeline stages. The approach taken to solve this problem is to do conditional and unconditional hardware sharing simultaneously while scheduling. A two-phase algorithm is used. The first phase tries to find a feasible solution (if it exists), while the second phase improves the initial solution by reducing the number of pipeline stages and the number of pipeline registers. The fast heuristics used to do this have been found to give excellent results.<>
{"title":"Conditional and unconditional hardware sharing in pipeline synthesis","authors":"U. Prabhu, B. Pangrle","doi":"10.1109/EURDAC.1993.410644","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410644","url":null,"abstract":"This paper addresses the following problem: given a set of functional units and a data introduction interval, find a pipelined schedule for the given behavioral description (which may contain conditionals) that minimizes the number of pipeline stages. The approach taken to solve this problem is to do conditional and unconditional hardware sharing simultaneously while scheduling. A two-phase algorithm is used. The first phase tries to find a feasible solution (if it exists), while the second phase improves the initial solution by reducing the number of pipeline stages and the number of pipeline registers. The fast heuristics used to do this have been found to give excellent results.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"34 26","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113941833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410700
P. M. Kist, R. V. Leuken, M. Sim
The CFI (CAD Framework initiative) organization aims to provide solutions for concurrent engineering by defining a set of standard textual specifications for interfaces that should enable ECAD tool consumers to incorporate tools from various vendors. The most mature of these specifications is the DRPI, a programming interface which specifies the data schema and functions for manipulating elementary ECAD objects. The authors' objective was to implement the DRPI specification utilizing the NELSIS CAD framework. NELSIS supports a large grained schema; there is just one entity type (called the design object) for representing the design data. Additional entities in the schema provide relational information about the design object. In contrast, the DRPI data schema is fine grained; all data are represented explicitly and homogeneously by many entities. To bridge the gap, an object manager is required. The authors have coupled DRPI to NELSIS in two different ways. The first uses a custom-built dedicated object manager implemented in C, and the second uses a general purpose object oriented manager implemented in C++. The focus is on the schema mapping. The authors provide suggestions for enhancing the CFI schema, and highlight the problems and solutions of performing the mapping. They conclude with several open questions and recommendations.<>
{"title":"Aspects of realizing the CFI design representation specification in the NELSIS framework","authors":"P. M. Kist, R. V. Leuken, M. Sim","doi":"10.1109/EURDAC.1993.410700","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410700","url":null,"abstract":"The CFI (CAD Framework initiative) organization aims to provide solutions for concurrent engineering by defining a set of standard textual specifications for interfaces that should enable ECAD tool consumers to incorporate tools from various vendors. The most mature of these specifications is the DRPI, a programming interface which specifies the data schema and functions for manipulating elementary ECAD objects. The authors' objective was to implement the DRPI specification utilizing the NELSIS CAD framework. NELSIS supports a large grained schema; there is just one entity type (called the design object) for representing the design data. Additional entities in the schema provide relational information about the design object. In contrast, the DRPI data schema is fine grained; all data are represented explicitly and homogeneously by many entities. To bridge the gap, an object manager is required. The authors have coupled DRPI to NELSIS in two different ways. The first uses a custom-built dedicated object manager implemented in C, and the second uses a general purpose object oriented manager implemented in C++. The focus is on the schema mapping. The authors provide suggestions for enhancing the CFI schema, and highlight the problems and solutions of performing the mapping. They conclude with several open questions and recommendations.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131235228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410611
Y. Saab
This paper describes a new partitioning algorithm, BISECT, which is an extension of the Fiduccia-Mattheyses (FM) algorithm that recursively combines clustering and iterative improvement. A post analysis of sequences of moves in one pass generates disjoint subsets of nodes for clustering. After clustering BISECT is applied again on the compacted circuit. BISECT is stabler, achieves results that can be up to 73 times better than FM, and runs in linear time under suitably mild assumptions. BISECT also performs well in comparison with the Kernighan-Lin algorithm and simulated annealing. The empirical results show that BISECT is stable and is not very sensitive to the initial partition. For many random sparse graphs, BISECT achieves 0-cut bisections (balanced partitions).<>
{"title":"Post-analysis-based clustering dramatically improves the Fiduccia-Mattheyses algorithm","authors":"Y. Saab","doi":"10.1109/EURDAC.1993.410611","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410611","url":null,"abstract":"This paper describes a new partitioning algorithm, BISECT, which is an extension of the Fiduccia-Mattheyses (FM) algorithm that recursively combines clustering and iterative improvement. A post analysis of sequences of moves in one pass generates disjoint subsets of nodes for clustering. After clustering BISECT is applied again on the compacted circuit. BISECT is stabler, achieves results that can be up to 73 times better than FM, and runs in linear time under suitably mild assumptions. BISECT also performs well in comparison with the Kernighan-Lin algorithm and simulated annealing. The empirical results show that BISECT is stable and is not very sensitive to the initial partition. For many random sparse graphs, BISECT achieves 0-cut bisections (balanced partitions).<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127189116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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