Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410644
U. Prabhu, B. Pangrle
This paper addresses the following problem: given a set of functional units and a data introduction interval, find a pipelined schedule for the given behavioral description (which may contain conditionals) that minimizes the number of pipeline stages. The approach taken to solve this problem is to do conditional and unconditional hardware sharing simultaneously while scheduling. A two-phase algorithm is used. The first phase tries to find a feasible solution (if it exists), while the second phase improves the initial solution by reducing the number of pipeline stages and the number of pipeline registers. The fast heuristics used to do this have been found to give excellent results.<>
{"title":"Conditional and unconditional hardware sharing in pipeline synthesis","authors":"U. Prabhu, B. Pangrle","doi":"10.1109/EURDAC.1993.410644","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410644","url":null,"abstract":"This paper addresses the following problem: given a set of functional units and a data introduction interval, find a pipelined schedule for the given behavioral description (which may contain conditionals) that minimizes the number of pipeline stages. The approach taken to solve this problem is to do conditional and unconditional hardware sharing simultaneously while scheduling. A two-phase algorithm is used. The first phase tries to find a feasible solution (if it exists), while the second phase improves the initial solution by reducing the number of pipeline stages and the number of pipeline registers. The fast heuristics used to do this have been found to give excellent results.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"34 26","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113941833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410700
P. M. Kist, R. V. Leuken, M. Sim
The CFI (CAD Framework initiative) organization aims to provide solutions for concurrent engineering by defining a set of standard textual specifications for interfaces that should enable ECAD tool consumers to incorporate tools from various vendors. The most mature of these specifications is the DRPI, a programming interface which specifies the data schema and functions for manipulating elementary ECAD objects. The authors' objective was to implement the DRPI specification utilizing the NELSIS CAD framework. NELSIS supports a large grained schema; there is just one entity type (called the design object) for representing the design data. Additional entities in the schema provide relational information about the design object. In contrast, the DRPI data schema is fine grained; all data are represented explicitly and homogeneously by many entities. To bridge the gap, an object manager is required. The authors have coupled DRPI to NELSIS in two different ways. The first uses a custom-built dedicated object manager implemented in C, and the second uses a general purpose object oriented manager implemented in C++. The focus is on the schema mapping. The authors provide suggestions for enhancing the CFI schema, and highlight the problems and solutions of performing the mapping. They conclude with several open questions and recommendations.<>
{"title":"Aspects of realizing the CFI design representation specification in the NELSIS framework","authors":"P. M. Kist, R. V. Leuken, M. Sim","doi":"10.1109/EURDAC.1993.410700","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410700","url":null,"abstract":"The CFI (CAD Framework initiative) organization aims to provide solutions for concurrent engineering by defining a set of standard textual specifications for interfaces that should enable ECAD tool consumers to incorporate tools from various vendors. The most mature of these specifications is the DRPI, a programming interface which specifies the data schema and functions for manipulating elementary ECAD objects. The authors' objective was to implement the DRPI specification utilizing the NELSIS CAD framework. NELSIS supports a large grained schema; there is just one entity type (called the design object) for representing the design data. Additional entities in the schema provide relational information about the design object. In contrast, the DRPI data schema is fine grained; all data are represented explicitly and homogeneously by many entities. To bridge the gap, an object manager is required. The authors have coupled DRPI to NELSIS in two different ways. The first uses a custom-built dedicated object manager implemented in C, and the second uses a general purpose object oriented manager implemented in C++. The focus is on the schema mapping. The authors provide suggestions for enhancing the CFI schema, and highlight the problems and solutions of performing the mapping. They conclude with several open questions and recommendations.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131235228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410671
Gabriele Pulini, S. Hamacher
The importance of test in ASIC and IC design is discussed, and some new design-for-test (DFT) strategies are presented. The advantages of a specific method for test vector creation and validation that tightly links two scan-test tools into the target design flow are described. These tools are a sequential, partial-scan automatic test pattern generator (ATPG) and an ATPG optimized for full-scan designs. Some customer results with these tools are presented as well.<>
{"title":"Next generation environment for extremely fast test pattern generation","authors":"Gabriele Pulini, S. Hamacher","doi":"10.1109/EURDAC.1993.410671","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410671","url":null,"abstract":"The importance of test in ASIC and IC design is discussed, and some new design-for-test (DFT) strategies are presented. The advantages of a specific method for test vector creation and validation that tightly links two scan-test tools into the target design flow are described. These tools are a sequential, partial-scan automatic test pattern generator (ATPG) and an ATPG optimized for full-scan designs. Some customer results with these tools are presented as well.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"1 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134025614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410637
Joao Marques-Silva, K. Sakallah
The authors describe a new two-step approach for determining the delay of the longest statically sensitizable path(s) in a combinational circuit. In the first step, the conditions for sensitizing all paths with the same path delay, D, are derived. In the second step, these conditions are checked for consistency by a Boolean satisfiability algorithm. This approach is unique in that it enumerates paths implicitly, giving it a decided performance edge over explicit path enumeration methods. The authors describe an implementation of this approach in an experimental timing analysis program, STA, and present preliminary results of its application to a representative set of benchmarks.<>
{"title":"Concurrent path sensitization in timing analysis","authors":"Joao Marques-Silva, K. Sakallah","doi":"10.1109/EURDAC.1993.410637","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410637","url":null,"abstract":"The authors describe a new two-step approach for determining the delay of the longest statically sensitizable path(s) in a combinational circuit. In the first step, the conditions for sensitizing all paths with the same path delay, D, are derived. In the second step, these conditions are checked for consistency by a Boolean satisfiability algorithm. This approach is unique in that it enumerates paths implicitly, giving it a decided performance edge over explicit path enumeration methods. The authors describe an implementation of this approach in an experimental timing analysis program, STA, and present preliminary results of its application to a representative set of benchmarks.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129114189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410694
D. Arvind
A new model is presented for the simulation of large and complex systems by exploiting concurrency. Composite ELSA is a distributed asynchronous event-driven simulation model which combines the conservative and optimistic synchronization protocols, while preserving their respective advantages. This model assigns synchronization classes to processes or a hierarchy of processes, which are based on attributes of conservatism or degree of optimism. These attributes can be dynamically updated during the course of simulation, enabling processes to switch smoothly between synchronization classes. A locally optimistic synchronization protocol is introduced, and comparisons are made with two traditional protocols for parallel logic simulation on distributed memory MIMD machines.<>
{"title":"Locally optimistic methods of concurrent simulation","authors":"D. Arvind","doi":"10.1109/EURDAC.1993.410694","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410694","url":null,"abstract":"A new model is presented for the simulation of large and complex systems by exploiting concurrency. Composite ELSA is a distributed asynchronous event-driven simulation model which combines the conservative and optimistic synchronization protocols, while preserving their respective advantages. This model assigns synchronization classes to processes or a hierarchy of processes, which are based on attributes of conservatism or degree of optimism. These attributes can be dynamically updated during the course of simulation, enabling processes to switch smoothly between synchronization classes. A locally optimistic synchronization protocol is introduced, and comparisons are made with two traditional protocols for parallel logic simulation on distributed memory MIMD machines.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116414795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410646
I. Pomeranz, S. Reddy
The authors consider the problem of diagnosing implementation errors in synchronous sequential circuits described by state tables. The diagnosis problem is formulated so as to provide the erroneously implemented entries of the state table, which are useful for the purposes of debugging the synthesis procedure. The diagnosis procedure developed is not limited to a specific error model and no bound is set on error multiplicity. Experimental results are presented to show the effectiveness of this procedure. The experiments indicate that state tables with certain properties make their implementations more amenable to diagnosis than others. These properties are used as guidelines for synthesis.<>
{"title":"A method for diagnosing implementation errors in synchronous sequential circuits and its implications on synthesis","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/EURDAC.1993.410646","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410646","url":null,"abstract":"The authors consider the problem of diagnosing implementation errors in synchronous sequential circuits described by state tables. The diagnosis problem is formulated so as to provide the erroneously implemented entries of the state table, which are useful for the purposes of debugging the synthesis procedure. The diagnosis procedure developed is not limited to a specific error model and no bound is set on error multiplicity. Experimental results are presented to show the effectiveness of this procedure. The experiments indicate that state tables with certain properties make their implementations more amenable to diagnosis than others. These properties are used as guidelines for synthesis.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125837697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410634
Gilles Fourneris, N. Bekkara, J. Benkoski, L. Zullino, Dino Spatafora, G. Martino
A methodology to automate DMOS layout generation starting from electrical specifications is presented. The main features of the Demosthenes technology independent layout generator that make it possible to synthesize lateral and vertical DMOS in different low and high voltage technologies are described. The built-in electrical model used by the generator to extract the device layout resistance is exposed and the accuracy of the model, ranging from 1% to 15%, is reported, according to comparisons with silicon measurements. In the future, the Demosthenes generator will be extended to support the next generation of BCD technology. In addition, electrical modeling capabilities will be improved by generating detailed electrical simulation models that make it possible to accurately simulate DMOS switching.<>
{"title":"Demosthenes-A technology-independent power DMOS layout generator","authors":"Gilles Fourneris, N. Bekkara, J. Benkoski, L. Zullino, Dino Spatafora, G. Martino","doi":"10.1109/EURDAC.1993.410634","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410634","url":null,"abstract":"A methodology to automate DMOS layout generation starting from electrical specifications is presented. The main features of the Demosthenes technology independent layout generator that make it possible to synthesize lateral and vertical DMOS in different low and high voltage technologies are described. The built-in electrical model used by the generator to extract the device layout resistance is exposed and the accuracy of the model, ranging from 1% to 15%, is reported, according to comparisons with silicon measurements. In the future, the Demosthenes generator will be extended to support the next generation of BCD technology. In addition, electrical modeling capabilities will be improved by generating detailed electrical simulation models that make it possible to accurately simulate DMOS switching.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123210774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410661
Kai Zhu, D. F. Wong
A key step in technology mapping for non-lookup-table (such as multiplexer) based FPGAs (field programmable gate arrays) is to determine whether a given function can be implemented by the logic module. A new algorithm is presented for solving this problem. The algorithm is based on a character string representation of binary decision diagrams. Such representation leads to a matching algorithm which requires only a few string comparisons for each matching operation. When compared to the matching algorithm by searching for isomorphism on all different BDDs (binary decision diagrams), the new algorithm is much faster with a modest increase of memory requirement. For example, the experimental results showed that in matching all three-input Boolean function against Actel's ACT1 logic module, the new algorithm is 634 times faster by using 19.9% more memory.<>
{"title":"Fast Boolean matching for field-programmable gate arrays","authors":"Kai Zhu, D. F. Wong","doi":"10.1109/EURDAC.1993.410661","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410661","url":null,"abstract":"A key step in technology mapping for non-lookup-table (such as multiplexer) based FPGAs (field programmable gate arrays) is to determine whether a given function can be implemented by the logic module. A new algorithm is presented for solving this problem. The algorithm is based on a character string representation of binary decision diagrams. Such representation leads to a matching algorithm which requires only a few string comparisons for each matching operation. When compared to the matching algorithm by searching for isomorphism on all different BDDs (binary decision diagrams), the new algorithm is much faster with a modest increase of memory requirement. For example, the experimental results showed that in matching all three-input Boolean function against Actel's ACT1 logic module, the new algorithm is 634 times faster by using 19.9% more memory.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132981053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410682
Philippe Moeschler, H. Amann, F. Pellandini
The principles of high level modeling of digital hardware circuits using the extended timing diagrams (ETD) formalism, which adds conditions, events, action expressions, and particular constraints to traditional timing diagrams, are described. Hierarchy and concurrency are also integrated so that a full top-down design becomes possible, enhancing at the same time the readability. While, for simulation purposes, the implementation of the formalism generates behavioral VHDL (VHSIC Hardware Description Language) models, a dedicated high-level translator generates VHDL code for synthesis. Both the ETD formalism and its implementation are part of MODES, a more complex modeling expert system including complementary editors.<>
{"title":"High-level modeling using extended timing diagrams - A formalism for the behavioral specification of digital hardware","authors":"Philippe Moeschler, H. Amann, F. Pellandini","doi":"10.1109/EURDAC.1993.410682","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410682","url":null,"abstract":"The principles of high level modeling of digital hardware circuits using the extended timing diagrams (ETD) formalism, which adds conditions, events, action expressions, and particular constraints to traditional timing diagrams, are described. Hierarchy and concurrency are also integrated so that a full top-down design becomes possible, enhancing at the same time the readability. While, for simulation purposes, the implementation of the formalism generates behavioral VHDL (VHSIC Hardware Description Language) models, a dedicated high-level translator generates VHDL code for synthesis. Both the ETD formalism and its implementation are part of MODES, a more complex modeling expert system including complementary editors.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131262644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410666
Wen-Lin Yang, R. Owens, M. J. Irwin
Various strategies for multi-way general decomposition have been investigated in the past. These strategies differ in how they reflect the cost of a logic-level implementation. The authors are concerned with the lower bound on the number of interconnecting wires which must exist when a machine is decomposed into several submachines. From a VLSI implementation point of view having a cost function based at least in part on interconnect complexity would be advantageous. The authors present a way to establish this bound for the multi-way decomposition of an arbitrary machine and tabulate the bound for a number of benchmarks. This tabulation shows that many large benchmarks are indeed highly decomposable from an interconnect point of view.<>
{"title":"Multi-way FSM decomposition based on interconnect complexity","authors":"Wen-Lin Yang, R. Owens, M. J. Irwin","doi":"10.1109/EURDAC.1993.410666","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410666","url":null,"abstract":"Various strategies for multi-way general decomposition have been investigated in the past. These strategies differ in how they reflect the cost of a logic-level implementation. The authors are concerned with the lower bound on the number of interconnecting wires which must exist when a machine is decomposed into several submachines. From a VLSI implementation point of view having a cost function based at least in part on interconnect complexity would be advantageous. The authors present a way to establish this bound for the multi-way decomposition of an arbitrary machine and tabulate the bound for a number of benchmarks. This tabulation shows that many large benchmarks are indeed highly decomposable from an interconnect point of view.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129831058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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