Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410687
S. Olcoz, J. Colom
The need for a formal interpretation of VHDL is addressed. The formal model used for this purpose is colored Petri nets because they can cover all aspects of VHDL. The authors start from the underlying executable model of VHDL based on communicating processes. The formal model of a VHDL description results from the specification in Petri net terms of the user-defined processes, the kernel process (VHDL simulator), and the communicating links between them. This approach can also be applied to other HDLs with the same underlying paradigm.<>
{"title":"Toward a formal semantics of IEEE Std. VHDL 1076","authors":"S. Olcoz, J. Colom","doi":"10.1109/EURDAC.1993.410687","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410687","url":null,"abstract":"The need for a formal interpretation of VHDL is addressed. The formal model used for this purpose is colored Petri nets because they can cover all aspects of VHDL. The authors start from the underlying executable model of VHDL based on communicating processes. The formal model of a VHDL description results from the specification in Petri net terms of the user-defined processes, the kernel process (VHDL simulator), and the communicating links between them. This approach can also be applied to other HDLs with the same underlying paradigm.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130417436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410654
V. Kommu, I. Pomeranz
A method for solving the technology mapping problem for field-programmable gate arrays that is based on the genetic algorithm is presented. The genetic algorithm simultaneously optimizes a set of solutions, which makes it a very powerful optimization technique. However, due to the highly constrained search spaces for design automation problems, the application of the genetic algorithm is not straightforward. It is shown that this limitation can be overcome by enhancing the genetic search appropriately. The performance of the enhanced genetic search is demonstrated through experimental results for the technology mapping problem.<>
{"title":"GAFPGA: Genetic algorithm for FPGA technology mapping","authors":"V. Kommu, I. Pomeranz","doi":"10.1109/EURDAC.1993.410654","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410654","url":null,"abstract":"A method for solving the technology mapping problem for field-programmable gate arrays that is based on the genetic algorithm is presented. The genetic algorithm simultaneously optimizes a set of solutions, which makes it a very powerful optimization technique. However, due to the highly constrained search spaces for design automation problems, the application of the genetic algorithm is not straightforward. It is shown that this limitation can be overcome by enhancing the genetic search appropriately. The performance of the enhanced genetic search is demonstrated through experimental results for the technology mapping problem.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"12 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130490263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410698
K. Boese, A. Kahng, C. Tsao
The simulated annealing (SA) algorithm has been applied to every difficult optimization problem in VLSI (very large scale integration) CAD. Existing SA implementations use monotone decreasing, or cooling, temperature schedules motivated by the algorithm's proof of optimality as well as by an analogy with statistical thermodynamics. This paper gives strong evidence that challenges the correctness of using such schedules. Specifically, the theoretical framework under which monotone cooling schedules is proved optimal fails to capture the practical application of simulated annealing. In practice, the algorithm runs for a finite rather than infinite amount of time; and the algorithm returns the best solution visited during the entire run ("best-so-far") rather than the last solution visited ("where-you-are"). For small instances of classic VLSI CAD problems, the authors determine annealing schedules that are optimal in terms of the expected quality of the best-so-far solution. These optimal schedules do not decrease monotonically, but are in fact either periodic or warming. (When the goal is to optimize the cost of the where-you-are solution, they confirm the traditional wisdom of cooling.) The results open up many new research directions, particularly how to choose annealing temperatures dynamically to optimize the quality of the finite time, best-so-far solution.<>
{"title":"Best-so-far vs. where-you-are: New perspectives on simulated annealing for CAD","authors":"K. Boese, A. Kahng, C. Tsao","doi":"10.1109/EURDAC.1993.410698","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410698","url":null,"abstract":"The simulated annealing (SA) algorithm has been applied to every difficult optimization problem in VLSI (very large scale integration) CAD. Existing SA implementations use monotone decreasing, or cooling, temperature schedules motivated by the algorithm's proof of optimality as well as by an analogy with statistical thermodynamics. This paper gives strong evidence that challenges the correctness of using such schedules. Specifically, the theoretical framework under which monotone cooling schedules is proved optimal fails to capture the practical application of simulated annealing. In practice, the algorithm runs for a finite rather than infinite amount of time; and the algorithm returns the best solution visited during the entire run (\"best-so-far\") rather than the last solution visited (\"where-you-are\"). For small instances of classic VLSI CAD problems, the authors determine annealing schedules that are optimal in terms of the expected quality of the best-so-far solution. These optimal schedules do not decrease monotonically, but are in fact either periodic or warming. (When the goal is to optimize the cost of the where-you-are solution, they confirm the traditional wisdom of cooling.) The results open up many new research directions, particularly how to choose annealing temperatures dynamically to optimize the quality of the finite time, best-so-far solution.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115650419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410615
A. A. Duncan, D. C. Hendry
CASS (column architecture synthesis system) is a behavioral high level synthesis system for DSP applications. It uses a column based target architecture and in-the-cell routing to produce compact layout which eliminates the need for global wiring. This is achieved using bit-sliced cells which butt together to produce the data path. A description of the architecture and algorithms which produce the datapath is given. It is also shown that this approach gives large area savings when compared to a conventional system.<>
{"title":"DSP datapath synthesis eliminating global interconnect","authors":"A. A. Duncan, D. C. Hendry","doi":"10.1109/EURDAC.1993.410615","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410615","url":null,"abstract":"CASS (column architecture synthesis system) is a behavioral high level synthesis system for DSP applications. It uses a column based target architecture and in-the-cell routing to produce compact layout which eliminates the need for global wiring. This is achieved using bit-sliced cells which butt together to produce the data path. A description of the architecture and algorithms which produce the datapath is given. It is also shown that this approach gives large area savings when compared to a conventional system.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122914600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410627
E. Felt, G. York, R. Brayton, A. Sangiovanni-Vincentelli
Binary Decision Diagrams (BDDs) are a data structure frequently used to represent complex Boolean functions in formal verification algorithms. An efficient heuristic algorithm for dynamically reducing the size of large reduced ordered BDDs by optimally reordering small windows of consecutive variables is presented. The algorithms have been fully integrated into the Berkeley and Carnegie Mellon BDD packages in such a way that the current variable order dynamically changes and is completely transparent to the user. Dynamic reordering significantly reduces the memory required for BDD-based verification algorithms, thus permitting the verification of significantly more complex systems than was previously possible. The algorithms exhibit a smooth tradeoff between CPU time and reduction in BDD size for almost all BDDs tested.<>
{"title":"Dynamic variable reordering for BDD minimization","authors":"E. Felt, G. York, R. Brayton, A. Sangiovanni-Vincentelli","doi":"10.1109/EURDAC.1993.410627","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410627","url":null,"abstract":"Binary Decision Diagrams (BDDs) are a data structure frequently used to represent complex Boolean functions in formal verification algorithms. An efficient heuristic algorithm for dynamically reducing the size of large reduced ordered BDDs by optimally reordering small windows of consecutive variables is presented. The algorithms have been fully integrated into the Berkeley and Carnegie Mellon BDD packages in such a way that the current variable order dynamically changes and is completely transparent to the user. Dynamic reordering significantly reduces the memory required for BDD-based verification algorithms, thus permitting the verification of significantly more complex systems than was previously possible. The algorithms exhibit a smooth tradeoff between CPU time and reduction in BDD size for almost all BDDs tested.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124630039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410679
J. Muller, H. Kramer
A method for analyzing behavioral multiprocess VHDL specifications used for optimizing system-level synthesis is presented. To determine the access conflicts to the global data signals, the system behavior must be analyzed. Therefore the synchronization scheme is modeled as a Petri net, which can be minimized by transformation. A reduced case graph is regarded as a state transition graph of the system states. To calculate the probabilities of the access conflicts, the probability of observing the system in a certain state must be determined. This is done by calculation of the stationary distribution of a Markov chain.<>
{"title":"Analysis of multi-process VHDL specifications with a Petri net model","authors":"J. Muller, H. Kramer","doi":"10.1109/EURDAC.1993.410679","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410679","url":null,"abstract":"A method for analyzing behavioral multiprocess VHDL specifications used for optimizing system-level synthesis is presented. To determine the access conflicts to the global data signals, the system behavior must be analyzed. Therefore the synchronization scheme is modeled as a Petri net, which can be minimized by transformation. A reduced case graph is regarded as a state transition graph of the system states. To calculate the probabilities of the access conflicts, the probability of observing the system in a certain state must be determined. This is done by calculation of the stationary distribution of a Markov chain.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114855452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410650
P. Windirsch, P. Duzy
The authors demonstrate the use of high-level synthesis for ASIC designs in the mechatronic application domain. The first chip synthesized and fabricated is part of a distance measurement system. Only six weeks were needed for the design of the 2700 equivalent gates ASIC. The hand-crafted standard cell design had taken four times as long for a result of comparable size and performance. Similar results have been obtained in a second ASIC project, which is part of a friction clutch controller.<>
{"title":"The CALLAS synthesis system and its application to mechatronic ASIC design problems","authors":"P. Windirsch, P. Duzy","doi":"10.1109/EURDAC.1993.410650","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410650","url":null,"abstract":"The authors demonstrate the use of high-level synthesis for ASIC designs in the mechatronic application domain. The first chip synthesized and fabricated is part of a distance measurement system. Only six weeks were needed for the design of the 2700 equivalent gates ASIC. The hand-crafted standard cell design had taken four times as long for a result of comparable size and performance. Similar results have been obtained in a second ASIC project, which is part of a friction clutch controller.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114580781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410613
T. Gao, C. Liu, Kuang-Chien Chen
A new hierarchical partitioning placement algorithm is presented. The objective function is formulated as a weighted sum of the total wire length and the maximum circuit delay. Special balancing rules are used to assure a good balance between the numbers of components in the regions. Total wire length and maximum circuit delay are estimated and updated efficiently at each step of the partitioning process. Experimental results are very encouraging.<>
{"title":"A performance driven hierarchical partitioning placement algorithm","authors":"T. Gao, C. Liu, Kuang-Chien Chen","doi":"10.1109/EURDAC.1993.410613","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410613","url":null,"abstract":"A new hierarchical partitioning placement algorithm is presented. The objective function is formulated as a weighted sum of the total wire length and the maximum circuit delay. Special balancing rules are used to assure a good balance between the numbers of components in the regions. Total wire length and maximum circuit delay are estimated and updated efficiently at each step of the partitioning process. Experimental results are very encouraging.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129209508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410658
M. Oussalah, Guilaine Talens, M. Colinas
Object versions are one of the most important data-modeling requirements for design environments. The authors describe the mechanisms for the creation of versioned objects (simple objects or composite objects) and the conversion of non-versioned objects into versioned form. They then explain the relationships between versions.<>
{"title":"Concepts and methods for version modeling","authors":"M. Oussalah, Guilaine Talens, M. Colinas","doi":"10.1109/EURDAC.1993.410658","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410658","url":null,"abstract":"Object versions are one of the most important data-modeling requirements for design environments. The authors describe the mechanisms for the creation of versioned objects (simple objects or composite objects) and the conversion of non-versioned objects into versioned form. They then explain the relationships between versions.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"56 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132678858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410677
A. Acosta, A. Barriga, M. Valencia-Barrero, M. J. Díaz, J. Huertas
A complete VHDL model of bistables including their metastable operation is presented. An RS-NAND latch has been modeled as a basic structure, orienting its implementation towards its inclusion in a cell library. Two applications are included: a description of a more complex latch (D-type) and a description of a circuit containing three latches where metastable signals are propagated. Simulation results show that the presented model provides very realistic information about the device behavior, which until now had to be obtained through electric simulation.<>
{"title":"Modeling of real bistables in VHDL","authors":"A. Acosta, A. Barriga, M. Valencia-Barrero, M. J. Díaz, J. Huertas","doi":"10.1109/EURDAC.1993.410677","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410677","url":null,"abstract":"A complete VHDL model of bistables including their metastable operation is presented. An RS-NAND latch has been modeled as a basic structure, orienting its implementation towards its inclusion in a cell library. Two applications are included: a description of a more complex latch (D-type) and a description of a circuit containing three latches where metastable signals are propagated. Simulation results show that the presented model provides very realistic information about the device behavior, which until now had to be obtained through electric simulation.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131701913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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