Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410662
M. Thornton, S. Nair
The spectral information of a Boolean function provides data regarding the correlation between the input variables and the output of the function. A spectral based methodology for combinational logic synthesis using linear transforms is introduced. An analysis of the properties of the spectra obtained from these transforms is provided and a synthesis algorithm using spectral techniques is presented. This result is significant since it provides an algebraic method for including XOR gates in the synthesis process without resorting to manipulation of symbolic Boolean equations.<>
{"title":"An iterative combinational logic synthesis technique using spectral information","authors":"M. Thornton, S. Nair","doi":"10.1109/EURDAC.1993.410662","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410662","url":null,"abstract":"The spectral information of a Boolean function provides data regarding the correlation between the input variables and the output of the function. A spectral based methodology for combinational logic synthesis using linear transforms is introduced. An analysis of the properties of the spectra obtained from these transforms is provided and a synthesis algorithm using spectral techniques is presented. This result is significant since it provides an algebraic method for including XOR gates in the synthesis process without resorting to manipulation of symbolic Boolean equations.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125652970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410655
I. Levin, R. Pinter
The authors consider the problem of mapping an expression graph (which represents a combinational network) to a minimal number of programmable functional elements connected by a configurable network (e.g., Xilinx elements). Since each element can realize any function of a fixed arity, they look only at the topological aspect of the mapping, i.e., no algebraic (or other) simplifications are considered (this could have been done at the earlier stage which produced the expression itself). Two analytic results are presented: (1) trees (of arbitrary degree) can be mapped optimally in linear time to elements of four inputs and one output each; and (2) the problem becomes NP-complete for DAGs even if they have only one root and the maximal in-degree of nodes is three. The first result can be easily generalized to elements with any other fixed number of inputs (that is known a priori) and which are used uniformly in the circuit. In light of the second result, the authors present three heuristics for mapping DAGs to networks and discuss their performance both on the ISCAS benchmark and on randomly generated graphs.<>
{"title":"Realizing expression graphs using table-lookup FPGAs","authors":"I. Levin, R. Pinter","doi":"10.1109/EURDAC.1993.410655","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410655","url":null,"abstract":"The authors consider the problem of mapping an expression graph (which represents a combinational network) to a minimal number of programmable functional elements connected by a configurable network (e.g., Xilinx elements). Since each element can realize any function of a fixed arity, they look only at the topological aspect of the mapping, i.e., no algebraic (or other) simplifications are considered (this could have been done at the earlier stage which produced the expression itself). Two analytic results are presented: (1) trees (of arbitrary degree) can be mapped optimally in linear time to elements of four inputs and one output each; and (2) the problem becomes NP-complete for DAGs even if they have only one root and the maximal in-degree of nodes is three. The first result can be easily generalized to elements with any other fixed number of inputs (that is known a priori) and which are used uniformly in the circuit. In light of the second result, the authors present three heuristics for mapping DAGs to networks and discuss their performance both on the ISCAS benchmark and on randomly generated graphs.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114757130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410633
T. W. Her, D. F. Wong
Tall transistors can be folded into shorter ones to reduce the layout area. The authors take two rows of transistors, one for P-type transistors and the other for N-type transistors, and attempt to determine an optimal folding for each transistor to minimize the layout area. They present an O(K/sup 3/L/sup 3/) time transistor folding algorithm to minimize the layout area, where K is the number of implementations of each transistor due to folding, and L is the channel length.<>
{"title":"Cell area minimization by transistor folding","authors":"T. W. Her, D. F. Wong","doi":"10.1109/EURDAC.1993.410633","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410633","url":null,"abstract":"Tall transistors can be folded into shorter ones to reduce the layout area. The authors take two rows of transistors, one for P-type transistors and the other for N-type transistors, and attempt to determine an optimal folding for each transistor to minimize the layout area. They present an O(K/sup 3/L/sup 3/) time transistor folding algorithm to minimize the layout area, where K is the number of implementations of each transistor due to folding, and L is the channel length.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123694593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410656
R. Jacobi, Anne-Marie Trullemans-Anckaert
A new method was presented for the minimization of incompletely specified functions using MBDs (modified binary decision diagrams: ROBDDs with a don't care terminal). The cost function to be minimized is the MBD size, which is an important factor in the case of FPGA synthesis. The method developed is based on a subgraph matching target to reduce the number of nodes of a MBD. The matching relies on the presence of a third terminal value X (don't care) in the MBD in order to represent an incompletely specified function in a single graph. The authors have compared the new method with ESPRESSO with respect to MBD size reduction and multiplexor based synthesis. The results obtained empirically confirm the initial hypothesis that two-level minimization techniques are inadequate for this purpose, and also show the efficiency of the proposed algorithm.<>
{"title":"A new logic minimization method for multiplexor-based FPGA synthesis","authors":"R. Jacobi, Anne-Marie Trullemans-Anckaert","doi":"10.1109/EURDAC.1993.410656","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410656","url":null,"abstract":"A new method was presented for the minimization of incompletely specified functions using MBDs (modified binary decision diagrams: ROBDDs with a don't care terminal). The cost function to be minimized is the MBD size, which is an important factor in the case of FPGA synthesis. The method developed is based on a subgraph matching target to reduce the number of nodes of a MBD. The matching relies on the presence of a third terminal value X (don't care) in the MBD in order to represent an incompletely specified function in a single graph. The authors have compared the new method with ESPRESSO with respect to MBD size reduction and multiplexor based synthesis. The results obtained empirically confirm the initial hypothesis that two-level minimization techniques are inadequate for this purpose, and also show the efficiency of the proposed algorithm.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130021571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410626
P. Camurati, Fulvio Corno, P. Prinetto
The use of process algebras is advocated as a solution for system-level description of structure, communication, and behavior, while an action-based temporal logic is used to specify and check system-level properties. It is shown how SEVERO, a tool for describing and verifying finite state systems, can be used to integrate in the unified framework of symbolic manipulations both descriptive and prescriptive aspects. Experimental results show the efficiency of the BDD (binary decision diagram)-based implementation of the proof procedures.<>
{"title":"An efficient tool for system-level verification of behaviors and temporal properties","authors":"P. Camurati, Fulvio Corno, P. Prinetto","doi":"10.1109/EURDAC.1993.410626","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410626","url":null,"abstract":"The use of process algebras is advocated as a solution for system-level description of structure, communication, and behavior, while an action-based temporal logic is used to specify and check system-level properties. It is shown how SEVERO, a tool for describing and verifying finite state systems, can be used to integrate in the unified framework of symbolic manipulations both descriptive and prescriptive aspects. Experimental results show the efficiency of the BDD (binary decision diagram)-based implementation of the proof procedures.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124447598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410648
Xiao Sun, F. Lombardi, D. Sciuto
A new heuristic algorithm (based on the fault dictionary approach) that finds the minimal test set for locating single faults (of the stuck-at type) in a digital circuit, thus reducing the size of the fault dictionary, is presented. The proposed algorithm is based on finding the transitive closure of the vectors in the test set with respect to the functional dominancies using Warshall's algorithm for binary matrices. The space complexity of the proposed algorithm is O(ma.<>
{"title":"On the minimal test set for single fault location","authors":"Xiao Sun, F. Lombardi, D. Sciuto","doi":"10.1109/EURDAC.1993.410648","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410648","url":null,"abstract":"A new heuristic algorithm (based on the fault dictionary approach) that finds the minimal test set for locating single faults (of the stuck-at type) in a digital circuit, thus reducing the size of the fault dictionary, is presented. The proposed algorithm is based on finding the transitive closure of the vectors in the test set with respect to the functional dominancies using Warshall's algorithm for binary matrices. The space complexity of the proposed algorithm is O(ma.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121313224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410629
I. Pyo, A. Despain
The PDAS (Processor Design Automation System) is a new approach to design automation that uses formal methods to achieve a new level of design power and the ability to formally validate designs. The idea is to develop a design automation system which considers both microprocessor hardware design and design of the corresponding language compiler concurrently. Benchmark programs are used to motivate design decisions and optimize performance. Compiler optimizations are considered during the design of hardware. The system spans language design, compiler design, instruction set design, microarchitecture, and VLSI implementation.<>
{"title":"PDAS: Processor design automation system","authors":"I. Pyo, A. Despain","doi":"10.1109/EURDAC.1993.410629","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410629","url":null,"abstract":"The PDAS (Processor Design Automation System) is a new approach to design automation that uses formal methods to achieve a new level of design power and the ability to formally validate designs. The idea is to develop a design automation system which considers both microprocessor hardware design and design of the corresponding language compiler concurrently. Benchmark programs are used to motivate design decisions and optimize performance. Compiler optimizations are considered during the design of hardware. The system spans language design, compiler design, instruction set design, microarchitecture, and VLSI implementation.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121414085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410610
E. Martin, O. Sentieys, H. Dubois, J. Philippe
This paper describes a pipeline architecture synthesis tool dedicated to signal processing applications. This approach relies on the use of a design strategy and of a generic architectural model, using optimized control of resources. GAUT takes a VHDL description of an application as input, and generates the optimal structural and functional VHDL description of a dedicated architecture. The results obtained by GAUT are intended for an application in acoustic echo cancellation.<>
{"title":"GAUT: An architectural synthesis tool for dedicated signal processors","authors":"E. Martin, O. Sentieys, H. Dubois, J. Philippe","doi":"10.1109/EURDAC.1993.410610","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410610","url":null,"abstract":"This paper describes a pipeline architecture synthesis tool dedicated to signal processing applications. This approach relies on the use of a design strategy and of a generic architectural model, using optimized control of resources. GAUT takes a VHDL description of an application as input, and generates the optimal structural and functional VHDL description of a dedicated architecture. The results obtained by GAUT are intended for an application in acoustic echo cancellation.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131258934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410632
U. Bruning, G. Radke, J. Sladky
The design of complex hardware systems demands high level design tools in order to shorten the design time and ensure the correctness. The analysis of a typical computer design example shows that the sequential control logic of hardware systems, realized as finite state machines, is one of the major design efforts. The tools presented support the main phases of the design process for FSMs and provide a significant reduction in design time. The efficient connection to a system level simulation and the display of animated graphical FSMs by these tools are described.<>
{"title":"State-machine-development-tool for high-level-design entry and simulation","authors":"U. Bruning, G. Radke, J. Sladky","doi":"10.1109/EURDAC.1993.410632","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410632","url":null,"abstract":"The design of complex hardware systems demands high level design tools in order to shorten the design time and ensure the correctness. The analysis of a typical computer design example shows that the sequential control logic of hardware systems, realized as finite state machines, is one of the major design efforts. The tools presented support the main phases of the design process for FSMs and provide a significant reduction in design time. The efficient connection to a system level simulation and the display of animated graphical FSMs by these tools are described.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131387044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410667
G. Rietsche
Considerable progress in the area of state assignment for PLA and multi-level finite state machine realizations was made in the last ten years. Although many finite state machines can be more efficiently implemented if T flip-flops are used as memory elements, research has concentrated on finite state machines using D flip-flop memory. A state assignment algorithm for finite state machines using T flip-flops is presented. For realistic benchmarks, the area requirements of the finite state machine realization are up to 50% smaller if T flip-flops are used as memory elements.<>
{"title":"State assignment for finite state machines using T flip-flops","authors":"G. Rietsche","doi":"10.1109/EURDAC.1993.410667","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410667","url":null,"abstract":"Considerable progress in the area of state assignment for PLA and multi-level finite state machine realizations was made in the last ten years. Although many finite state machines can be more efficiently implemented if T flip-flops are used as memory elements, research has concentrated on finite state machines using D flip-flop memory. A state assignment algorithm for finite state machines using T flip-flops is presented. For realistic benchmarks, the area requirements of the finite state machine realization are up to 50% smaller if T flip-flops are used as memory elements.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131598744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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