Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410635
Ronald D. Hindmarsh
A new width minimizing layout style called jogged gate matrix (JOGM) for CMOS cells is described. The traditional gate matrix layout style is modified by inserting 45/spl deg/ jogs into transistor gates. Thus, JOGM improves CMOS cell width by 23% to 31% in comparison to traditional gate matrix layout. An approach for automatic layout generation is suggested.<>
{"title":"JOGM: A CMOS cell layout style using jogged transistor gates","authors":"Ronald D. Hindmarsh","doi":"10.1109/EURDAC.1993.410635","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410635","url":null,"abstract":"A new width minimizing layout style called jogged gate matrix (JOGM) for CMOS cells is described. The traditional gate matrix layout style is modified by inserting 45/spl deg/ jogs into transistor gates. Thus, JOGM improves CMOS cell width by 23% to 31% in comparison to traditional gate matrix layout. An approach for automatic layout generation is suggested.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133437879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410660
Kuang-Chien Chen
The authors consider the problem of detecting the equivalence of two single-output Boolean functions, considering the permutation and complementation of their inputs, complementation of outputs, and their associated don't-care sets. This is often referred to as the Boolean matching problem. Boolean matching is a verification problem, and it has important applications in logic synthesis problems such as technology-mapping. An algorithm for solving the Boolean matching problem which is based on Boolean unification and branch-and-bound techniques is presented. This algorithm has been applied to the task of technology-mapping for cell-based designs, and experimental results show that it is an efficient and effective algorithm. Comparisons with existing Boolean matching algorithms are presented.<>
{"title":"Boolean matching based on Boolean unification","authors":"Kuang-Chien Chen","doi":"10.1109/EURDAC.1993.410660","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410660","url":null,"abstract":"The authors consider the problem of detecting the equivalence of two single-output Boolean functions, considering the permutation and complementation of their inputs, complementation of outputs, and their associated don't-care sets. This is often referred to as the Boolean matching problem. Boolean matching is a verification problem, and it has important applications in logic synthesis problems such as technology-mapping. An algorithm for solving the Boolean matching problem which is based on Boolean unification and branch-and-bound techniques is presented. This algorithm has been applied to the task of technology-mapping for cell-based designs, and experimental results show that it is an efficient and effective algorithm. Comparisons with existing Boolean matching algorithms are presented.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"354 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132553883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410699
Bertram Després, R. Piloty, Ulf Schellin
CAD database services which support CAD tools in preserving design consistency are presented. Design consistency is briefly defined. Interactive design tools require support with respect to the specification of consistency rules, check points, and reactions to checks. Services of the object oriented IREEN database system designed to meet these requirements are presented. The authors introduce tasks (event driven processes) which provide a means to create supervisors for consistency rules as well as to model higher order actions to which consistency rules are related.<>
{"title":"An approach to CAD database support of design consistency control","authors":"Bertram Després, R. Piloty, Ulf Schellin","doi":"10.1109/EURDAC.1993.410699","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410699","url":null,"abstract":"CAD database services which support CAD tools in preserving design consistency are presented. Design consistency is briefly defined. Interactive design tools require support with respect to the specification of consistency rules, check points, and reactions to checks. Services of the object oriented IREEN database system designed to meet these requirements are presented. The authors introduce tasks (event driven processes) which provide a means to create supervisors for consistency rules as well as to model higher order actions to which consistency rules are related.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130236518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410643
Chaeryung Park, Taewhan Kim, C. Liu
A new approach to the problem of register allocation in the presence of both conditional branches and loops in a data flow graph is presented. The authors algorithm exploits the possibility of register sharing among mutually exclusive variables using a transformational approach - sets of mutually exclusive variables are transformed into an equivalent set of non-mutually exclusive variables. The transformational approach is extended to the case of data flow graphs with loops. A new register allocation algorithm is then used to produce an allocation for the non-mutually exclusive variables. From such an allocation, a corresponding allocation for the original sets of mutually exclusive variables is derived. Experimental results show that the approach is quite effective.<>
{"title":"Register allocation for data flow graphs with conditional branches and loops","authors":"Chaeryung Park, Taewhan Kim, C. Liu","doi":"10.1109/EURDAC.1993.410643","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410643","url":null,"abstract":"A new approach to the problem of register allocation in the presence of both conditional branches and loops in a data flow graph is presented. The authors algorithm exploits the possibility of register sharing among mutually exclusive variables using a transformational approach - sets of mutually exclusive variables are transformed into an equivalent set of non-mutually exclusive variables. The transformational approach is extended to the case of data flow graphs with loops. A new register allocation algorithm is then used to produce an allocation for the non-mutually exclusive variables. From such an allocation, a corresponding allocation for the original sets of mutually exclusive variables is derived. Experimental results show that the approach is quite effective.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132749222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410690
Hazem ElTahawy, Dominique Rodriguez, S. G. Sabiro, J.-J. Mayol
Mixed-mode simulation has recently received increased interest not only in cases where analog and digital circuitries coexist in one integrated circuit, but also for a faster digital and complex circuitry which needs high precision in simulation. The importance of mixed mode simulation is highlighted, and its basic principles are described. VHD/sub e/LDO, a new mixed mode simulation, is presented showing a new feature for the mixed interface and synchronization mechanism. Finally, a practical example showing all these characteristics is presented.<>
{"title":"VHD/sub e/LDO: A new mixed mode simulation","authors":"Hazem ElTahawy, Dominique Rodriguez, S. G. Sabiro, J.-J. Mayol","doi":"10.1109/EURDAC.1993.410690","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410690","url":null,"abstract":"Mixed-mode simulation has recently received increased interest not only in cases where analog and digital circuitries coexist in one integrated circuit, but also for a faster digital and complex circuitry which needs high precision in simulation. The importance of mixed mode simulation is highlighted, and its basic principles are described. VHD/sub e/LDO, a new mixed mode simulation, is presented showing a new feature for the mixed interface and synchronization mechanism. Finally, a practical example showing all these characteristics is presented.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"513 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123566732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410624
Ting-Chi Wang, D. F. Wong, Yachyang Sun, Chak-Kuen Wong
The authors consider two over-the-cell channel routing problems: the over-the-cell planar routing problem and the over-the-cell net assignment problem. They present optimal algorithms for solving the two problems. Experimental results are also provided to demonstrate the efficiency and effectiveness of the algorithms.<>
{"title":"On over-the-cell channel routing","authors":"Ting-Chi Wang, D. F. Wong, Yachyang Sun, Chak-Kuen Wong","doi":"10.1109/EURDAC.1993.410624","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410624","url":null,"abstract":"The authors consider two over-the-cell channel routing problems: the over-the-cell planar routing problem and the over-the-cell net assignment problem. They present optimal algorithms for solving the two problems. Experimental results are also provided to demonstrate the efficiency and effectiveness of the algorithms.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125542686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410691
J. P. Calvez, Dominique Heller, P. Bakowski
The authors describe a procedure and a tool for ASIC synthesis with VHDL. They show that the functional level which they define and use as the design input provides a synthesis level located between the system-level synthesis and the RT-level synthesis. The described design and synthesis process is based on a complete methodology and the use of its functional model allows designers to describe their solutions according to two views: an organizational view which defines the internal structure, and a behavioral view which describes the activity of each function. Tools, mainly graphical, have been developed as an aid to capture the design description. After that, a generator is used to obtain the complete VHDL model at a RT-level model which is simulatable and synthesizable. Such a tool leads to obtaining of ASIC prototypes efficiently and in an incremental manner. Results for some ASICs designed by the authors are given to illustrate the benefit of the proposed method and the significance of the functional level.<>
{"title":"Functional-level synthesis with VHDL","authors":"J. P. Calvez, Dominique Heller, P. Bakowski","doi":"10.1109/EURDAC.1993.410691","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410691","url":null,"abstract":"The authors describe a procedure and a tool for ASIC synthesis with VHDL. They show that the functional level which they define and use as the design input provides a synthesis level located between the system-level synthesis and the RT-level synthesis. The described design and synthesis process is based on a complete methodology and the use of its functional model allows designers to describe their solutions according to two views: an organizational view which defines the internal structure, and a behavioral view which describes the activity of each function. Tools, mainly graphical, have been developed as an aid to capture the design description. After that, a generator is used to obtain the complete VHDL model at a RT-level model which is simulatable and synthesizable. Such a tool leads to obtaining of ASIC prototypes efficiently and in an incremental manner. Results for some ASICs designed by the authors are given to illustrate the benefit of the proposed method and the significance of the functional level.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"04 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128990471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410683
W. Ecker
HW/SW (hardware/software) co-specification and co-design require a medium for HW/SW implementation independent description as well as for integration of hardware and software. Since not all design steps can be performed automatically, this medium must be capable of representing results of intermediate design steps from both CAD tools and human interaction. VHDL is widely accepted in HW design where it is mostly used at the RT level. VHDL implementations of abstract data and control structures which support clock independent communication and synchronization allow one to extend VHDL toward system level and HW/SW co-design.<>
{"title":"Using VHDL for HW/SW co-specification","authors":"W. Ecker","doi":"10.1109/EURDAC.1993.410683","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410683","url":null,"abstract":"HW/SW (hardware/software) co-specification and co-design require a medium for HW/SW implementation independent description as well as for integration of hardware and software. Since not all design steps can be performed automatically, this medium must be capable of representing results of intermediate design steps from both CAD tools and human interaction. VHDL is widely accepted in HW design where it is mostly used at the RT level. VHDL implementations of abstract data and control structures which support clock independent communication and synchronization allow one to extend VHDL toward system level and HW/SW co-design.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115686423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410645
L. Ramachandran, D. Gajski
Current synthesis approaches do not take into account the impact of the underlying architecture during operations like scheduling and binding. This results in synthesis algorithms that can produce designs only for a single architecture. The design space that can be explored by such a synthesis tool is limited. The authors examine three architectures that have different control pipelining strategies. They derive the important constraints that these architectures impose on the scheduling algorithm and propose an algorithm that incorporates these constraints when producing a schedule. They also demonstrate through several experiments that by being able to synthesize for a given control pipeline architecture, they can provide designers with a wide range of area-delay tradeoffs.<>
{"title":"Architectural tradeoffs in synthesis of pipelined controls","authors":"L. Ramachandran, D. Gajski","doi":"10.1109/EURDAC.1993.410645","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410645","url":null,"abstract":"Current synthesis approaches do not take into account the impact of the underlying architecture during operations like scheduling and binding. This results in synthesis algorithms that can produce designs only for a single architecture. The design space that can be explored by such a synthesis tool is limited. The authors examine three architectures that have different control pipelining strategies. They derive the important constraints that these architectures impose on the scheduling algorithm and propose an algorithm that incorporates these constraints when producing a schedule. They also demonstrate through several experiments that by being able to synthesize for a given control pipeline architecture, they can provide designers with a wide range of area-delay tradeoffs.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131403643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410673
J. Armstrong
Complex VLSI (very large scale integration) system design with VHDL requires test generation techniques that work at different levels in the abstraction hierarchy. The author discusses approaches to test generation which attempt to address this issue. Areas of test generation considered are behavior-assisted gate-level and switch-level test generation, test construction from sub-component tests, and test generation from behavioral models. The status of these methods and recommendations for future research and development are given, so that effective hierarchical test generation can become a reality.<>
{"title":"Hierarchical test generation: Where we are, and where we should be going","authors":"J. Armstrong","doi":"10.1109/EURDAC.1993.410673","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410673","url":null,"abstract":"Complex VLSI (very large scale integration) system design with VHDL requires test generation techniques that work at different levels in the abstraction hierarchy. The author discusses approaches to test generation which attempt to address this issue. Areas of test generation considered are behavior-assisted gate-level and switch-level test generation, test construction from sub-component tests, and test generation from behavioral models. The status of these methods and recommendations for future research and development are given, so that effective hierarchical test generation can become a reality.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127501994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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