Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410619
H. Vaishnav, Massoud Pedram
PCUBE, a performance driven placement algorithm for minimizing power consumption, is described. The problem is formulated as a constrained programming problem and is solved in two phases: global optimization and slot assignment. The objective function used during either phase is the total weighted net length, where net weights are calculated as the expected switching activities of gates driving the nets. Constraints on total path delays are also accounted for. On average, PCUBE reduces power consumption due to interconnect by 7% at the expense of 8% increase in the total wire length and 2% increase in circuit delay.<>
{"title":"PCUBE: A performance driven placement algorithm for low power designs","authors":"H. Vaishnav, Massoud Pedram","doi":"10.1109/EURDAC.1993.410619","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410619","url":null,"abstract":"PCUBE, a performance driven placement algorithm for minimizing power consumption, is described. The problem is formulated as a constrained programming problem and is solved in two phases: global optimization and slot assignment. The objective function used during either phase is the total weighted net length, where net weights are calculated as the expected switching activities of gates driving the nets. Constraints on total path delays are also accounted for. On average, PCUBE reduces power consumption due to interconnect by 7% at the expense of 8% increase in the total wire length and 2% increase in circuit delay.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123461651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410621
Jack T. Yao, A. Yang
Nonlinear simulations of semiconductor networks, in both the time and the frequency domains, determine the accuracy of analog CAD tools. Conventional circuit simulators such as SPICE provide nonlinear simulation only in the time domain. Analysis outputs are often verified by the frequency-domain nonlinear harmonic balance (HB) techniques. However, inconsistency between the individually developed tools would easily invalidate this simulation/verification process. In addition, the HB algorithms also suffer from many convergence problems which exclude HB from general applications. The authors present a compiler-based design framework in association with the improved HB algorithms to provide consistent nonlinear simulations. Simulation algorithms are formulated directly on unified modeling primitives which are then used to construct device models. Application examples and simulation results are presented to demonstrate the effectiveness of the proposed methodology.<>
{"title":"A consistent nonlinear simulation environment based on improved harmonic balance techniques","authors":"Jack T. Yao, A. Yang","doi":"10.1109/EURDAC.1993.410621","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410621","url":null,"abstract":"Nonlinear simulations of semiconductor networks, in both the time and the frequency domains, determine the accuracy of analog CAD tools. Conventional circuit simulators such as SPICE provide nonlinear simulation only in the time domain. Analysis outputs are often verified by the frequency-domain nonlinear harmonic balance (HB) techniques. However, inconsistency between the individually developed tools would easily invalidate this simulation/verification process. In addition, the HB algorithms also suffer from many convergence problems which exclude HB from general applications. The authors present a compiler-based design framework in association with the improved HB algorithms to provide consistent nonlinear simulations. Simulation algorithms are formulated directly on unified modeling primitives which are then used to construct device models. Application examples and simulation results are presented to demonstrate the effectiveness of the proposed methodology.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125113177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410678
M. Bluml, Michael Lenzen, A. Pawlak
The authors present a generator of behavioral components models which is highly flexible as it depends neither on a particular modeling technique, nor on a specific input format of a component specification. It is currently tuned for VHDL, but in fact is not HDL specific. To obtain a maximum degree of flexibility, the generator was designed as a model development environment basically composed of four module types: preprocessor modules parsing and processing component specifications of a specific definition format, method modules representating the component modeling technique to be used, a server module that controls and invokes various generation activities, and a client module constituting the user interface. To provide a workbench that can be tailored to the model developer's individual needs and can grow with the model developer's experience is the major concern of this work.<>
{"title":"A workbench for generation of component models","authors":"M. Bluml, Michael Lenzen, A. Pawlak","doi":"10.1109/EURDAC.1993.410678","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410678","url":null,"abstract":"The authors present a generator of behavioral components models which is highly flexible as it depends neither on a particular modeling technique, nor on a specific input format of a component specification. It is currently tuned for VHDL, but in fact is not HDL specific. To obtain a maximum degree of flexibility, the generator was designed as a model development environment basically composed of four module types: preprocessor modules parsing and processing component specifications of a specific definition format, method modules representating the component modeling technique to be used, a server module that controls and invokes various generation activities, and a client module constituting the user interface. To provide a workbench that can be tailored to the model developer's individual needs and can grow with the model developer's experience is the major concern of this work.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122256305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410653
B. Klaassen, K. Paap
A method is presented to combine solvers for ordinary and partial differential equations, like SPICE and ANSYS, for thermal-electrical analysis of integrated circuits or systems. A sketch of a first prototype program (SPAN) is given together with the theoretical background, which makes use of convergence principles from waveform relaxation. The approach can also be extended to more general problems within mechatronics simulation.<>
{"title":"SPAN: Tightly coupled thermal and electrical simulation","authors":"B. Klaassen, K. Paap","doi":"10.1109/EURDAC.1993.410653","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410653","url":null,"abstract":"A method is presented to combine solvers for ordinary and partial differential equations, like SPICE and ANSYS, for thermal-electrical analysis of integrated circuits or systems. A sketch of a first prototype program (SPAN) is given together with the theoretical background, which makes use of convergence principles from waveform relaxation. The approach can also be extended to more general problems within mechatronics simulation.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126033616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410620
M. Sabry, M. Tawfik, Hazem ElTahawy, S. G. Sabiro, J. Besnard
A new method capable of simulating transient behavior of tightly coupled circuits with high precision and speed is proposed. It is based on the transformation of the differential equations into integral equations. The method is semi-analytic and is of the third order. It gives a net speed advantage (about one order of magnitude) over classical methods, especially for high precision (typically analog) circuits. It also gives an a priori error estimate which will reduce rejected steps.<>
{"title":"A novel and efficient technique for transient analysis of tightly coupled circuits: The integral equation method (IEM)","authors":"M. Sabry, M. Tawfik, Hazem ElTahawy, S. G. Sabiro, J. Besnard","doi":"10.1109/EURDAC.1993.410620","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410620","url":null,"abstract":"A new method capable of simulating transient behavior of tightly coupled circuits with high precision and speed is proposed. It is based on the transformation of the differential equations into integral equations. The method is semi-analytic and is of the third order. It gives a net speed advantage (about one order of magnitude) over classical methods, especially for high precision (typically analog) circuits. It also gives an a priori error estimate which will reduce rejected steps.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128920078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410636
A. Hernández, Luis Gómez, A. Núñez
A methodology is presented to calculate delays in DCFL/SDCFL GaAs circuits. The model has been implemented in a prototype timing analyzer. Input-slope influences and overlapping input transitions are taken into account. The simulation results show that the proposed model can predict the delay time within 15% error and with a speed-up of three orders of magnitude for several circuits tested as compared with HSPICE simulations.<>
{"title":"GASTIM: A timing analyzer for GaAs digital circuits","authors":"A. Hernández, Luis Gómez, A. Núñez","doi":"10.1109/EURDAC.1993.410636","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410636","url":null,"abstract":"A methodology is presented to calculate delays in DCFL/SDCFL GaAs circuits. The model has been implemented in a prototype timing analyzer. Input-slope influences and overlapping input transitions are taken into account. The simulation results show that the proposed model can predict the delay time within 15% error and with a speed-up of three orders of magnitude for several circuits tested as compared with HSPICE simulations.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"20 13-14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123588678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410641
S. Kanjilal, S. Chakradhar, V. Agrawal
The authors present new algorithms for embedding a test function in the state diagram of a finite state machine. When possible, the test function is embedded in the given object machine without using an extra input line. When such embedding is not possible, an extra input line is added to the object machine to make the embedding possible. For the extra input case, partition theory and the state variable dependencies of the object machine are used to obtain a mapping of the test machine states onto the object machine states. This mapping introduces a minimum number of extra state variable dependencies in the augmented machine as compared to the dependencies in the object machine. Experimental results on several MCNC benchmarks show that the method yields augmented machine implementations that have smaller areas than the corresponding full scan designs. The test generation complexity for the augmented machine implementation is the same as that for a full scan design. The embedding of test functions in machines specified as interconnection of finite state machines is also considered.<>
{"title":"Test function embedding algorithms with application to interconnected finite state machines","authors":"S. Kanjilal, S. Chakradhar, V. Agrawal","doi":"10.1109/EURDAC.1993.410641","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410641","url":null,"abstract":"The authors present new algorithms for embedding a test function in the state diagram of a finite state machine. When possible, the test function is embedded in the given object machine without using an extra input line. When such embedding is not possible, an extra input line is added to the object machine to make the embedding possible. For the extra input case, partition theory and the state variable dependencies of the object machine are used to obtain a mapping of the test machine states onto the object machine states. This mapping introduces a minimum number of extra state variable dependencies in the augmented machine as compared to the dependencies in the object machine. Experimental results on several MCNC benchmarks show that the method yields augmented machine implementations that have smaller areas than the corresponding full scan designs. The test generation complexity for the augmented machine implementation is the same as that for a full scan design. The embedding of test functions in machines specified as interconnection of finite state machines is also considered.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134050131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410652
V. A. Koval, A. Ostapchuk, Igor V. Farmaga, D. Fedasyuk
The problem of microelectronic device thermal field analysis has been formalized. The presented method of the initial and boundary problem formalization makes it possible to take account of various boundary conditions and to carry out adaptation of the received mathematical model to the object of designing and operation conditions by CAD methods. The combination of numerical and analytical methods has been developed for solution of three-dimensional parabolic equations. The said combination makes it possible to receive both stationary and nonstationary solutions as well as to approximate in boundary conditions along z coordinate the nonhomogeneity of functions and their derivatives along x,y coordinates. The testing (investigation) of the computational accuracy and the adequacy of the received mathematical models and algorithms has been carried out. The software system of microelectronic devices thermal design has been developed, the system making it possible to decrease the development time and to improve the quality of microelectronic devices.<>
{"title":"CAD: The numerical and analytical methods combined for the analysis of IC's thermal fields","authors":"V. A. Koval, A. Ostapchuk, Igor V. Farmaga, D. Fedasyuk","doi":"10.1109/EURDAC.1993.410652","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410652","url":null,"abstract":"The problem of microelectronic device thermal field analysis has been formalized. The presented method of the initial and boundary problem formalization makes it possible to take account of various boundary conditions and to carry out adaptation of the received mathematical model to the object of designing and operation conditions by CAD methods. The combination of numerical and analytical methods has been developed for solution of three-dimensional parabolic equations. The said combination makes it possible to receive both stationary and nonstationary solutions as well as to approximate in boundary conditions along z coordinate the nonhomogeneity of functions and their derivatives along x,y coordinates. The testing (investigation) of the computational accuracy and the adequacy of the received mathematical models and algorithms has been carried out. The software system of microelectronic devices thermal design has been developed, the system making it possible to decrease the development time and to improve the quality of microelectronic devices.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129341196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410676
H. Juan, N. D. Holmes, Smita Bakshi, D. Gajski
The authors present a high-level design modeling methodology with three modeling levels: a specification level, an interface level, and a functional level. They demonstrate the methodology on a RISC processor design. All models have been implemented in VHDL and simulated on a SPARC 1 workstation using the ZYCAD VHDL simulator, version 1.0a. Experimental results demonstrate the feasibility and usefulness of the methodology.<>
{"title":"Top-down modeling of RISC processors in VHDL","authors":"H. Juan, N. D. Holmes, Smita Bakshi, D. Gajski","doi":"10.1109/EURDAC.1993.410676","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410676","url":null,"abstract":"The authors present a high-level design modeling methodology with three modeling levels: a specification level, an interface level, and a functional level. They demonstrate the methodology on a RISC processor design. All models have been implemented in VHDL and simulated on a SPARC 1 workstation using the ZYCAD VHDL simulator, version 1.0a. Experimental results demonstrate the feasibility and usefulness of the methodology.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134476417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410670
M. Robinson
A design flow paradigm that integrates technology independent boundary scan synthesis into a chip design methodology is presented. The approach accommodates multiple vendor boundary scan technologies and the requirements of (sometimes non-1149.1-compliant) user specified boundary scan architectures. Boundary scan synthesis is described and design-specific requirements, 1149.1 compliance verification, boundary scan manufacturing test, and interfacing with the board and system test environments are discussed.<>
{"title":"Technology independent boundary scan synthesis (design flow issues)","authors":"M. Robinson","doi":"10.1109/EURDAC.1993.410670","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410670","url":null,"abstract":"A design flow paradigm that integrates technology independent boundary scan synthesis into a chip design methodology is presented. The approach accommodates multiple vendor boundary scan technologies and the requirements of (sometimes non-1149.1-compliant) user specified boundary scan architectures. Boundary scan synthesis is described and design-specific requirements, 1149.1 compliance verification, boundary scan manufacturing test, and interfacing with the board and system test environments are discussed.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"92 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131263302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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