Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410688
F. Rammig
The necessity for a common modeling approach for heterogeneous systems is discussed. As an example for such a modeling technique, extended predicate/transition nets (Pr/T-Nets) are introduced. These nets can combine modeling in a declarative way by means of first order logic with an operational interpretation inherited from Petri nets. The added concepts of hierarchy and recursion allow the description of extremely complex systems. Three applications of Pr/T-Nets are shown: control of complex design systems, timing analysis, and the implementation of communication protocols.<>
{"title":"Modelling aspects of system level design","authors":"F. Rammig","doi":"10.1109/EURDAC.1993.410688","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410688","url":null,"abstract":"The necessity for a common modeling approach for heterogeneous systems is discussed. As an example for such a modeling technique, extended predicate/transition nets (Pr/T-Nets) are introduced. These nets can combine modeling in a declarative way by means of first order logic with an operational interpretation inherited from Petri nets. The added concepts of hierarchy and recursion allow the description of extremely complex systems. Three applications of Pr/T-Nets are shown: control of complex design systems, timing analysis, and the implementation of communication protocols.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134112179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410674
V. Pla, J. Santucci, N. Giambiasi
A new automatic test generation principle based on a formal modeling of VHDL behavioral descriptions is proposed. Using to the finite state machine representation and a formalism close to that of Petri nets, the authors define two models which represent all the concepts associated with a VHDL description. They then propose a generation principle which uses both forward and backward time processing.<>
{"title":"On the modeling and testing of VHDL behavioral descriptions of sequential circuits","authors":"V. Pla, J. Santucci, N. Giambiasi","doi":"10.1109/EURDAC.1993.410674","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410674","url":null,"abstract":"A new automatic test generation principle based on a formal modeling of VHDL behavioral descriptions is proposed. Using to the finite state machine representation and a formalism close to that of Petri nets, the authors define two models which represent all the concepts associated with a VHDL description. They then propose a generation principle which uses both forward and backward time processing.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"169 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131692773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410608
A. Alomary, Takeharu Nakata, Y. Honma, J. Sato, N. Hikichi, M. Imai
The current implementation and experimental results of the PEAS-1 (practical environment for application specific integrated processor (ASIP) development - Version I) system are described. The PEAS-I system is a hardware/software co-design system for ASIP development. The input to the system is a set of application programs written in C language, an associated data set, and design constraints such as chip area and power consumption. The system generates an optimized CPU core design in the form of an HDL, as well as a set of application program development tools, such as a C compiler, assembler, and simulator. A novel method that formulates the design of an optimal instruction set using an integer programming approach is described. A tool that enables the designer to predict the chip area and performance of the design before the detailed design is completed is discussed. Application program development tools are generated in addition to the ASIP hardware design.<>
{"title":"PEAS-I: A hardware/software co-design system for ASIPs","authors":"A. Alomary, Takeharu Nakata, Y. Honma, J. Sato, N. Hikichi, M. Imai","doi":"10.1109/EURDAC.1993.410608","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410608","url":null,"abstract":"The current implementation and experimental results of the PEAS-1 (practical environment for application specific integrated processor (ASIP) development - Version I) system are described. The PEAS-I system is a hardware/software co-design system for ASIP development. The input to the system is a set of application programs written in C language, an associated data set, and design constraints such as chip area and power consumption. The system generates an optimized CPU core design in the form of an HDL, as well as a set of application program development tools, such as a C compiler, assembler, and simulator. A novel method that formulates the design of an optimal instruction set using an integer programming approach is described. A tool that enables the designer to predict the chip area and performance of the design before the detailed design is completed is discussed. Application program development tools are generated in addition to the ASIP hardware design.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123450168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410657
U. Weinmann, W. Rosenstiel
A new technology mapping technique for implementing sequential circuits by table lookup FPGAs (field programmable gate arrays) with predefined memory elements is presented. Most mapping algorithms in this field are restricted to combinational logic. The presented methods for optimizing delay and area consumption are based on a redesign of the circuit with retiming and specific sequential transformations. Experimental results of several benchmark circuits show an improvement of up to 20% less area consumption and delay in comparison to existing tools.<>
{"title":"Technology mapping for sequential circuits based on retiming techniques","authors":"U. Weinmann, W. Rosenstiel","doi":"10.1109/EURDAC.1993.410657","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410657","url":null,"abstract":"A new technology mapping technique for implementing sequential circuits by table lookup FPGAs (field programmable gate arrays) with predefined memory elements is presented. Most mapping algorithms in this field are restricted to combinational logic. The presented methods for optimizing delay and area consumption are based on a redesign of the circuit with retiming and specific sequential transformations. Experimental results of several benchmark circuits show an improvement of up to 20% less area consumption and delay in comparison to existing tools.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123659419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410651
J. Berrie, A. Slade
The authors introduce a new tool to assist in ensuring electromagnetic compatibility (EMC): an expert system for measuring EMC design rules during printed circuit board (PCB) or multi-chip module (MCM) layout. The nature of the tool and its place in the design process are discussed and the perceived merits of this approach are presented.<>
{"title":"A practical approach to EMC for printed circuit board (PCB) and multichip module (MCM) design","authors":"J. Berrie, A. Slade","doi":"10.1109/EURDAC.1993.410651","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410651","url":null,"abstract":"The authors introduce a new tool to assist in ensuring electromagnetic compatibility (EMC): an expert system for measuring EMC design rules during printed circuit board (PCB) or multi-chip module (MCM) layout. The nature of the tool and its place in the design process are discussed and the perceived merits of this approach are presented.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128351945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410664
Olav Schettler, A. Bredenfeld
The authors present a data model for design representation. BEPPO (Basic, Efficient, Portable, Persistent Objects) provides a data model, schema language, and schema invariant programming interface geared towards the representation of arbitrary design data. Its domain invariant concepts and well-defined interfaces to applications and to the underlying storage manager make it suitable as a flexible basis for design data storage and manipulation in a CAD framework. BEPPO served as a vehicle to implement CFIs Design Representation Programming Interface.<>
{"title":"BEPPO: A data model for design representation","authors":"Olav Schettler, A. Bredenfeld","doi":"10.1109/EURDAC.1993.410664","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410664","url":null,"abstract":"The authors present a data model for design representation. BEPPO (Basic, Efficient, Portable, Persistent Objects) provides a data model, schema language, and schema invariant programming interface geared towards the representation of arbitrary design data. Its domain invariant concepts and well-defined interfaces to applications and to the underlying storage manager make it suitable as a flexible basis for design data storage and manipulation in a CAD framework. BEPPO served as a vehicle to implement CFIs Design Representation Programming Interface.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115117512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410625
T. Koide, S. Wakabayashi, N. Yoshida
The authors present a new global routing algorithm for over-the-cell routing in standard cell layout, which determines global routes for each net both in channels and on over-the-cell regions. The goal of the algorithm is to minimize the total channel height in the final lyout. The proposed algorithm is implemented in the C language on a SPARC station 2 and tested with the benchmarks distributed from MCNC, whose cell placements were generated with TimberWolfSC4.2c. Experimental results show that the new routing algorithm reduces the channel height by about 13.1% compared to the conventional routing algorithm.<>
{"title":"A new global routing algorithm for over-the-cell routing in standard cell layouts","authors":"T. Koide, S. Wakabayashi, N. Yoshida","doi":"10.1109/EURDAC.1993.410625","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410625","url":null,"abstract":"The authors present a new global routing algorithm for over-the-cell routing in standard cell layout, which determines global routes for each net both in channels and on over-the-cell regions. The goal of the algorithm is to minimize the total channel height in the final lyout. The proposed algorithm is implemented in the C language on a SPARC station 2 and tested with the benchmarks distributed from MCNC, whose cell placements were generated with TimberWolfSC4.2c. Experimental results show that the new routing algorithm reduces the channel height by about 13.1% compared to the conventional routing algorithm.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115126809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EURDAC.1993.410639
M. Gossel, H. Jurgensen
The authors show how to combine a conventional built-in self-test method with a simple method for online error detection for combinational circuits. The output sequence of one or more components of the signature analyzer is monitored, in test mode, by an error detection circuit consisting of a one-cover and a zero-cover. The cover circuits need to detect only such faults that are masked by the signature analyzer. Because of a large number of don't-care conditions for the cover circuits the hardware overhead is very low. All faults in the fault model under consideration are detected either by the cover circuits or, due to an erroneous signature, by the signature analyzer.<>
{"title":"Monitoring BIST by covers","authors":"M. Gossel, H. Jurgensen","doi":"10.1109/EURDAC.1993.410639","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410639","url":null,"abstract":"The authors show how to combine a conventional built-in self-test method with a simple method for online error detection for combinational circuits. The output sequence of one or more components of the signature analyzer is monitored, in test mode, by an error detection circuit consisting of a one-cover and a zero-cover. The cover circuits need to detect only such faults that are masked by the signature analyzer. Because of a large number of don't-care conditions for the cover circuits the hardware overhead is very low. All faults in the fault model under consideration are detected either by the cover circuits or, due to an erroneous signature, by the signature analyzer.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115800430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EURDAC.1993.410618
Too-Seng Tia, C. Liu
The authors present a new performance-driven macro-cell placement algorithm. They introduce the concept of a window which is an estimate of the initial placement of a module. There are three phases in the algorithm. In phase one, an initial window for each module is constructed. In phase two, a novel force-directed approach is used to reduce the size of each window in an iterative process so as to determine an initial placement of the modules. In phase three, the same force-directed concept is used to refine the placement. Timing and physical constraints are used in all phases to guide the placement process. The effectiveness of the algorithm is demonstrated by comparing the experimental results with those produced by TimberWolfMC and the GVL algorithm.<>
{"title":"A new performance driven macro-cell placement algorithm","authors":"Too-Seng Tia, C. Liu","doi":"10.1109/EURDAC.1993.410618","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410618","url":null,"abstract":"The authors present a new performance-driven macro-cell placement algorithm. They introduce the concept of a window which is an estimate of the initial placement of a module. There are three phases in the algorithm. In phase one, an initial window for each module is constructed. In phase two, a novel force-directed approach is used to reduce the size of each window in an iterative process so as to determine an initial placement of the modules. In phase three, the same force-directed concept is used to refine the placement. Timing and physical constraints are used in all phases to guide the placement process. The effectiveness of the algorithm is demonstrated by comparing the experimental results with those produced by TimberWolfMC and the GVL algorithm.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"353 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131243844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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