Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927934
R. Joshi, R. Manatad, C. Tangpuz
In the semiconductor industry, reducing the size of power electronics has been limited by the thermal performance of miniature surface mount packages. A key development in the industry has been the availability of more efficient silicon, allowing a lower on resistance die (RDS(ON)) to fit in a smaller package. However new innovative surface mount packages such as the MOSFET BGA package which combine the small form factors of miniature packages with the thermal performance of much larger packages have been developed. These new packages have the added advantage of virtually eliminating the package resistance. However packages which involve the BGA form factor require different handling equipment as compared to leaded surface mount devices, slowing their adoption rate. In the flip chip in a leaded molded package (FLMP), these shortcomings have been addressed preserving the advantages of miniature packages such as the MOSFET BGA package. A die up to 75% larger in area as compared to its wire bonded counterpart with estimated /spl theta/jc of <0.5/spl deg/C/W are typical characteristics of this package. Packages of a low profile (<1.0 mm height) can also be easily constructed due to the absence of wire bonds. In addition, the construction of the package lends itself well to a "lead free" or a green package. The paper will describe the construction of the package, the process flow, the performance and early reliability results.
{"title":"Flip chip in leaded molded package (FLMP)","authors":"R. Joshi, R. Manatad, C. Tangpuz","doi":"10.1109/ECTC.2001.927934","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927934","url":null,"abstract":"In the semiconductor industry, reducing the size of power electronics has been limited by the thermal performance of miniature surface mount packages. A key development in the industry has been the availability of more efficient silicon, allowing a lower on resistance die (RDS(ON)) to fit in a smaller package. However new innovative surface mount packages such as the MOSFET BGA package which combine the small form factors of miniature packages with the thermal performance of much larger packages have been developed. These new packages have the added advantage of virtually eliminating the package resistance. However packages which involve the BGA form factor require different handling equipment as compared to leaded surface mount devices, slowing their adoption rate. In the flip chip in a leaded molded package (FLMP), these shortcomings have been addressed preserving the advantages of miniature packages such as the MOSFET BGA package. A die up to 75% larger in area as compared to its wire bonded counterpart with estimated /spl theta/jc of <0.5/spl deg/C/W are typical characteristics of this package. Packages of a low profile (<1.0 mm height) can also be easily constructed due to the absence of wire bonds. In addition, the construction of the package lends itself well to a \"lead free\" or a green package. The paper will describe the construction of the package, the process flow, the performance and early reliability results.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123861558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927731
J.B. Breedis
Clearly, the most daunting challenge facing developers of passively aligned optical packages is that of meeting the manufacturing tolerances necessary to achieve adequate coupling between a laser source and an outgoing optical fiber. As these tolerances continue to press the limits of available manufacturing technology, the need for optimized designs becomes obvious. Unfortunately, the arrival at an optimized design is complicated by the often complex interaction of many variables ranging from component process variability, to device placement on assembly to optical fiber core concentricity and fiber diameter. In response to this, the current work describes a simplified approach towards optimizing the design of a silicon waferboard optical subassembly by ways of Monte Carlo analysis. Issues ranging from the impact of silicon process variables to device placement to fiber geometric variability are combined to predict anticipated assembly yields. Key control variables are identified enabling the arrival at optimized designs in a reasonably straightforward manner.
{"title":"Monte Carlo tolerance analysis of a passively aligned silicon waferboard package","authors":"J.B. Breedis","doi":"10.1109/ECTC.2001.927731","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927731","url":null,"abstract":"Clearly, the most daunting challenge facing developers of passively aligned optical packages is that of meeting the manufacturing tolerances necessary to achieve adequate coupling between a laser source and an outgoing optical fiber. As these tolerances continue to press the limits of available manufacturing technology, the need for optimized designs becomes obvious. Unfortunately, the arrival at an optimized design is complicated by the often complex interaction of many variables ranging from component process variability, to device placement on assembly to optical fiber core concentricity and fiber diameter. In response to this, the current work describes a simplified approach towards optimizing the design of a silicon waferboard optical subassembly by ways of Monte Carlo analysis. Issues ranging from the impact of silicon process variables to device placement to fiber geometric variability are combined to predict anticipated assembly yields. Key control variables are identified enabling the arrival at optimized designs in a reasonably straightforward manner.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124516964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927955
N. Na, M. Swaminathan, J. Libous, D. O'connor
This paper presents simulation and analysis of core switching noise on a CMOS test vehicle. The test vehicle consists of a ceramic ball grid array (CBGA) package on a printed circuit board (PCB). The entire test vehicle has been modeled by accounting for all the plane resonances using the cavity resonator method. The models included both the on-chip and off-chip decoupling capacitors. Using both time domain and frequency domain simulations, the role of plane resonances on power supply noise for fast current edge rates has been discussed. The models have been constructed to amplify certain parts of the test vehicle during simulations.
{"title":"Modeling and simulation of core switching noise on a package and board","authors":"N. Na, M. Swaminathan, J. Libous, D. O'connor","doi":"10.1109/ECTC.2001.927955","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927955","url":null,"abstract":"This paper presents simulation and analysis of core switching noise on a CMOS test vehicle. The test vehicle consists of a ceramic ball grid array (CBGA) package on a printed circuit board (PCB). The entire test vehicle has been modeled by accounting for all the plane resonances using the cavity resonator method. The models included both the on-chip and off-chip decoupling capacitors. Using both time domain and frequency domain simulations, the role of plane resonances on power supply noise for fast current edge rates has been discussed. The models have been constructed to amplify certain parts of the test vehicle during simulations.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121242178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927765
M. Lebby
With the recent frenzy of new start-ups and acquisition activity in the optical communications space, companies are positioning themselves to better provide customers with the solutions they need for higher bandwidth and performance in the network. Coupled with staggering valuations, the expectations set by the financial institutions puts heavy pressure on creativity in commercializing optoelectronic solutions. Clearly, for high performance and efficient networks, the industry needs to be enabled by new optoelectronic component technologies and new system architectures. This paper reviews and roadmaps some of the key optoelectronic component and module based technologies that will be needed to support customer expectations over the next decade. The paper has two themes: firstly, optical technologies and what they can offer in terms of performance and bandwidth, and secondly, a view on technology roadmaps and where optical technologies are heading. Binding the two themes together will be a critical view of optoelectronic integrated circuits (OEICs). OEICs are well documented in the R&D establishment with over 15 years of papers, however, are gradually emerging as commercial products in optical networking architectures. This paper will review progress made and what the industry can expect from the integration of optical components for better performance metrics as the industry moves forward. The key metrics will include the silicon effect on manufacturing planar components such as optical multipliers (also known as mux and demux), both with add/drop capabilities as well as other associated planar components such as variable optical attenuators, switches, amplifiers etc. As in the majority of OEIC designs, different IC functions with emitter (laser) and receiver (detector) solutions will be discussed.
{"title":"Optical components and their role in optical networks","authors":"M. Lebby","doi":"10.1109/ECTC.2001.927765","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927765","url":null,"abstract":"With the recent frenzy of new start-ups and acquisition activity in the optical communications space, companies are positioning themselves to better provide customers with the solutions they need for higher bandwidth and performance in the network. Coupled with staggering valuations, the expectations set by the financial institutions puts heavy pressure on creativity in commercializing optoelectronic solutions. Clearly, for high performance and efficient networks, the industry needs to be enabled by new optoelectronic component technologies and new system architectures. This paper reviews and roadmaps some of the key optoelectronic component and module based technologies that will be needed to support customer expectations over the next decade. The paper has two themes: firstly, optical technologies and what they can offer in terms of performance and bandwidth, and secondly, a view on technology roadmaps and where optical technologies are heading. Binding the two themes together will be a critical view of optoelectronic integrated circuits (OEICs). OEICs are well documented in the R&D establishment with over 15 years of papers, however, are gradually emerging as commercial products in optical networking architectures. This paper will review progress made and what the industry can expect from the integration of optical components for better performance metrics as the industry moves forward. The key metrics will include the silicon effect on manufacturing planar components such as optical multipliers (also known as mux and demux), both with add/drop capabilities as well as other associated planar components such as variable optical attenuators, switches, amplifiers etc. As in the majority of OEIC designs, different IC functions with emitter (laser) and receiver (detector) solutions will be discussed.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129387129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927783
T. Lee, Taek-Yeong Lee, K. Tu
This paper applies an analogy between heat flow and current flow to examine the current density distribution in a solder interconnect, which has a direct relationship with the atomic flux movement. From a 3D heat conduction analysis, we discover that the heat flux distribution in the solder bump is a strong function of the direction of heat flow. If the heat flow turns 90 degrees when it leaves the solder bump, the high heat flux region will also turn 90 degrees. From a cross-sectional view of the mean heat flux, the high heat flux (or current flux) region in the solder moves from the top of the UBM region to the lower right corner, and the right side of the solder has the highest flux density. This result correlates well with the experimental data where the measured atomic flux in the left side of the solder is less than in the right side. Two other cases with 0 and 180-degree heat flows also illustrate the difference in heat flux distribution. This suggests that the current density distribution in the solder changes as the direction of the current flow changes.
{"title":"A study of electromigration in 3D flip chip solder joint using numerical simulation of heat flux and current density","authors":"T. Lee, Taek-Yeong Lee, K. Tu","doi":"10.1109/ECTC.2001.927783","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927783","url":null,"abstract":"This paper applies an analogy between heat flow and current flow to examine the current density distribution in a solder interconnect, which has a direct relationship with the atomic flux movement. From a 3D heat conduction analysis, we discover that the heat flux distribution in the solder bump is a strong function of the direction of heat flow. If the heat flow turns 90 degrees when it leaves the solder bump, the high heat flux region will also turn 90 degrees. From a cross-sectional view of the mean heat flux, the high heat flux (or current flux) region in the solder moves from the top of the UBM region to the lower right corner, and the right side of the solder has the highest flux density. This result correlates well with the experimental data where the measured atomic flux in the left side of the solder is less than in the right side. Two other cases with 0 and 180-degree heat flows also illustrate the difference in heat flux distribution. This suggests that the current density distribution in the solder changes as the direction of the current flow changes.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"326 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115872225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927811
M. Joodaki, G. Kompa, T. Leinhos, R. Kassing, H. Hillmer
It is well known that thermal stress not only effects the reliability and life time of the packaging but also the device characteristics, which is crucial in microwave and millimeter wave design. A three dimensional finite element (3DFE) thermal stress simulator, scanning probe microscopy (SPM) measurements and nanometer surface profiler (DEKTAK) accompanied with a Peltier element (PE) have been used to determine the thermal stress distribution in the standard structure of QMIT. In this method by measuring and mapping the surface profile of Si-wafer around the embedded devices using SPM and DEKTAK the induced thermal stress is determined. Effects of different parameters such as baking temperature, power dissipation of the embedded GaAs-FET, geometry and elastic properties of thermal conductive epoxy have been described in detail. In all simulations a new model of QMIT with a minimum-number of nodes has been introduced. Remarkable agreement between calculated and measured displacements created by thermal stress was found.
{"title":"Simulation and measurement of thermal stress in quasi-monolithic integration technology (QMIT)","authors":"M. Joodaki, G. Kompa, T. Leinhos, R. Kassing, H. Hillmer","doi":"10.1109/ECTC.2001.927811","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927811","url":null,"abstract":"It is well known that thermal stress not only effects the reliability and life time of the packaging but also the device characteristics, which is crucial in microwave and millimeter wave design. A three dimensional finite element (3DFE) thermal stress simulator, scanning probe microscopy (SPM) measurements and nanometer surface profiler (DEKTAK) accompanied with a Peltier element (PE) have been used to determine the thermal stress distribution in the standard structure of QMIT. In this method by measuring and mapping the surface profile of Si-wafer around the embedded devices using SPM and DEKTAK the induced thermal stress is determined. Effects of different parameters such as baking temperature, power dissipation of the embedded GaAs-FET, geometry and elastic properties of thermal conductive epoxy have been described in detail. In all simulations a new model of QMIT with a minimum-number of nodes has been introduced. Remarkable agreement between calculated and measured displacements created by thermal stress was found.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"519 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116256340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927806
Deok-Hoon Kim, P. Elenius
SAC (SnAgCu) lead free solder is currently the alloy of choice by the electronics industry for lead free applications. In this study multiple WLPs (Wafer Level Packages) called the Ultra CSP/sup TM/ from Flip Chip Technologies were put into a TC (Thermal Cycling) test. The goal was to see if the current AI/NiV/Cu UBM (Under Bump Metallurgy) system that has been used for eutectic SnPb solder Ultra CSP would be suitable for the SAC lead free solder version. Both SAC and eutectic SnPb solders were tested together. In this TC test, two parts were taken out of the TC chamber after every 200 cycles for monitoring the characteristics of deformation and crack growth in the solder joints. The result showed eutectic SnPb solder joints might have a global and uniform deformation in the high temperature regime. On the other hand, in the low temperature regime, the deformation is localized only at chip side solder joint while maintaining the global deformed shape from the previous high temperature regime. This localized deformation at low temperature regime created a large shear dislocation at chip side solder joint, with the crack initiating at the outside corner of the solder joint and growing toward the inside of chip. On the other hand, the SAC solder joints did not show that kind of large sliding at chip side solder joint. Instead two cracks initiated at both the outside and inside of chip side solder joint and grew at almost the same rate. There was very good agreement between Weibull life and the time that the cracked length (%) goes to 100% in eutectic SnPb solder. Extending this correlation to SAC lead free solder appears to be possible. Indications are that there will be an improvement, but there was insufficient data to make a conclusive statement as to reliability improvement. Tests are underway to confirm this.
{"title":"Deformation and crack growth characteristics of SnAgCu vs 63Sn/Pb solder joints on a WLP in thermal cycle testing","authors":"Deok-Hoon Kim, P. Elenius","doi":"10.1109/ECTC.2001.927806","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927806","url":null,"abstract":"SAC (SnAgCu) lead free solder is currently the alloy of choice by the electronics industry for lead free applications. In this study multiple WLPs (Wafer Level Packages) called the Ultra CSP/sup TM/ from Flip Chip Technologies were put into a TC (Thermal Cycling) test. The goal was to see if the current AI/NiV/Cu UBM (Under Bump Metallurgy) system that has been used for eutectic SnPb solder Ultra CSP would be suitable for the SAC lead free solder version. Both SAC and eutectic SnPb solders were tested together. In this TC test, two parts were taken out of the TC chamber after every 200 cycles for monitoring the characteristics of deformation and crack growth in the solder joints. The result showed eutectic SnPb solder joints might have a global and uniform deformation in the high temperature regime. On the other hand, in the low temperature regime, the deformation is localized only at chip side solder joint while maintaining the global deformed shape from the previous high temperature regime. This localized deformation at low temperature regime created a large shear dislocation at chip side solder joint, with the crack initiating at the outside corner of the solder joint and growing toward the inside of chip. On the other hand, the SAC solder joints did not show that kind of large sliding at chip side solder joint. Instead two cracks initiated at both the outside and inside of chip side solder joint and grew at almost the same rate. There was very good agreement between Weibull life and the time that the cracked length (%) goes to 100% in eutectic SnPb solder. Extending this correlation to SAC lead free solder appears to be possible. Indications are that there will be an improvement, but there was insufficient data to make a conclusive statement as to reliability improvement. Tests are underway to confirm this.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114611012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927968
Tee-Onn Chong, Seng-Hooi Ong, T. Yew, C. Chung, R. Sankman
The semiconductor industry at large is migrating from wire bond packaging to flip chip packaging due to electrical performance requirements. With the removal of the highly resistive and inductive wire bonds, high-speed buses achieve well-controlled characteristic impedance for signal wave propagation and lower impedance for the power delivery network. However, a disadvantage of flip chip packaging is its lower input/output (I/O) routing density when compared to wire bond packaging. To meet the high I/O count for certain products, innovative flip chip bump patterns and creative routing options are needed. This paper will outline some innovative package design concepts on both die to package, defined as level 1 interconnect, and package to motherboard (MB), defined as level 2 interconnect, to increase the I/O signal routing density without increasing the package or MB cost.
{"title":"Low cost flip chip package design concepts for high density I/O","authors":"Tee-Onn Chong, Seng-Hooi Ong, T. Yew, C. Chung, R. Sankman","doi":"10.1109/ECTC.2001.927968","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927968","url":null,"abstract":"The semiconductor industry at large is migrating from wire bond packaging to flip chip packaging due to electrical performance requirements. With the removal of the highly resistive and inductive wire bonds, high-speed buses achieve well-controlled characteristic impedance for signal wave propagation and lower impedance for the power delivery network. However, a disadvantage of flip chip packaging is its lower input/output (I/O) routing density when compared to wire bond packaging. To meet the high I/O count for certain products, innovative flip chip bump patterns and creative routing options are needed. This paper will outline some innovative package design concepts on both die to package, defined as level 1 interconnect, and package to motherboard (MB), defined as level 2 interconnect, to increase the I/O signal routing density without increasing the package or MB cost.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"223 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127178108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.927883
I. Doerr, L. Hwang, G. Sommer, H. Oppermann, L. Li, M. Petras, S. Korf, F. Sahli, T. Myers, M. Miller, W. John
Skyrocketing growth in the cellular personal communications services (PCS) sector has fueled the needs for higher density, more functionality, and greater performance on both handset and base stations. Third generation wireless standards, which require hardware upgrades, loom on the horizon. RF component suppliers are scrambling to find solutions at the IC, package, and PCB levels to meet these challenges. RF module packaging is considered as one of the low cost solutions for the future wireless products. One of the critical design needs for RF interconnects is to understand the electrical performance of wire bond (the RF interconnect of choice) at and above frequency of interest, and to determine the performance limit for the wire bond chip-to-substrate interconnect. The availability of design kit or library would result in a substantial reduction in design cycle times. Using wire bond as example, this paper illustrates the developmental stages that turn electromagnetic characteristics of a physical structure into a design library. Fullwave simulation using Ansoft HFSS and compact models extraction using optimization tool for wire bond are shown, followed by in-depth discussions of wire bond parameterized models. Validation of parameterized model by measurement is presented.
{"title":"Parameterized models for a RF chip-to-substrate interconnect","authors":"I. Doerr, L. Hwang, G. Sommer, H. Oppermann, L. Li, M. Petras, S. Korf, F. Sahli, T. Myers, M. Miller, W. John","doi":"10.1109/ECTC.2001.927883","DOIUrl":"https://doi.org/10.1109/ECTC.2001.927883","url":null,"abstract":"Skyrocketing growth in the cellular personal communications services (PCS) sector has fueled the needs for higher density, more functionality, and greater performance on both handset and base stations. Third generation wireless standards, which require hardware upgrades, loom on the horizon. RF component suppliers are scrambling to find solutions at the IC, package, and PCB levels to meet these challenges. RF module packaging is considered as one of the low cost solutions for the future wireless products. One of the critical design needs for RF interconnects is to understand the electrical performance of wire bond (the RF interconnect of choice) at and above frequency of interest, and to determine the performance limit for the wire bond chip-to-substrate interconnect. The availability of design kit or library would result in a substantial reduction in design cycle times. Using wire bond as example, this paper illustrates the developmental stages that turn electromagnetic characteristics of a physical structure into a design library. Fullwave simulation using Ansoft HFSS and compact models extraction using optimization tool for wire bond are shown, followed by in-depth discussions of wire bond parameterized models. Validation of parameterized model by measurement is presented.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127509295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-29DOI: 10.1109/ECTC.2001.928018
Y. Rao, J. Yue, C. Wong
Embedded capacitor technology can improve electrical performance and reduce assembly cost compared with traditional discrete capacitor technology. Polymer-ceramic composites have been of great interest as embedded capacitor material because they combine the processability of polymers with the desired electrical properties of ceramics. A novel nano-structure polymer-ceramic composite with very high dielectric constant (/spl epsiv//sub /spl tau//=150) has been developed in this work. RF application of embedded capacitors requires that insulating material have high dielectric constant in higher frequency (GHz), low leakage current, high breakdown voltage and high reliability. A set of electric tests have been conducted in this work to characterize the properties of the in house developed novel high dielectric constant polymer-ceramic nano-composite. Results show that this material has fair high dielectric constant in RF range, low electric leakage and high breakdown voltage. An embedded capacitor prototype with capacitance density of 35 nF/cm/sup 2/ has been manufactured using this nano-composite and spinning coating technology. The design of embedded passives is very important to its practical application. The commercial finite element software ANSYS and electric simulation software SPICE were used for the simulation of embedded capacitor performance in the RF range. This novel nano-composite can be used for the integral capacitors in the RF applications.
{"title":"High K polymer-ceramic nano-composite development, characterization, and modeling for embedded capacitor RF application","authors":"Y. Rao, J. Yue, C. Wong","doi":"10.1109/ECTC.2001.928018","DOIUrl":"https://doi.org/10.1109/ECTC.2001.928018","url":null,"abstract":"Embedded capacitor technology can improve electrical performance and reduce assembly cost compared with traditional discrete capacitor technology. Polymer-ceramic composites have been of great interest as embedded capacitor material because they combine the processability of polymers with the desired electrical properties of ceramics. A novel nano-structure polymer-ceramic composite with very high dielectric constant (/spl epsiv//sub /spl tau//=150) has been developed in this work. RF application of embedded capacitors requires that insulating material have high dielectric constant in higher frequency (GHz), low leakage current, high breakdown voltage and high reliability. A set of electric tests have been conducted in this work to characterize the properties of the in house developed novel high dielectric constant polymer-ceramic nano-composite. Results show that this material has fair high dielectric constant in RF range, low electric leakage and high breakdown voltage. An embedded capacitor prototype with capacitance density of 35 nF/cm/sup 2/ has been manufactured using this nano-composite and spinning coating technology. The design of embedded passives is very important to its practical application. The commercial finite element software ANSYS and electric simulation software SPICE were used for the simulation of embedded capacitor performance in the RF range. This novel nano-composite can be used for the integral capacitors in the RF applications.","PeriodicalId":340217,"journal":{"name":"2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122038516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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