Pub Date : 2010-05-23DOI: 10.1109/MWSYM.2010.5515392
C. Lai, T. Ma
A novel synthesized microstrip line with quasi-elliptic response is proposed in this paper. By utilizing quasi-lumped elements, the proposed synthesized lines are capable of reducing the circuit size with good slow-wave property. Benefitted from the quasi-elliptic response, signal suppression capability is introduced to the synthesized line at the harmonic frequencies. The design concept, circuit geometry, equivalent lumped circuit model, and simulated and measured results are carefully investigated and discussed. Based on the new synthesized microstrip line, a miniaturized quadrature hybrid coupler with harmonic suppressions is designed as a demonstrated example. The signal rejection levels are higher than 20 and 40 dB at the second and third harmonics, respectively. At the mean time, the size reduction percentage is 50%.
{"title":"Novel synthesized microstrip line with quasi-elliptic response for harmonic suppressions","authors":"C. Lai, T. Ma","doi":"10.1109/MWSYM.2010.5515392","DOIUrl":"https://doi.org/10.1109/MWSYM.2010.5515392","url":null,"abstract":"A novel synthesized microstrip line with quasi-elliptic response is proposed in this paper. By utilizing quasi-lumped elements, the proposed synthesized lines are capable of reducing the circuit size with good slow-wave property. Benefitted from the quasi-elliptic response, signal suppression capability is introduced to the synthesized line at the harmonic frequencies. The design concept, circuit geometry, equivalent lumped circuit model, and simulated and measured results are carefully investigated and discussed. Based on the new synthesized microstrip line, a miniaturized quadrature hybrid coupler with harmonic suppressions is designed as a demonstrated example. The signal rejection levels are higher than 20 and 40 dB at the second and third harmonics, respectively. At the mean time, the size reduction percentage is 50%.","PeriodicalId":341557,"journal":{"name":"2010 IEEE MTT-S International Microwave Symposium","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133824704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-23DOI: 10.1109/MWSYM.2010.5518084
H. Park, J. Rieh, M. Kim, J. Hacker
A 300 GHz amplifier is fabricated using indium-phosphide (InP) double-heterojunction bipolar transistor (DHBT) technology. The cascade chain in the amplifier contains six unit cells each containing a pair of common-base DHBTs in differential configuration. A total of three signal lines run through to the unit-cell to obtain the differential-mode amplifier gain and provide proper dc bias. Measured results show the peak gain of 17.3 dB at 290 GHz with 10-dB gain-bandwidth of 20 GHz.
{"title":"300 GHz six-stage differential-mode amplifier","authors":"H. Park, J. Rieh, M. Kim, J. Hacker","doi":"10.1109/MWSYM.2010.5518084","DOIUrl":"https://doi.org/10.1109/MWSYM.2010.5518084","url":null,"abstract":"A 300 GHz amplifier is fabricated using indium-phosphide (InP) double-heterojunction bipolar transistor (DHBT) technology. The cascade chain in the amplifier contains six unit cells each containing a pair of common-base DHBTs in differential configuration. A total of three signal lines run through to the unit-cell to obtain the differential-mode amplifier gain and provide proper dc bias. Measured results show the peak gain of 17.3 dB at 290 GHz with 10-dB gain-bandwidth of 20 GHz.","PeriodicalId":341557,"journal":{"name":"2010 IEEE MTT-S International Microwave Symposium","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115897229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-23DOI: 10.1109/MWSYM.2010.5518217
Yong‐Sub Lee, Mun‐Woo Lee, S. Kam, Y. Jeong
This paper reports a new double Doherty power amplifier (DDPA) with a flat efficiency range, which consists of two-stage amplifiers. When the two-way DPA is used as the main peaking amplifier, the driving peaking cell with class-C bias turns the DPA off before the saturation of the main carrier amplifier. Three efficiency-peaking points are achieved with the additional Doherty operation by the main peaking amplifier after the saturation of the main carrier amplifier. For verifications, the driving and main amplifiers are designed and implemented with 2-W and 10-W GaN HEMTs, respectively, at 2.14 GHz. From the continuous wave (CW) results, three efficiency-peaking points are obtained at approximately 9-, 5-, and 0-dB back-off powers with over 42% drain efficiency. For one-carrier wide-band code division multiple access (WCDMA) signal, the DDPA shows good digital predistortion linearization performance.
本文报道了一种由两级放大器组成的具有平坦效率范围的双Doherty功率放大器(DDPA)。当使用双向DPA作为主峰值放大器时，具有c类偏置的驱动峰值单元在主载波放大器饱和之前关闭DPA。在主载波放大器饱和后，主调峰放大器通过额外的Doherty运算实现了三个效率峰值点。为了验证，驱动放大器和主放大器分别采用2.14 GHz的2 w和10 w GaN hemt设计和实现。从连续波(CW)结果来看，在大约9 db、5 db和0 db的回退功率下获得了三个效率峰值点，漏极效率超过42%。对于单载波宽带码分多址(WCDMA)信号，DDPA具有良好的数字预失真线性化性能。
{"title":"Advanced design of a double Doherty power amplifier with a flat efficiency range","authors":"Yong‐Sub Lee, Mun‐Woo Lee, S. Kam, Y. Jeong","doi":"10.1109/MWSYM.2010.5518217","DOIUrl":"https://doi.org/10.1109/MWSYM.2010.5518217","url":null,"abstract":"This paper reports a new double Doherty power amplifier (DDPA) with a flat efficiency range, which consists of two-stage amplifiers. When the two-way DPA is used as the main peaking amplifier, the driving peaking cell with class-C bias turns the DPA off before the saturation of the main carrier amplifier. Three efficiency-peaking points are achieved with the additional Doherty operation by the main peaking amplifier after the saturation of the main carrier amplifier. For verifications, the driving and main amplifiers are designed and implemented with 2-W and 10-W GaN HEMTs, respectively, at 2.14 GHz. From the continuous wave (CW) results, three efficiency-peaking points are obtained at approximately 9-, 5-, and 0-dB back-off powers with over 42% drain efficiency. For one-carrier wide-band code division multiple access (WCDMA) signal, the DDPA shows good digital predistortion linearization performance.","PeriodicalId":341557,"journal":{"name":"2010 IEEE MTT-S International Microwave Symposium","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124202047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-23DOI: 10.1109/MWSYM.2010.5517848
F. He, K. Wu, Xiaoping Chen, Liang Han, W. Hong
In this paper, a modified magic-T using substrate integrated waveguide (SIW) and slotline is proposed and developed for RF/microwave applications on the basis of the substrate integrated circuits (SICs) concept. The modified planar magic-T consists of an 180° phase-reversal T-junction and an Hplane SIW T-junction. An optimized wideband magic-T structure is demonstrated and fabricated. Measurement of this structure shows very promising results. Also, theoretical analyses are presented and discussed with transmission line models of the modified magic-T. Measured results of the circuit agree well with its simulated ones.
{"title":"A planar magic-T structure using substrate integrated circuits concept","authors":"F. He, K. Wu, Xiaoping Chen, Liang Han, W. Hong","doi":"10.1109/MWSYM.2010.5517848","DOIUrl":"https://doi.org/10.1109/MWSYM.2010.5517848","url":null,"abstract":"In this paper, a modified magic-T using substrate integrated waveguide (SIW) and slotline is proposed and developed for RF/microwave applications on the basis of the substrate integrated circuits (SICs) concept. The modified planar magic-T consists of an 180° phase-reversal T-junction and an Hplane SIW T-junction. An optimized wideband magic-T structure is demonstrated and fabricated. Measurement of this structure shows very promising results. Also, theoretical analyses are presented and discussed with transmission line models of the modified magic-T. Measured results of the circuit agree well with its simulated ones.","PeriodicalId":341557,"journal":{"name":"2010 IEEE MTT-S International Microwave Symposium","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114748615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-23DOI: 10.1109/MWSYM.2010.5517222
A. L. Clarke, Muhammad Akmal, J. Lees, P. Tasker, J. Benedikt
A rigorous, systematic, measurement-founded approach is presented that enables the design of highly efficient power amplifiers. The identified process allows the designer to quickly identify the parameters necessary for completion of a design whilst ascertaining their flexibility and impact on performance degradation. The investigation continues to consider the impact of the higher harmonics and gate bias as design tools on the performance of the design and proposes a strategy that utilizes their positive effect as well as considering the subsequent impact on device scaling. This was carried out on GaAs pHEMT devices from commercial processes that obtained measured peak efficiencies of 90.1% at P1dB in a class-B bias.
{"title":"Investigation and analysis into device optimization for attaining efficiencies in-excess of 90% when accounting for higher harmonics","authors":"A. L. Clarke, Muhammad Akmal, J. Lees, P. Tasker, J. Benedikt","doi":"10.1109/MWSYM.2010.5517222","DOIUrl":"https://doi.org/10.1109/MWSYM.2010.5517222","url":null,"abstract":"A rigorous, systematic, measurement-founded approach is presented that enables the design of highly efficient power amplifiers. The identified process allows the designer to quickly identify the parameters necessary for completion of a design whilst ascertaining their flexibility and impact on performance degradation. The investigation continues to consider the impact of the higher harmonics and gate bias as design tools on the performance of the design and proposes a strategy that utilizes their positive effect as well as considering the subsequent impact on device scaling. This was carried out on GaAs pHEMT devices from commercial processes that obtained measured peak efficiencies of 90.1% at P1dB in a class-B bias.","PeriodicalId":341557,"journal":{"name":"2010 IEEE MTT-S International Microwave Symposium","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114905431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-23DOI: 10.1109/MWSYM.2010.5516224
G. Mouginot, Z. Ouarch, B. Lefebvre, S. Heckmann, J. Lhortolary, D. Baglieri, D. Floriot, M. Camiade, H. Blanck, M. Le Pipec, D. Mesnager, P. Le Helleye
A monolithic three stage HPA has been developed for wide band applications. This MMIC is fabricated on UMS 0.25 µm GaN technology based on SiC substrate. At 18GHz, the MMIC achieved in CW mode 10W of output power with 20dB linear gain and 20% power added efficiency. The HPA provided 6 to 10W output power over 6 to 18GHz with minimum small signal gain of 18dB. These obtained performances are very promising and very close to the simulations; this will allow a very short term further improvement. This demonstration is the first MMIC on the UMS 0.25µm GaN technology.
{"title":"Three stage 6–18 GHz high gain and high power amplifier based on GaN technology","authors":"G. Mouginot, Z. Ouarch, B. Lefebvre, S. Heckmann, J. Lhortolary, D. Baglieri, D. Floriot, M. Camiade, H. Blanck, M. Le Pipec, D. Mesnager, P. Le Helleye","doi":"10.1109/MWSYM.2010.5516224","DOIUrl":"https://doi.org/10.1109/MWSYM.2010.5516224","url":null,"abstract":"A monolithic three stage HPA has been developed for wide band applications. This MMIC is fabricated on UMS 0.25 µm GaN technology based on SiC substrate. At 18GHz, the MMIC achieved in CW mode 10W of output power with 20dB linear gain and 20% power added efficiency. The HPA provided 6 to 10W output power over 6 to 18GHz with minimum small signal gain of 18dB. These obtained performances are very promising and very close to the simulations; this will allow a very short term further improvement. This demonstration is the first MMIC on the UMS 0.25µm GaN technology.","PeriodicalId":341557,"journal":{"name":"2010 IEEE MTT-S International Microwave Symposium","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115031750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-23DOI: 10.1109/MWSYM.2010.5516851
Hua Wang, Shohei Kosai, Constantine Sideris, A. Hajimiri
This paper presents a scalable and ultrasensitive frequency-shift magnetic biosensing array scheme. The theoretical limit of the sensor noise floor is shown to be dominated by the phase noise of the sensing oscillators. To increase the sensitivity, a noise suppression technique, Correlated Double Counting (CDC), is proposed with no power overhead. As an implementation example, a 64-cell sensor array is designed in a standard 65nm CMOS process. The CDC scheme achieves an additional 6dB noise suppression. The magnetic sensing capability of the presented sensor is verified by detecting micron size magnetic particles with an SNR of 14.6dB for a single bead and an effective dynamic range of at least 74.5dB.
{"title":"An ultrasensitive CMOS magnetic biosensor array with correlated double counting noise suppression","authors":"Hua Wang, Shohei Kosai, Constantine Sideris, A. Hajimiri","doi":"10.1109/MWSYM.2010.5516851","DOIUrl":"https://doi.org/10.1109/MWSYM.2010.5516851","url":null,"abstract":"This paper presents a scalable and ultrasensitive frequency-shift magnetic biosensing array scheme. The theoretical limit of the sensor noise floor is shown to be dominated by the phase noise of the sensing oscillators. To increase the sensitivity, a noise suppression technique, Correlated Double Counting (CDC), is proposed with no power overhead. As an implementation example, a 64-cell sensor array is designed in a standard 65nm CMOS process. The CDC scheme achieves an additional 6dB noise suppression. The magnetic sensing capability of the presented sensor is verified by detecting micron size magnetic particles with an SNR of 14.6dB for a single bead and an effective dynamic range of at least 74.5dB.","PeriodicalId":341557,"journal":{"name":"2010 IEEE MTT-S International Microwave Symposium","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116038964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-23DOI: 10.1109/MWSYM.2010.5517180
T. Bolz, A. Beyer
The aim of this contribution is the derivation of a simple mathematical model to describe the electromagnetic interaction between the microstrip structure and the resonant modes of the metal shielding, in which the structure mentioned is built in either for avoiding the radiation or for suppressing electric coupling between adjacent circuit. By the help of this model based on the electromagnetic field equations equivalent electric circuits are extracted to consider the interaction between electric and magnetic surface currents and cavity modes in a commercially available circuit simulator. Several examples and their results show the applicability of the technique proposed.
{"title":"Analytical approaches to calculating the parasitic coupling between packages and microwave circuits","authors":"T. Bolz, A. Beyer","doi":"10.1109/MWSYM.2010.5517180","DOIUrl":"https://doi.org/10.1109/MWSYM.2010.5517180","url":null,"abstract":"The aim of this contribution is the derivation of a simple mathematical model to describe the electromagnetic interaction between the microstrip structure and the resonant modes of the metal shielding, in which the structure mentioned is built in either for avoiding the radiation or for suppressing electric coupling between adjacent circuit. By the help of this model based on the electromagnetic field equations equivalent electric circuits are extracted to consider the interaction between electric and magnetic surface currents and cavity modes in a commercially available circuit simulator. Several examples and their results show the applicability of the technique proposed.","PeriodicalId":341557,"journal":{"name":"2010 IEEE MTT-S International Microwave Symposium","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123547908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-23DOI: 10.1109/MWSYM.2010.5516843
Jianjun Xu, J. Horn, M. Iwamoto, D. Root
A non-quasi static large-signal FET model is presented incorporating self-heating and other multiple timescale dynamics necessary to describe the large-signal behavior of III–V FET technologies including GaAs and GaN. The model is unique in that it incorporates electro-thermal and trapping dynamics (gate lag and drain lag) into both the model current source and the model nonlinear output charge source, for the first time. The model is developed from large-signal waveform data obtained from a modern nonlinear vector network analyzer (NVNA), working in concert with an output tuner and bias supplies. The dependences of Id and Qd on temperature, two trap states, and instantaneous terminal voltages are identified directly from NVNA data. Artificial neural networks are used to represent these constitutive relations for a compiled implementation into a commercial nonlinear circuit simulator (Agilent ADS). Detailed comparisons to large-signal measured data are presented.
{"title":"Large-signal FET model with multiple time scale dynamics from nonlinear vector network analyzer data","authors":"Jianjun Xu, J. Horn, M. Iwamoto, D. Root","doi":"10.1109/MWSYM.2010.5516843","DOIUrl":"https://doi.org/10.1109/MWSYM.2010.5516843","url":null,"abstract":"A non-quasi static large-signal FET model is presented incorporating self-heating and other multiple timescale dynamics necessary to describe the large-signal behavior of III–V FET technologies including GaAs and GaN. The model is unique in that it incorporates electro-thermal and trapping dynamics (gate lag and drain lag) into both the model current source and the model nonlinear output charge source, for the first time. The model is developed from large-signal waveform data obtained from a modern nonlinear vector network analyzer (NVNA), working in concert with an output tuner and bias supplies. The dependences of Id and Qd on temperature, two trap states, and instantaneous terminal voltages are identified directly from NVNA data. Artificial neural networks are used to represent these constitutive relations for a compiled implementation into a commercial nonlinear circuit simulator (Agilent ADS). Detailed comparisons to large-signal measured data are presented.","PeriodicalId":341557,"journal":{"name":"2010 IEEE MTT-S International Microwave Symposium","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125702568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-23DOI: 10.1109/MWSYM.2010.5518218
K. Yau, I. Sarkas, A. Tomkins, P. Chevalier, S. Voinigescu
This paper compares for the first time open-short, split-through, and TRL de-embedding techniques for on-wafer characterization of silicon active and passive devices in the DC to 170 GHz range. It is demonstrated using transformers, capacitors, 65 nm MOSFETs and SiGe HBTs that, if the open and short dummies are designed to remain lumped through 170GHz, there is almost no difference between the three de-embedding techniques. For transistor test structures with series ground inductance, a new TRL + short de-embedding method is proposed.
{"title":"On-wafer S-parameter de-embedding of silicon active and passive devices up to 170 GHz","authors":"K. Yau, I. Sarkas, A. Tomkins, P. Chevalier, S. Voinigescu","doi":"10.1109/MWSYM.2010.5518218","DOIUrl":"https://doi.org/10.1109/MWSYM.2010.5518218","url":null,"abstract":"This paper compares for the first time open-short, split-through, and TRL de-embedding techniques for on-wafer characterization of silicon active and passive devices in the DC to 170 GHz range. It is demonstrated using transformers, capacitors, 65 nm MOSFETs and SiGe HBTs that, if the open and short dummies are designed to remain lumped through 170GHz, there is almost no difference between the three de-embedding techniques. For transistor test structures with series ground inductance, a new TRL + short de-embedding method is proposed.","PeriodicalId":341557,"journal":{"name":"2010 IEEE MTT-S International Microwave Symposium","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125797222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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