Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367594
P. Thompson, M. Begay, S. Lindsey, D. Vanoverloop, B. Vasquez, S. Walker, B. Williams
A high-yield die supply has been identified as a key requirement for the viability of commercial multichip modules (MCM). The result of die or wafer level test and burn-in, (beyond the level of historical wafer probe), to provide dice with performance and reliability levels equivalent to single chip packaged dice is commonly called known good die (KGD). There are many proposed methods to obtain KGD, at varying levels of maturity, and with varying levels of cost, complexity, and potential impact on device performance and reliability. In this paper, we describe the mechanical and electrical evaluation of a temporary die-level burn-in carrier designed for use in providing known good dice. Three device types are used in this evaluation to explore the limitations of the carrier system under evaluation: a 1 M DRAM, a 128 k/spl times/8 SRAM, and a 56 k gate ASIC. Die size, and bond pad count, size and pitch all impact the applicability of the carrier system under evaluation. Mechanical evaluations performed to date include measurements of critical carrier features such as bump height, die alignment structure placement and bond pad damage caused by the carrier contacts. Electrical evaluations include continuity and electrical test performance at multiple temperatures.<>
高产量的模具供应已被确定为商业多芯片模块(MCM)可行性的关键要求。通过晶片级或晶片级测试和老化的结果，(超越历史晶片探测的水平)，提供与单芯片封装的晶片性能和可靠性水平相当的晶片通常被称为已知好晶片(KGD)。有许多获得KGD的建议方法，它们的成熟度不同，成本、复杂性和对设备性能和可靠性的潜在影响也不同。在本文中，我们描述了一个临时模级烧蚀载体设计用于提供已知的好骰子的机械和电气评价。在本次评估中使用了三种器件类型来探索被评估载波系统的局限性:1 M DRAM, 128 k/spl times/8 SRAM和56 k栅极ASIC。模具尺寸、粘结垫数量、尺寸和间距都会影响所评估的载体系统的适用性。迄今为止进行的机械评估包括对关键载体特征的测量，如凹凸高度、模具对准结构位置和由载体接触引起的键合垫损坏。电气评估包括在多个温度下的连续性和电气测试性能。
{"title":"Mechanical and electrical evaluation of a bumped-substrate die-level burn-in carrier","authors":"P. Thompson, M. Begay, S. Lindsey, D. Vanoverloop, B. Vasquez, S. Walker, B. Williams","doi":"10.1109/ECTC.1994.367594","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367594","url":null,"abstract":"A high-yield die supply has been identified as a key requirement for the viability of commercial multichip modules (MCM). The result of die or wafer level test and burn-in, (beyond the level of historical wafer probe), to provide dice with performance and reliability levels equivalent to single chip packaged dice is commonly called known good die (KGD). There are many proposed methods to obtain KGD, at varying levels of maturity, and with varying levels of cost, complexity, and potential impact on device performance and reliability. In this paper, we describe the mechanical and electrical evaluation of a temporary die-level burn-in carrier designed for use in providing known good dice. Three device types are used in this evaluation to explore the limitations of the carrier system under evaluation: a 1 M DRAM, a 128 k/spl times/8 SRAM, and a 56 k gate ASIC. Die size, and bond pad count, size and pitch all impact the applicability of the carrier system under evaluation. Mechanical evaluations performed to date include measurements of critical carrier features such as bump height, die alignment structure placement and bond pad damage caused by the carrier contacts. Electrical evaluations include continuity and electrical test performance at multiple temperatures.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125560093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367638
A. Okuno, K. Nagai, N. Fujita, Y. Tsukasaki, N. Oyama, K. Nakahira, T. Hashimoto
MCM/sup L/ can expect to be the main current of semiconductor packaging technology in near future. BGA, PLCC and PGA packaging methods will expect much of this application. But the most pressing problem is warp after the packaging process. The warp after packaging needs to be below 150 /spl mu/m at BGA and 100 /spl mu/m at PLCC. We have already developed the Printing Encapsulation Systems (PES). PES is able to make low cost and mass produced semiconductor packaging. This paper describes the use of PES to make MCM/sup L/ semiconductor packaging. We have developed a low warp packaging epoxy resin using elastomer modified epoxy resin to fit BGA, PLCC and PGA. We verified the low stress epoxy resin using dynamic mechanical properties and internal stress measurements. We packaged BGA, PLCC and BGA with this low stress epoxy resin using PES, and measured the warp of each packaging. We obtained good results for the warp, demonstrating that using this low stress epoxy resin and PES, low cost and high reliability packaging of BGA, PLCC and PGA could be achieved.<>
{"title":"High reliability MCM packaging using low stress liquid type epoxy resin by printing encapsulation systems (PES)","authors":"A. Okuno, K. Nagai, N. Fujita, Y. Tsukasaki, N. Oyama, K. Nakahira, T. Hashimoto","doi":"10.1109/ECTC.1994.367638","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367638","url":null,"abstract":"MCM/sup L/ can expect to be the main current of semiconductor packaging technology in near future. BGA, PLCC and PGA packaging methods will expect much of this application. But the most pressing problem is warp after the packaging process. The warp after packaging needs to be below 150 /spl mu/m at BGA and 100 /spl mu/m at PLCC. We have already developed the Printing Encapsulation Systems (PES). PES is able to make low cost and mass produced semiconductor packaging. This paper describes the use of PES to make MCM/sup L/ semiconductor packaging. We have developed a low warp packaging epoxy resin using elastomer modified epoxy resin to fit BGA, PLCC and PGA. We verified the low stress epoxy resin using dynamic mechanical properties and internal stress measurements. We packaged BGA, PLCC and BGA with this low stress epoxy resin using PES, and measured the warp of each packaging. We obtained good results for the warp, demonstrating that using this low stress epoxy resin and PES, low cost and high reliability packaging of BGA, PLCC and PGA could be achieved.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128372367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367599
R. E. Canright
The principle feature of robust design for quality is parameter design: selecting the design parameters to minimize quality loss. The tolerance in interconnection characteristic impedance (Zo) can impact the cost of a printed circuit board (PCB), multichip module (MCM), or hybrid if the tolerance is too small and the cost of the interconnect has to absorb rejected parts. This paper extends a theory of controlled impedance design that is compatible with the principles of robust design for quality. Practical applications and broad implications of this theory are demonstrated. The results are pertinent to both designers and fabricators of interconnections for high speed digital systems. Designers of digital output drivers will see the effect of driver impedance upon transmission line impedance.<>
{"title":"The impact of driver impedance upon transmission line impedance","authors":"R. E. Canright","doi":"10.1109/ECTC.1994.367599","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367599","url":null,"abstract":"The principle feature of robust design for quality is parameter design: selecting the design parameters to minimize quality loss. The tolerance in interconnection characteristic impedance (Zo) can impact the cost of a printed circuit board (PCB), multichip module (MCM), or hybrid if the tolerance is too small and the cost of the interconnect has to absorb rejected parts. This paper extends a theory of controlled impedance design that is compatible with the principles of robust design for quality. Practical applications and broad implications of this theory are demonstrated. The results are pertinent to both designers and fabricators of interconnections for high speed digital systems. Designers of digital output drivers will see the effect of driver impedance upon transmission line impedance.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128486773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367557
T. Lee, B. Chambers, M. Mahalingam
Application of a Computational Fluids Dynamics (CFD) tool to the thermal modeling of free convection cooled handheld/portable products and component level products is assessed. The results of two case studies are reviewed. The first case focuses on a sealed, system level enclosure typical of portable consumer products; while the second case looks at a component level analysis of a sealed multichip module (MCM) package possessing an internal cavity. Temperatures predicted by the simulations are compared to available experimental data as a means of assessing the software's ability to adequately solve the coupled fluid dynamics/heat transfer problem. All simulation results were within 10% of experimental results for these two cases, indicating the software is readily capable of providing good thermal performance predictions.<>
{"title":"Application of CFD Technology to electronic thermal management","authors":"T. Lee, B. Chambers, M. Mahalingam","doi":"10.1109/ECTC.1994.367557","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367557","url":null,"abstract":"Application of a Computational Fluids Dynamics (CFD) tool to the thermal modeling of free convection cooled handheld/portable products and component level products is assessed. The results of two case studies are reviewed. The first case focuses on a sealed, system level enclosure typical of portable consumer products; while the second case looks at a component level analysis of a sealed multichip module (MCM) package possessing an internal cavity. Temperatures predicted by the simulations are compared to available experimental data as a means of assessing the software's ability to adequately solve the coupled fluid dynamics/heat transfer problem. All simulation results were within 10% of experimental results for these two cases, indicating the software is readily capable of providing good thermal performance predictions.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126710808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367578
R. Fillion, R. Wojnarowski, T. B. Gorcyzca, E. Wildi, H. Cole
Non-military/non-computer electronics industry segments such as PCs, workstations, portable electronics, automotive, medical, automated test equipment and high end consumer, are evolving to higher complexity and higher performance circuits and components. At the same time, many of these industry segments are being driven to shrink size, weigh and power dissipation. Standard low cost packaging approaches such as thru-hole PCB and chip and wire hybrids, can no longer efficiently interconnect these more complex circuits. These industry segments are being forced to turn to new higher performance packaging approaches such as SMT, MCM and COB. This paper describes the development of an innovative embedded chip MCM technology that eliminates high cost structures, materials and processes in current thin film MCM technologies. A plastic encapsulated multichip technology has been developed in which an epoxy encapsulant is molded around bare die to form the MCM substrate. This new MCM process readily scales-up to high volume production and is inherently high yielding, while maintaining all of the performance advantages of the GE developed overlay HDI process. This paper describes the thermal, mechanical and chemical stability issues that drove this development, the process used to fabricate the modules and the cost and yield advantages associated with this structure.<>
{"title":"Development of a plastic encapsulated multichip technology for high volume, low cost commercial electronics","authors":"R. Fillion, R. Wojnarowski, T. B. Gorcyzca, E. Wildi, H. Cole","doi":"10.1109/ECTC.1994.367578","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367578","url":null,"abstract":"Non-military/non-computer electronics industry segments such as PCs, workstations, portable electronics, automotive, medical, automated test equipment and high end consumer, are evolving to higher complexity and higher performance circuits and components. At the same time, many of these industry segments are being driven to shrink size, weigh and power dissipation. Standard low cost packaging approaches such as thru-hole PCB and chip and wire hybrids, can no longer efficiently interconnect these more complex circuits. These industry segments are being forced to turn to new higher performance packaging approaches such as SMT, MCM and COB. This paper describes the development of an innovative embedded chip MCM technology that eliminates high cost structures, materials and processes in current thin film MCM technologies. A plastic encapsulated multichip technology has been developed in which an epoxy encapsulant is molded around bare die to form the MCM substrate. This new MCM process readily scales-up to high volume production and is inherently high yielding, while maintaining all of the performance advantages of the GE developed overlay HDI process. This paper describes the thermal, mechanical and chemical stability issues that drove this development, the process used to fabricate the modules and the cost and yield advantages associated with this structure.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126975865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367529
F. Yeung, Y. Chan
In this paper, the electrical behavior of multilayer ceramic capacitors (MLCs) in strict dynamic high temperature-humidity-DC bias voltage (THB) conditions were studied and the failure model of MLCs under such conditions was proposed. It was found, if the environmental temperature and humidity rose too fast and the temperature of a MLC was lower than the dew point temperature of surrounding moist air, dewdrops would condense on the MLC surface. When DC voltage was applied, metallic ions from end terminations of the MLC would migrate along the condensed water film on the MLC surface and made a permanent short-circuiting path between two terminations. Silver and tin migrations were found by EDX detection in our experiment. It was also found that the applied DC electrical loading level had a strong influence on the fail rate of MLCs. The recovery rate of MLCs after the dynamic THB process decreased with applied DC voltage increasing. To reduce the effect of dewdrops of moist air on the reliability of MLCs, the method and speed of temperature and humidity rise are discussed.<>
{"title":"Electrical failure of multilayer ceramic capacitors caused by high temperature and high humidity environment","authors":"F. Yeung, Y. Chan","doi":"10.1109/ECTC.1994.367529","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367529","url":null,"abstract":"In this paper, the electrical behavior of multilayer ceramic capacitors (MLCs) in strict dynamic high temperature-humidity-DC bias voltage (THB) conditions were studied and the failure model of MLCs under such conditions was proposed. It was found, if the environmental temperature and humidity rose too fast and the temperature of a MLC was lower than the dew point temperature of surrounding moist air, dewdrops would condense on the MLC surface. When DC voltage was applied, metallic ions from end terminations of the MLC would migrate along the condensed water film on the MLC surface and made a permanent short-circuiting path between two terminations. Silver and tin migrations were found by EDX detection in our experiment. It was also found that the applied DC electrical loading level had a strong influence on the fail rate of MLCs. The recovery rate of MLCs after the dynamic THB process decreased with applied DC voltage increasing. To reduce the effect of dewdrops of moist air on the reliability of MLCs, the method and speed of temperature and humidity rise are discussed.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127470149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367602
Y. Ma
A geometrically-based user interface has been developed as a preprocessor for a numerical model of convective heat transfer from printed circuit boards (PCB). The physical problem is specified in a natural way as a collection of the control parameters and the objects that exist within the computational domain. Complicated configurations of discrete electronic components on a circuit board is represented by several simple physical objects with specified boundary conditions and heat-generating status. No reference to node or element number is needed and the input order of the objects can be arbitrary. The preprocessor program automatically sorts the coordinates of each object, subdivides the computational domain, eliminates the redundant coordinates and generates an object grid system that is consistent with the physical configurations of PCBs. This three dimensional geometrically-based object grid system is integrated to the main analysis codes for solving flow and temperature distribution. The geometrically-based model specification provides the hooks for a graphical user interface (GUI) which could be added later.<>
{"title":"An interface for numerical analysis of convective heat transfer from printed circuit boards","authors":"Y. Ma","doi":"10.1109/ECTC.1994.367602","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367602","url":null,"abstract":"A geometrically-based user interface has been developed as a preprocessor for a numerical model of convective heat transfer from printed circuit boards (PCB). The physical problem is specified in a natural way as a collection of the control parameters and the objects that exist within the computational domain. Complicated configurations of discrete electronic components on a circuit board is represented by several simple physical objects with specified boundary conditions and heat-generating status. No reference to node or element number is needed and the input order of the objects can be arbitrary. The preprocessor program automatically sorts the coordinates of each object, subdivides the computational domain, eliminates the redundant coordinates and generates an object grid system that is consistent with the physical configurations of PCBs. This three dimensional geometrically-based object grid system is integrated to the main analysis codes for solving flow and temperature distribution. The geometrically-based model specification provides the hooks for a graphical user interface (GUI) which could be added later.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125177684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367566
A. Yoshikawa, H. Nakanishi, K. Itoh, T. Yamazaki, T. Komino, T. Musha
The LDH unit with the size of 4.8/spl times/8.2/spl times/4.3 mm for a thin optical pickup head of a CD player has been successfully developed. The technology to make the LDH unit thin and small is based upon (1) the most efficient optical combination of the low operation current laser diode with the 45/spl deg/ built-in micro-mirror which is formed on the Si photodetector substrate, (2) the thin plastic-molded flat package with good thermal dissipation, and (3) the plastic-molded holographic optical element (HOE) as a cap. The pick-up head using the LDH unit has shown good optical performance sufficient for the application to CD players.<>
{"title":"LDH (laser/detector/hologram) unit for thin optical pick-up head of CD player","authors":"A. Yoshikawa, H. Nakanishi, K. Itoh, T. Yamazaki, T. Komino, T. Musha","doi":"10.1109/ECTC.1994.367566","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367566","url":null,"abstract":"The LDH unit with the size of 4.8/spl times/8.2/spl times/4.3 mm for a thin optical pickup head of a CD player has been successfully developed. The technology to make the LDH unit thin and small is based upon (1) the most efficient optical combination of the low operation current laser diode with the 45/spl deg/ built-in micro-mirror which is formed on the Si photodetector substrate, (2) the thin plastic-molded flat package with good thermal dissipation, and (3) the plastic-molded holographic optical element (HOE) as a cap. The pick-up head using the LDH unit has shown good optical performance sufficient for the application to CD players.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128196368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367532
A. Deutsch, G. Arjavalingam, C. Surovic, A. P. Lanzetta, K. Fogel, F. Doany, M. Ritter
The electrical performance of three types of cables, namely coaxial, shielded ribbon and flexible-film is characterized for interconnection applications inside high-speed digital systems. Measurements are made of the cable attenuation signal propagation integrity, bit-error rate, connector discontinuities and crosstalk. The electrical parameters obtained experimentally are used in simulations to predict the bandwidth and range of useful lengths for these cables. The paper highlights the performance-limiting factors such as connector and via discontinuities, and printed-circuit-board wiring losses and the practical density and extendibility limitations are discussed.<>
{"title":"Intra-system interconnects for digital communications","authors":"A. Deutsch, G. Arjavalingam, C. Surovic, A. P. Lanzetta, K. Fogel, F. Doany, M. Ritter","doi":"10.1109/ECTC.1994.367532","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367532","url":null,"abstract":"The electrical performance of three types of cables, namely coaxial, shielded ribbon and flexible-film is characterized for interconnection applications inside high-speed digital systems. Measurements are made of the cable attenuation signal propagation integrity, bit-error rate, connector discontinuities and crosstalk. The electrical parameters obtained experimentally are used in simulations to predict the bandwidth and range of useful lengths for these cables. The paper highlights the performance-limiting factors such as connector and via discontinuities, and printed-circuit-board wiring losses and the practical density and extendibility limitations are discussed.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130844206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367513
A. Vaidyanath, B. Thoroddsen, J. Prince, A. Cangellaris
The paper presents an aspect of Simultaneous Switching Noise (SSN) for CMOS drivers in packages with power distribution planes. The analysis takes into account the interactions between power distribution planes and signal traces. Coupling between these have a significant effect on the noise and must be taken into account. A model for the interaction between the signal conductors and the current paths in the power distribution planes is presented. The presence of the signal conductors is seen to have a significant impact on the SSN. The magnitude of the noise is strongly dependent on the relative positions of the signal conductors and the power and ground plane pin connections. Power and ground planes sufficiently close to each other also have significant mutual inductive coupling. This coupling will cause noise to be observed in both distribution planes, even though switching current flows in only one plane. This effect is explained.<>
{"title":"Simultaneous switching noise: influence of plane-plane and plane-signal trace coupling","authors":"A. Vaidyanath, B. Thoroddsen, J. Prince, A. Cangellaris","doi":"10.1109/ECTC.1994.367513","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367513","url":null,"abstract":"The paper presents an aspect of Simultaneous Switching Noise (SSN) for CMOS drivers in packages with power distribution planes. The analysis takes into account the interactions between power distribution planes and signal traces. Coupling between these have a significant effect on the noise and must be taken into account. A model for the interaction between the signal conductors and the current paths in the power distribution planes is presented. The presence of the signal conductors is seen to have a significant impact on the SSN. The magnitude of the noise is strongly dependent on the relative positions of the signal conductors and the power and ground plane pin connections. Power and ground planes sufficiently close to each other also have significant mutual inductive coupling. This coupling will cause noise to be observed in both distribution planes, even though switching current flows in only one plane. This effect is explained.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131165847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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