Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367562
H. Akahoshi, M. Kawamoto, T. Itabashi, O. Miura, A. Takahashi, S. Kobayashi, M. Miyazaki, T. Mutho, M. Wajima, T. Ishimaru
Two types of additive processes for fine circuit pattern manufacturing technology using electroless copper plating have been developed. The processes offer high dimensional accuracy. Technical aspects of the additive processes, materials for the fabrication of additive circuits, and the performance of these circuits are reported here.<>
{"title":"Fine line circuit manufacturing technology with electroless copper plating","authors":"H. Akahoshi, M. Kawamoto, T. Itabashi, O. Miura, A. Takahashi, S. Kobayashi, M. Miyazaki, T. Mutho, M. Wajima, T. Ishimaru","doi":"10.1109/ECTC.1994.367562","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367562","url":null,"abstract":"Two types of additive processes for fine circuit pattern manufacturing technology using electroless copper plating have been developed. The processes offer high dimensional accuracy. Technical aspects of the additive processes, materials for the fabrication of additive circuits, and the performance of these circuits are reported here.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123089359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367542
D. E. Pope, H. Do
The unenhanced thermal performance of Tape carrier Package (TCP) packages on 8 layer boards with internal planes is 19 C/W. Simple PCB enhancements such as the addition of thermal vias, alone or with the use of low profile heatsinks, brings the thermal performance in line with requirements for mobile computing platforms which do not have forced convection cooling options available. With forced convection cooling, devices with a power dissipation requirement of up to 4.7 C/W can be packaged in TCP format.<>
{"title":"Thermal characterization of a tape carrier package","authors":"D. E. Pope, H. Do","doi":"10.1109/ECTC.1994.367542","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367542","url":null,"abstract":"The unenhanced thermal performance of Tape carrier Package (TCP) packages on 8 layer boards with internal planes is 19 C/W. Simple PCB enhancements such as the addition of thermal vias, alone or with the use of low profile heatsinks, brings the thermal performance in line with requirements for mobile computing platforms which do not have forced convection cooling options available. With forced convection cooling, devices with a power dissipation requirement of up to 4.7 C/W can be packaged in TCP format.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126044739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367561
A. Strandjord, R. H. Heistand, J. Bremmer, P. Garrou, T. Tessier
As Multichip Module (MCM) technology has evolved from research to commercial production, cost has become the important issue for implementation. Manufacturing schemes are incorporating those processes and materials which take advantage of the most cost effective technologies to meet the specific performance requirements for a given application. The work described in this paper demonstrates how laminate based MCM technology (MCM-L) and deposited dielectric technology (MCM-D) can be combined to form a low cost solution for systems requiring high density interconnections. The use of laminate board technology to fabricate the relatively low density interconnect portion of the multilayer structure, allows one to take advantage of the well established and highly cost competitive printed wiring board (PWB) industry. Deposited dielectric technology takes advantage of the high density capabilities, normally associated with MCM-D packaging, to increase performance. Benzocyclobutene (BCB) is a well suited dielectric material for a laminate/deposited dielectric application (MCM-LD) since it can be cured at relatively low temperatures (220-275/spl deg/C). Additionally, the use of BCB as the interlayer dielectric provides a stable copper/BCB interface, excellent planarization over rough topographies, and exhibits very low moisture absorption. Several low cost processing techniques were demonstrated as part of this MCM-LD program. These include an inherently photosensitive BCB formulation as the thin film dielectrics, meniscus coating as the large area deposition process for the photosensitive-BCB, and an in-line belt furnace for Rapid Thermal Curing (RTC). A two layer module was fabricated to demonstrate the feasibility of this MCM-LD process flow. This paper describes the processing issues and techniques associated with such a hybridized interconnection technology.<>
{"title":"A photosensitive-BCB on laminate technology (MCM-LD)","authors":"A. Strandjord, R. H. Heistand, J. Bremmer, P. Garrou, T. Tessier","doi":"10.1109/ECTC.1994.367561","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367561","url":null,"abstract":"As Multichip Module (MCM) technology has evolved from research to commercial production, cost has become the important issue for implementation. Manufacturing schemes are incorporating those processes and materials which take advantage of the most cost effective technologies to meet the specific performance requirements for a given application. The work described in this paper demonstrates how laminate based MCM technology (MCM-L) and deposited dielectric technology (MCM-D) can be combined to form a low cost solution for systems requiring high density interconnections. The use of laminate board technology to fabricate the relatively low density interconnect portion of the multilayer structure, allows one to take advantage of the well established and highly cost competitive printed wiring board (PWB) industry. Deposited dielectric technology takes advantage of the high density capabilities, normally associated with MCM-D packaging, to increase performance. Benzocyclobutene (BCB) is a well suited dielectric material for a laminate/deposited dielectric application (MCM-LD) since it can be cured at relatively low temperatures (220-275/spl deg/C). Additionally, the use of BCB as the interlayer dielectric provides a stable copper/BCB interface, excellent planarization over rough topographies, and exhibits very low moisture absorption. Several low cost processing techniques were demonstrated as part of this MCM-LD program. These include an inherently photosensitive BCB formulation as the thin film dielectrics, meniscus coating as the large area deposition process for the photosensitive-BCB, and an in-line belt furnace for Rapid Thermal Curing (RTC). A two layer module was fabricated to demonstrate the feasibility of this MCM-LD process flow. This paper describes the processing issues and techniques associated with such a hybridized interconnection technology.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114064650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367584
Oh-Gone Chun, S. Ahn, Myung-Yung Jeong, T. Choy, K. Kang, B. Park, Jae-Joo Kim
Analysis of data from an accelerated life test employs a model. Such a statistical model for an accelerated life test consists of a life distribution that represents the scatter in product life and a relationship between life and stress. In this study, the Coffin-Manson relationship is used to model fatigue failure of metals subject to thermal cycling. Generally there are two statistical methods for estimating reliability of objects (life distribution). One is a parametric approach and the other is a nonparametric one. The parametric method assumes that the underlying distribution function belongs to a fixed distribution family indexed by a finite number of parameters. The unknown parameters are then estimated from the data. On the other hand, the nonparametric method does not specify a particular family of distributions. The major difficulty of the parametric approach arises at the stage of model specification. Correct specification of the underlying model is crucial for successful application of the parametric approach. Incorrect specification yields severe model bias and this cannot be compensated in any degree by accurate parameter estimation. In this paper, we provide a nonparametric method to estimate the life distribution under normal usage from accelerated life test data.<>
{"title":"Nonparametric estimation of reliability function using the kernel density estimation method","authors":"Oh-Gone Chun, S. Ahn, Myung-Yung Jeong, T. Choy, K. Kang, B. Park, Jae-Joo Kim","doi":"10.1109/ECTC.1994.367584","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367584","url":null,"abstract":"Analysis of data from an accelerated life test employs a model. Such a statistical model for an accelerated life test consists of a life distribution that represents the scatter in product life and a relationship between life and stress. In this study, the Coffin-Manson relationship is used to model fatigue failure of metals subject to thermal cycling. Generally there are two statistical methods for estimating reliability of objects (life distribution). One is a parametric approach and the other is a nonparametric one. The parametric method assumes that the underlying distribution function belongs to a fixed distribution family indexed by a finite number of parameters. The unknown parameters are then estimated from the data. On the other hand, the nonparametric method does not specify a particular family of distributions. The major difficulty of the parametric approach arises at the stage of model specification. Correct specification of the underlying model is crucial for successful application of the parametric approach. Incorrect specification yields severe model bias and this cannot be compensated in any degree by accurate parameter estimation. In this paper, we provide a nonparametric method to estimate the life distribution under normal usage from accelerated life test data.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128039132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367657
G. Kromann, D. Gerke, W. Huang
The application of a controlled-collapse-chip-connection, ceramic-ball-grid-array (C4/CBGA) module for a RISC microprocessor is presented. The zero to second-level interconnection technologies and the various design considerations, from the on-chip redistribution metal to the single-chip module printed-circuit-board connection, are analysed. In addition to an overview of the interconnect technology, we discuss the: 1) electrical modeling and characterization, 2) board design and routability, 3) thermal management, and 4) C4 and ball-grid-array interconnection reliability.<>
{"title":"A hi-density C4/CBGA interconnect technology for a CMOS microprocessor","authors":"G. Kromann, D. Gerke, W. Huang","doi":"10.1109/ECTC.1994.367657","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367657","url":null,"abstract":"The application of a controlled-collapse-chip-connection, ceramic-ball-grid-array (C4/CBGA) module for a RISC microprocessor is presented. The zero to second-level interconnection technologies and the various design considerations, from the on-chip redistribution metal to the single-chip module printed-circuit-board connection, are analysed. In addition to an overview of the interconnect technology, we discuss the: 1) electrical modeling and characterization, 2) board design and routability, 3) thermal management, and 4) C4 and ball-grid-array interconnection reliability.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131419764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367589
C. Bargeron, T. E. Phillips, R. Benson
The surface conductance of adsorbed water, carbon dioxide, and ammonia has been measured as a function of temperature using a triple-track test substrate. The individual pure gases were studied along with their mixtures. Adsorbed carbon dioxide or ammonia was found to have a negligible surface conductance, while adsorbed water exhibited an increase in conductance beginning at -25/spl deg/C. Mixtures of carbon dioxide and water exhibited essentially the same conductance as water by itself, while mixtures of ammonia and water exhibited a conductance 10/sup 4/ times larger than water between -40/spl deg/C and 0/spl deg/C. Mixtures of all three gases resulted in a relatively low conductance at lower temperatures (-100/spl deg/C to -50/spl deg/C). Corresponding pressure measurements indicated that vaporization was greatly suppressed in some cases, suggesting strong interaction between the adsorbed species.<>
{"title":"Surface conductance measurements of adsorbed gases","authors":"C. Bargeron, T. E. Phillips, R. Benson","doi":"10.1109/ECTC.1994.367589","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367589","url":null,"abstract":"The surface conductance of adsorbed water, carbon dioxide, and ammonia has been measured as a function of temperature using a triple-track test substrate. The individual pure gases were studied along with their mixtures. Adsorbed carbon dioxide or ammonia was found to have a negligible surface conductance, while adsorbed water exhibited an increase in conductance beginning at -25/spl deg/C. Mixtures of carbon dioxide and water exhibited essentially the same conductance as water by itself, while mixtures of ammonia and water exhibited a conductance 10/sup 4/ times larger than water between -40/spl deg/C and 0/spl deg/C. Mixtures of all three gases resulted in a relatively low conductance at lower temperatures (-100/spl deg/C to -50/spl deg/C). Corresponding pressure measurements indicated that vaporization was greatly suppressed in some cases, suggesting strong interaction between the adsorbed species.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131473546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367598
F.J. Cericola, B. K. Bhattacharyya
In this paper, a theoretical method is described for the optimization of a CMOS driven, center tap terminated network. This method is verified by circuit simulations. In the simulations, we have assumed a 70 ohm characteristic impedance of the board interconnects and at the same time, n number of various loads connected at different points on that line. Each of these loads has some stub length that can vary from 1.0 inch to 1.5 inch depending on the packaging technology. The above example is a shared bus situation. This method will also work on other topologies as long as the effective characteristic impedance of that topology is less than Zmin, where Zmin is the minimum characteristic impedance that the CMOS driver can support for a given noise criteria.<>
{"title":"A method for the optimization of a CMOS driven, center tap terminated (CTT) network in a shared bus design","authors":"F.J. Cericola, B. K. Bhattacharyya","doi":"10.1109/ECTC.1994.367598","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367598","url":null,"abstract":"In this paper, a theoretical method is described for the optimization of a CMOS driven, center tap terminated network. This method is verified by circuit simulations. In the simulations, we have assumed a 70 ohm characteristic impedance of the board interconnects and at the same time, n number of various loads connected at different points on that line. Each of these loads has some stub length that can vary from 1.0 inch to 1.5 inch depending on the packaging technology. The above example is a shared bus situation. This method will also work on other topologies as long as the effective characteristic impedance of that topology is less than Zmin, where Zmin is the minimum characteristic impedance that the CMOS driver can support for a given noise criteria.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"41 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116729646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367649
F. Djennas, Wilhelm Sterlin
The plastic Quad Flat Package has evolved into a large, high pin count package, however higher reliability and thermal dissipation requirements constitute the boundary conditions it must overcome to evolve as a viable high density package. The present mold compounds used as encapsulants have poor thermal conductivities and represent a large portion of the thermal resistance in the plastic package. Existing thermally enhanced plastic packages are prone to delamination, and higher costs. A new plastic package is proposed herein that achieves a new level of reliability and performance, all at a cost lower than the standard plastic package. The ESPP package integrity is analyzed and compared to other thermally enhanced packages. Thermal performance is measured and compared to other packages.<>
{"title":"A novel, lower cost, thermally enhanced exposed silicon plastic package (ESPP)","authors":"F. Djennas, Wilhelm Sterlin","doi":"10.1109/ECTC.1994.367649","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367649","url":null,"abstract":"The plastic Quad Flat Package has evolved into a large, high pin count package, however higher reliability and thermal dissipation requirements constitute the boundary conditions it must overcome to evolve as a viable high density package. The present mold compounds used as encapsulants have poor thermal conductivities and represent a large portion of the thermal resistance in the plastic package. Existing thermally enhanced plastic packages are prone to delamination, and higher costs. A new plastic package is proposed herein that achieves a new level of reliability and performance, all at a cost lower than the standard plastic package. The ESPP package integrity is analyzed and compared to other thermally enhanced packages. Thermal performance is measured and compared to other packages.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115784233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367537
C. S. Chang, A. Agrawal
The rough surface of the copper foil, introduced to enhance its interfacial adhesion to the dielectric medium, will increase the signal propagation time constant and reduce the characteristic impedance. A high resolution resonant measurement technique will be presented for such study. The internal inductance will increase both the propagation time constant and the characteristic impedance. It adds an additional delay term, proportional to the square root of the signal rise time in the transient measurement. We will compare the results of different measurement techniques in this paper.<>
{"title":"Fine line thin dielectric circuit board characterization","authors":"C. S. Chang, A. Agrawal","doi":"10.1109/ECTC.1994.367537","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367537","url":null,"abstract":"The rough surface of the copper foil, introduced to enhance its interfacial adhesion to the dielectric medium, will increase the signal propagation time constant and reduce the characteristic impedance. A high resolution resonant measurement technique will be presented for such study. The internal inductance will increase both the propagation time constant and the characteristic impedance. It adds an additional delay term, proportional to the square root of the signal rise time in the transient measurement. We will compare the results of different measurement techniques in this paper.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115436985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367595
N. Gasparini, B. Bhattacharyya
In this paper we are going to show a method of defining a group of C4 bumps that can be placed in a repeated manner on silicon die. It is also shown that for a given package design guideline all these bumps can be routed in a given package layer. This method also allows one to route a maximum number of C4 bumps for a given number of package layers. These groups of bumps can be placed along the die edge, along the diagonals of the die, or both. This method is also verified by extensive experimental drawings on various die sizes, as well as for various package design guidelines. It is shown that this method takes the minimum distance from the die edge for the placement of the maximum number of bumps for a given package routing layer. If the numbers of I/Os are reasonable compared to the die size, then this design methodology can help one design a set of bond pads in the die that can be utilized both for C4 and for wire bond technology.<>
{"title":"A method of designing a group of bumps for C4 packages to maximize the number of bumps and minimize the number of package layers","authors":"N. Gasparini, B. Bhattacharyya","doi":"10.1109/ECTC.1994.367595","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367595","url":null,"abstract":"In this paper we are going to show a method of defining a group of C4 bumps that can be placed in a repeated manner on silicon die. It is also shown that for a given package design guideline all these bumps can be routed in a given package layer. This method also allows one to route a maximum number of C4 bumps for a given number of package layers. These groups of bumps can be placed along the die edge, along the diagonals of the die, or both. This method is also verified by extensive experimental drawings on various die sizes, as well as for various package design guidelines. It is shown that this method takes the minimum distance from the die edge for the placement of the maximum number of bumps for a given package routing layer. If the numbers of I/Os are reasonable compared to the die size, then this design methodology can help one design a set of bond pads in the die that can be utilized both for C4 and for wire bond technology.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123181722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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