Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367634
M. Aamagi, H. Seno, K. Ebe, R. Baumann, H. Kitagawa
The increasingly severe demands of concurrently increasing die size while reducing package size have made the mechanical stability of novel surface mount technologies a primary concern. Package cracks induced by interfacial delamination between the chip backside surface and the epoxy molding resin are a major failure mode in Lead-On-Chip (LOC) packages. This interfacial delamination is caused by contamination of the backside surface by the wafer tape adhesive. The physical and chemical parameters of the backside surface and tape adhesive which lead to interfacial delaminations in LOC packages are described along with a method to alleviate the problem. To investigate which adhesive attributes impacted interfacial delamination, wafer tape adhesive samples were prepared with a variety of different base polymers, oligomers, cross-linking agents, initiative agents, and additive agents. The degree and type of backside contamination left by these various adhesives was determined with scanning electron microscope (SEM) and scanning acoustic tomography (SAT) techniques. The adhesive and the chip backside surfaces were characterised with viscoelastic, particle count, water contact angle, and atomic force microscope (AFM) measurements.<>
{"title":"Cracking failures in lead-on-chip packages induced by chip backside contamination","authors":"M. Aamagi, H. Seno, K. Ebe, R. Baumann, H. Kitagawa","doi":"10.1109/ECTC.1994.367634","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367634","url":null,"abstract":"The increasingly severe demands of concurrently increasing die size while reducing package size have made the mechanical stability of novel surface mount technologies a primary concern. Package cracks induced by interfacial delamination between the chip backside surface and the epoxy molding resin are a major failure mode in Lead-On-Chip (LOC) packages. This interfacial delamination is caused by contamination of the backside surface by the wafer tape adhesive. The physical and chemical parameters of the backside surface and tape adhesive which lead to interfacial delaminations in LOC packages are described along with a method to alleviate the problem. To investigate which adhesive attributes impacted interfacial delamination, wafer tape adhesive samples were prepared with a variety of different base polymers, oligomers, cross-linking agents, initiative agents, and additive agents. The degree and type of backside contamination left by these various adhesives was determined with scanning electron microscope (SEM) and scanning acoustic tomography (SAT) techniques. The adhesive and the chip backside surfaces were characterised with viscoelastic, particle count, water contact angle, and atomic force microscope (AFM) measurements.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"187 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133445167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367543
T. R. Conrad, R. L. Shook
Ambient moisture uptake in plastic surface mount IC packages can cause delamination of critical internal surfaces within the package during reflow assembly. Delaminations can result in reduced thermal cycling life performance or provide for a pathway for the ingress of chemicals and contaminates. The effects that moisture/reflow induced delaminations can have on the thermal performance of plastic packaged ICs are not entirely understood. In this paper, the thermal performance of moisture/reflow delaminated ICs is reported. The effective sensitivity of the thermal performance as a result of the moisture/reflow induced delaminations was measured by experimental thermal resistance measurements (/spl theta//sub JA/) and compared to theoretical calculations based on Finite Element Analysis (FEA). Both 3-D and 2-D FEA models were developed for predictive responses which gave excellent correlation to the experimental measurements. The results showed that interfacial delaminations can cause a measurable increase in /spl theta//sub JA/. The magnitude of the increase is found to be proportional to the power consumption of the device and dependent on the delamination gap thickness. Expected reliability degradation as a result of die temperature rise from the interfacial delaminations is most significant for plastic packaged devices of power ratings greater than about 1 W.<>
{"title":"Impact of moisture/reflow induced delaminations on integrated circuit thermal performance","authors":"T. R. Conrad, R. L. Shook","doi":"10.1109/ECTC.1994.367543","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367543","url":null,"abstract":"Ambient moisture uptake in plastic surface mount IC packages can cause delamination of critical internal surfaces within the package during reflow assembly. Delaminations can result in reduced thermal cycling life performance or provide for a pathway for the ingress of chemicals and contaminates. The effects that moisture/reflow induced delaminations can have on the thermal performance of plastic packaged ICs are not entirely understood. In this paper, the thermal performance of moisture/reflow delaminated ICs is reported. The effective sensitivity of the thermal performance as a result of the moisture/reflow induced delaminations was measured by experimental thermal resistance measurements (/spl theta//sub JA/) and compared to theoretical calculations based on Finite Element Analysis (FEA). Both 3-D and 2-D FEA models were developed for predictive responses which gave excellent correlation to the experimental measurements. The results showed that interfacial delaminations can cause a measurable increase in /spl theta//sub JA/. The magnitude of the increase is found to be proportional to the power consumption of the device and dependent on the delamination gap thickness. Expected reliability degradation as a result of die temperature rise from the interfacial delaminations is most significant for plastic packaged devices of power ratings greater than about 1 W.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130563696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367547
S. Omi, T. Maruyama, T. Ishio, A. Narai, Y. Sota, K. Toyosawa, K. Fujiita, T. Maeda
The authors developed an Ultra-Thin Small Outline Package (UTSOP) with a package thickness of 0.45 mm. In spite of the fact that it is a significant reduction relative to conventional TSOPs (1.0 mm thick), the inner leads of the lead frame can be bonded to the electrodes on the chip with gold wire as with a conventional plastic package. It is feasible since the lead that supports the chip through insulating tape (support lead) is placed on the top side of the chip. Establishing molding technology and overcoming problems such as warping of the package or chip during assembly were key points in the development of the UTSOP. The UTSOP retains the same level of reliability as a TSOP.<>
{"title":"Development of 0.45 mm thick Ultra-Thin Small Outline Package (UTSOP)","authors":"S. Omi, T. Maruyama, T. Ishio, A. Narai, Y. Sota, K. Toyosawa, K. Fujiita, T. Maeda","doi":"10.1109/ECTC.1994.367547","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367547","url":null,"abstract":"The authors developed an Ultra-Thin Small Outline Package (UTSOP) with a package thickness of 0.45 mm. In spite of the fact that it is a significant reduction relative to conventional TSOPs (1.0 mm thick), the inner leads of the lead frame can be bonded to the electrodes on the chip with gold wire as with a conventional plastic package. It is feasible since the lead that supports the chip through insulating tape (support lead) is placed on the top side of the chip. Establishing molding technology and overcoming problems such as warping of the package or chip during assembly were key points in the development of the UTSOP. The UTSOP retains the same level of reliability as a TSOP.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116810289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367603
M. Reill
The numerical procedure described in this work performs analysis of 3-dimensional structures by partitioning the geometry in basic blocks, which can be described as multi-layer-structures with rectangular base area. Combining such basic regions, complex geometries like stacked structures can be treated. The Laplacian equation describing the steady state heat flux is solved efficiently in three dimensions using a Fast Fourier Transform (FFT) algorithm. By the use of an iterative procedure handling of inhomogeneous, nonlinear boundary conditions on the top and bottom side of the geometry and modeling complex geometries by matching the solution at the interface of two or more basic blocks is possible. This allows to take into account boundary conditions calculated by the analytical solution of the Navier-Stokes equations describing convection and the Stefan Boltzmann law describing radiation. Experimental studies using infrared thermography, thermal sensors and laser doppler velocimetry were carried out. By measurement of the temperature distribution and the flow field it is shown, that the simultaneous solution of the heat flux in the solid structure and the heat-transfer by boundary approximation improves the accuracy of temperature computation and expands the application range of the Fourier method. It is shown, that parallel placed substrates with bare chips can be handled with high accuracy by the proposed model for laminar flow. The model gives good results for mountings up to 0.6 mm height. For low fluid velocities up to 1 m/s and natural convection the model works also for higher mountings (e.g. SMD). Further applications demonstrate the accuracy and applicability of the presented program. The simple model-creation and the numerical efficiency enables the handling of problems with a high number of components and high aspect ratios between the components and the board. Analytical models describing heat dissipation in special applications can be easily incorporated for simultaneous solution.<>
{"title":"Iterative direct solution method for thermal analysis of electronic equipment","authors":"M. Reill","doi":"10.1109/ECTC.1994.367603","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367603","url":null,"abstract":"The numerical procedure described in this work performs analysis of 3-dimensional structures by partitioning the geometry in basic blocks, which can be described as multi-layer-structures with rectangular base area. Combining such basic regions, complex geometries like stacked structures can be treated. The Laplacian equation describing the steady state heat flux is solved efficiently in three dimensions using a Fast Fourier Transform (FFT) algorithm. By the use of an iterative procedure handling of inhomogeneous, nonlinear boundary conditions on the top and bottom side of the geometry and modeling complex geometries by matching the solution at the interface of two or more basic blocks is possible. This allows to take into account boundary conditions calculated by the analytical solution of the Navier-Stokes equations describing convection and the Stefan Boltzmann law describing radiation. Experimental studies using infrared thermography, thermal sensors and laser doppler velocimetry were carried out. By measurement of the temperature distribution and the flow field it is shown, that the simultaneous solution of the heat flux in the solid structure and the heat-transfer by boundary approximation improves the accuracy of temperature computation and expands the application range of the Fourier method. It is shown, that parallel placed substrates with bare chips can be handled with high accuracy by the proposed model for laminar flow. The model gives good results for mountings up to 0.6 mm height. For low fluid velocities up to 1 m/s and natural convection the model works also for higher mountings (e.g. SMD). Further applications demonstrate the accuracy and applicability of the presented program. The simple model-creation and the numerical efficiency enables the handling of problems with a high number of components and high aspect ratios between the components and the board. Analytical models describing heat dissipation in special applications can be easily incorporated for simultaneous solution.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130318678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367560
G. O'malley, J. Giesler, S. Machuga
Flip chip technology, where the unpackaged silicon chip is assembled directly to an organic substrate, provides an unique interconnect structure that significantly reduces the substrate area required by traditional surface mount integrated circuit packages. Without the protection for the chip that a package body affords however, reduced mechanical robustness and a decrease in reliability performance are potential concerns. In addition, the inherent thermal mismatch between the chip and substrate, particularly with an organic printed circuit board, will produce an accumulation of stress in the solder joints under normal operating conditions that can result in relatively premature failures. Coupling the chip and substrate together with an encapsulation material under the chip face has successfully overcome these mechanical and reliability issues. However, the success of the encapsulation is dependent on many factors. Among these are the encapsulant's material properties, and its compatibility with the chip and substrate surfaces. Thus, the selection of the basic materials to be used in the Flip Chip on Board (FCOB) assembly are interrelated and critical to the subsequent performance of the completed assembly.<>
{"title":"The importance of material selection for flip chip on board assemblies","authors":"G. O'malley, J. Giesler, S. Machuga","doi":"10.1109/ECTC.1994.367560","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367560","url":null,"abstract":"Flip chip technology, where the unpackaged silicon chip is assembled directly to an organic substrate, provides an unique interconnect structure that significantly reduces the substrate area required by traditional surface mount integrated circuit packages. Without the protection for the chip that a package body affords however, reduced mechanical robustness and a decrease in reliability performance are potential concerns. In addition, the inherent thermal mismatch between the chip and substrate, particularly with an organic printed circuit board, will produce an accumulation of stress in the solder joints under normal operating conditions that can result in relatively premature failures. Coupling the chip and substrate together with an encapsulation material under the chip face has successfully overcome these mechanical and reliability issues. However, the success of the encapsulation is dependent on many factors. Among these are the encapsulant's material properties, and its compatibility with the chip and substrate surfaces. Thus, the selection of the basic materials to be used in the Flip Chip on Board (FCOB) assembly are interrelated and critical to the subsequent performance of the completed assembly.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130109369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367535
H. Nakayoshi, N. Izawa, T. Ishikawa, T. Suzuki
The LOC (Lead On Chip) structure has been considered as an effective technology to encapsulate a large LSI memory chip into a small package. The main feature of the structure is contact of leadframes onto the active chip area with adhesive sandwiched in between. Therefore, the design concept of LOC greatly depends on the characteristics of the adhesive layer. The key technologies for LOC development are summarized as: 1. To lessen damage on chip during die-attach and wire bonding; 2. To secure sufficient wire bendability above the organic adhesive; and 3. To reduce package crack rate during the solder reflowing process. We have developed a new adhesive tape which is composed of single-layer thermoplastic polyimide siloxanes. Due to the absence of a base film, the single layer adhesive can be fabricated to any desirable thickness. During its softening process, the thick adhesive film encloses dust that, otherwise, could damage the chip surface. These properties, by providing a large Young's modulus of the film at high temperature and contamination-free lead surface, enable us to secure sufficient lead-wire bendability. The other materialistic advantage of the adhesive is its low moisture absorption. The low moisture absorption results in high resistance against package crack caused by the solder reflowing process. In this paper, we describe how we have selected the LOC adhesive tape through the evaluations of the assembly process and have successfully developed a highly productive and reliable memory package with LOC structure.<>
导联芯片(Lead On Chip)结构被认为是将大型LSI存储芯片封装在小封装中的有效技术。该结构的主要特点是引线框与主动芯片区域接触，中间夹有粘合剂。因此，LOC的设计理念在很大程度上取决于粘接层的特性。LOC开发的关键技术总结为:1。减少贴模和焊线过程中对芯片的损坏;2. 确保金属丝在有机粘合剂上有足够的可弯曲性;和3。降低焊料回流过程中封装的裂纹率。我们研制了一种由单层热塑性聚酰亚胺硅氧烷组成的新型胶带。由于没有基膜，单层粘合剂可以制造成任何所需的厚度。在其软化过程中，厚厚的胶膜包围灰尘，否则可能会损坏芯片表面。这些特性，通过在高温下提供大的杨氏模量的薄膜和无污染的铅表面，使我们能够确保足够的引线可弯曲性。胶粘剂的另一个材料优势是它的低吸湿性。低吸湿性使其具有很高的抗焊料回流过程引起的封装裂纹的能力。在本文中，我们描述了我们如何通过对装配过程的评估来选择LOC胶带，并成功开发出具有LOC结构的高生产率和可靠的存储封装
{"title":"Memory package with LOC structure using new adhesive material","authors":"H. Nakayoshi, N. Izawa, T. Ishikawa, T. Suzuki","doi":"10.1109/ECTC.1994.367535","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367535","url":null,"abstract":"The LOC (Lead On Chip) structure has been considered as an effective technology to encapsulate a large LSI memory chip into a small package. The main feature of the structure is contact of leadframes onto the active chip area with adhesive sandwiched in between. Therefore, the design concept of LOC greatly depends on the characteristics of the adhesive layer. The key technologies for LOC development are summarized as: 1. To lessen damage on chip during die-attach and wire bonding; 2. To secure sufficient wire bendability above the organic adhesive; and 3. To reduce package crack rate during the solder reflowing process. We have developed a new adhesive tape which is composed of single-layer thermoplastic polyimide siloxanes. Due to the absence of a base film, the single layer adhesive can be fabricated to any desirable thickness. During its softening process, the thick adhesive film encloses dust that, otherwise, could damage the chip surface. These properties, by providing a large Young's modulus of the film at high temperature and contamination-free lead surface, enable us to secure sufficient lead-wire bendability. The other materialistic advantage of the adhesive is its low moisture absorption. The low moisture absorption results in high resistance against package crack caused by the solder reflowing process. In this paper, we describe how we have selected the LOC adhesive tape through the evaluations of the assembly process and have successfully developed a highly productive and reliable memory package with LOC structure.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129480437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367530
J. Bousaba, S. Bobbio, S. Goodwin-Johansson, M. Kellam, B. Dudley, J. Jacobson, S. Jones, T. D. DuBois, F. Tranjan
Integrated Force Arrays (IFAs) are membrane based actuators that are made of polyimide material. They are metallized membranes that are flexible enough to undergo substantial deformation when a voltage is applied. IFAs can be patterned using the techniques of VLSI electronics. They can be integrated in arrays to form complex systems that have wide range of applications. The theory of operation and the methods of construction are presented.<>
{"title":"Membrane based actuator-integrated force arrays","authors":"J. Bousaba, S. Bobbio, S. Goodwin-Johansson, M. Kellam, B. Dudley, J. Jacobson, S. Jones, T. D. DuBois, F. Tranjan","doi":"10.1109/ECTC.1994.367530","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367530","url":null,"abstract":"Integrated Force Arrays (IFAs) are membrane based actuators that are made of polyimide material. They are metallized membranes that are flexible enough to undergo substantial deformation when a voltage is applied. IFAs can be patterned using the techniques of VLSI electronics. They can be integrated in arrays to form complex systems that have wide range of applications. The theory of operation and the methods of construction are presented.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122781808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The Carrier and Socket Technology for high pin count Quad Flat Pack, QFP, packages is a set of three components, that can be used in various combinations, that allow for easier manipulation of fine pitch, (fine pitch defined as packages having a lead tip to lead tip spacing of .65 millimeters or less), QFP between various shipping, test, programming, and proto- typing environments. The three components are the small outline Carrier, surface mountable Development Socket, and through hole mountable Programming Socket. The Carrier is designed to protect the leads of the QFP from deformation, while allowing the leads to make electrical connection with the contacts of the two different sockets. The Development Socket is surface mountable with a footprint that is identical to the naked QFP housed within the Carrier. The Programming Socket is a through hole mountable, clam-shell socket, which accepts the same Carrier as the Development Socket.<>
用于高引脚数Quad Flat Pack (QFP)的载波和插座技术(Carrier and Socket Technology)封装由三个组件组成，可以以各种组合方式使用，从而可以更轻松地操作细间距(细间距定义为具有0.65毫米或更小间距的封装)，QFP适用于各种运输、测试、编程和原型环境。这三种组件分别是小轮廓托架、面装开发插座和通孔安装编程插座。托架设计用于保护QFP的引线不变形，同时允许引线与两个不同插座的触点进行电气连接。开发插座是表面可安装的，其占地面积与安装在载体内的裸QFP相同。编程插座是一个通孔安装，蛤壳插座，它接受与开发插座相同的载体。
{"title":"Carrier and socket technology for high pin count QFP packages","authors":"J. Foerstel","doi":"10.1109/95.370747","DOIUrl":"https://doi.org/10.1109/95.370747","url":null,"abstract":"The Carrier and Socket Technology for high pin count Quad Flat Pack, QFP, packages is a set of three components, that can be used in various combinations, that allow for easier manipulation of fine pitch, (fine pitch defined as packages having a lead tip to lead tip spacing of .65 millimeters or less), QFP between various shipping, test, programming, and proto- typing environments. The three components are the small outline Carrier, surface mountable Development Socket, and through hole mountable Programming Socket. The Carrier is designed to protect the leads of the QFP from deformation, while allowing the leads to make electrical connection with the contacts of the two different sockets. The Development Socket is surface mountable with a footprint that is identical to the naked QFP housed within the Carrier. The Programming Socket is a through hole mountable, clam-shell socket, which accepts the same Carrier as the Development Socket.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122822343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367505
D.R. Young, A. Morrow, K. Gadkaree, D. E. Quinn
The increased amount of telephony and computer data traffic over single optical fiber lines and the desire to reduce redundancy to decrease capital cost have led to an increased need for high reliability components both in terrestrial and submarine markets. The authors describe a multiclad coupler process which has been used to develop ultra-high reliability couplers suitable for undersea applications. A new packaging process using a new low expansion composite wrap and LCP housing was required to achieve the optical and mechanical stability required. Extensive thermal and mechanical tests of the couplers and packaging materials predict excellent performance over the planned 27 year lifetime of these components.<>
{"title":"Packaging of high reliability couplers","authors":"D.R. Young, A. Morrow, K. Gadkaree, D. E. Quinn","doi":"10.1109/ECTC.1994.367505","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367505","url":null,"abstract":"The increased amount of telephony and computer data traffic over single optical fiber lines and the desire to reduce redundancy to decrease capital cost have led to an increased need for high reliability components both in terrestrial and submarine markets. The authors describe a multiclad coupler process which has been used to develop ultra-high reliability couplers suitable for undersea applications. A new packaging process using a new low expansion composite wrap and LCP housing was required to achieve the optical and mechanical stability required. Extensive thermal and mechanical tests of the couplers and packaging materials predict excellent performance over the planned 27 year lifetime of these components.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117242305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367586
J. Sweet, D. Peterson, J. Emerson
A new assembly test chip, ATC04, designed to measure mechanical stresses at the die surface has been built and tested. This CMOS chip, 0.25 in. on a side, has an array of 25 piezoresistive stress sensing cells, four resistive heaters and two ring oscillators. The ATC04 chip facilitates making stress measurements with relatively simple test equipment and data analysis. The design, use, and accuracy of the chip are discussed and initial results presented from three types of stress measurement experiments: four-point bending calibration, single point bending of a substrate with an ATC04 attached by epoxy, and stress produced by a liquid epoxy encapsulant.<>
{"title":"Liquid encapsulant and uniaxial calibration mechanical stress measurement with the ATC04 assembly test chip","authors":"J. Sweet, D. Peterson, J. Emerson","doi":"10.1109/ECTC.1994.367586","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367586","url":null,"abstract":"A new assembly test chip, ATC04, designed to measure mechanical stresses at the die surface has been built and tested. This CMOS chip, 0.25 in. on a side, has an array of 25 piezoresistive stress sensing cells, four resistive heaters and two ring oscillators. The ATC04 chip facilitates making stress measurements with relatively simple test equipment and data analysis. The design, use, and accuracy of the chip are discussed and initial results presented from three types of stress measurement experiments: four-point bending calibration, single point bending of a substrate with an ATC04 attached by epoxy, and stress produced by a liquid epoxy encapsulant.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115579562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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