Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367553
J. Constable
Methods are described which have successfully measured the electrical resistance change induced by strain and fatigue in leaded electrical interconnections. The dependance of electrical resistance on elastic strain, plastic deformation, and cyclic fatigue is examined. A type of spectroscopy for fatigue testing which measures the amplitude of the resistance change at harmonics of the fatigue cycling frequency is described. The spectroscopic method is shown to have the advantage of greater sensitivity, and of providing more information than conventional methods. An analytical frame work is developed, and recently published data for gull-wing leads and lap shear solder joints are examined using it. The cause for the limiting resistance fluctuations in these measurements is investigated. It is argued that after calibration, the method can be used to measure strain level, shorten fatigue tests, and reliably detect interconnect failures.<>
{"title":"Use of interconnect resistance as a reliability tool","authors":"J. Constable","doi":"10.1109/ECTC.1994.367553","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367553","url":null,"abstract":"Methods are described which have successfully measured the electrical resistance change induced by strain and fatigue in leaded electrical interconnections. The dependance of electrical resistance on elastic strain, plastic deformation, and cyclic fatigue is examined. A type of spectroscopy for fatigue testing which measures the amplitude of the resistance change at harmonics of the fatigue cycling frequency is described. The spectroscopic method is shown to have the advantage of greater sensitivity, and of providing more information than conventional methods. An analytical frame work is developed, and recently published data for gull-wing leads and lap shear solder joints are examined using it. The cause for the limiting resistance fluctuations in these measurements is investigated. It is argued that after calibration, the method can be used to measure strain level, shorten fatigue tests, and reliably detect interconnect failures.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132668384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367552
C. Lizzul, J. Constable, G. Westby
The electrical resistance of lap shear (60%Sn-40%Pb) solder joints has been measured while the specimens were undergoing cyclic fatigue testing. The resistance measuring system had a noise level of less than one nano-ohm. An FFT analyzer was used to transform the time varying resistance to the frequency domain. Measurements were made of the average resistance (zero frequency amplitude), amplitude of the resistance change at the mechanical drive frequency, and the amplitudes of the resistance change at the second and third harmonics of the drive frequency. The average resistance and resistance amplitude at the drive frequency exhibited a systematic behavior as the specimens were cycled toward failure. Initially the average resistance increased, followed by a much stronger decrease, and lastly increased markedly as the specimen fractured. The decreasing resistance portion of this signature which occurs prior to mechanical failure (i.e. crack propagation) can be used to detect failure in solder joints much sooner than present techniques.<>
{"title":"Fatigue investigation of lap shear solder joints using resistance spectroscopy","authors":"C. Lizzul, J. Constable, G. Westby","doi":"10.1109/ECTC.1994.367552","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367552","url":null,"abstract":"The electrical resistance of lap shear (60%Sn-40%Pb) solder joints has been measured while the specimens were undergoing cyclic fatigue testing. The resistance measuring system had a noise level of less than one nano-ohm. An FFT analyzer was used to transform the time varying resistance to the frequency domain. Measurements were made of the average resistance (zero frequency amplitude), amplitude of the resistance change at the mechanical drive frequency, and the amplitudes of the resistance change at the second and third harmonics of the drive frequency. The average resistance and resistance amplitude at the drive frequency exhibited a systematic behavior as the specimens were cycled toward failure. Initially the average resistance increased, followed by a much stronger decrease, and lastly increased markedly as the specimen fractured. The decreasing resistance portion of this signature which occurs prior to mechanical failure (i.e. crack propagation) can be used to detect failure in solder joints much sooner than present techniques.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133647668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367496
P. Beckett, A. R. Fleming, R. J. Foster, J. M. Gilbert, A. V. Polijanczuk, D. G. Whitehead
The trend to high pin-count high density packaging in surface mount assembly has highlighted inherent difficulties in the automatic placement and soldering of these very fine pitch devices. The integration of a laser soldering operation with the placement process can provide one solution to the problem, particularly where the attachment of large high-value devices is involved. This paper will describe the use of a solid state laser diode power source as part of an automatic pick-place-solder technique which, by allowing a secondary assembly process for specific devices, avoids the environmental extremes introduced by conventional soldering.<>
{"title":"An automated pick-place laser soldering process for electronics assembly","authors":"P. Beckett, A. R. Fleming, R. J. Foster, J. M. Gilbert, A. V. Polijanczuk, D. G. Whitehead","doi":"10.1109/ECTC.1994.367496","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367496","url":null,"abstract":"The trend to high pin-count high density packaging in surface mount assembly has highlighted inherent difficulties in the automatic placement and soldering of these very fine pitch devices. The integration of a laser soldering operation with the placement process can provide one solution to the problem, particularly where the attachment of large high-value devices is involved. This paper will describe the use of a solid state laser diode power source as part of an automatic pick-place-solder technique which, by allowing a secondary assembly process for specific devices, avoids the environmental extremes introduced by conventional soldering.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129308010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367506
O. Strand, M. Lowry, S. Lu, D. C. Nelson, D. Nikkel, M. Pocha, K. Young
The high cost of optoelectronic (OE) devices is due mainly to the labor-intensive packaging process. Manually pigtailing such devices as single-mode laser diodes and modulators is very time consuming with poor quality control. The Photonics Program and the Engineering Research Division at LLNL are addressing several issues associated with automatically packaging OE devices. A fully automated system must include high-precision fiber alignment, fiber attachment techniques, in-situ quality control, and parts handling and feeding. This paper will present on-going work at LLNL in the areas of automated fiber alignment and fiber attachment. For the fiber alignment, we are building an automated fiber pigtailing machine (AFPM) which combines computer vision and object recognition algorithms with active feedback to perform sub-micron alignments of single-mode fibers to modulators and laser diodes. We expect to perform sub-micron alignments in less than five minutes with this technology. For fiber attachment, we are building various geometries of silicon microbenches which include onboard heaters to solder metal-coated fibers and other components in place; these designs are completely compatible with an automated process of OE packaging.<>
{"title":"Automated fiber pigtailing technology","authors":"O. Strand, M. Lowry, S. Lu, D. C. Nelson, D. Nikkel, M. Pocha, K. Young","doi":"10.1109/ECTC.1994.367506","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367506","url":null,"abstract":"The high cost of optoelectronic (OE) devices is due mainly to the labor-intensive packaging process. Manually pigtailing such devices as single-mode laser diodes and modulators is very time consuming with poor quality control. The Photonics Program and the Engineering Research Division at LLNL are addressing several issues associated with automatically packaging OE devices. A fully automated system must include high-precision fiber alignment, fiber attachment techniques, in-situ quality control, and parts handling and feeding. This paper will present on-going work at LLNL in the areas of automated fiber alignment and fiber attachment. For the fiber alignment, we are building an automated fiber pigtailing machine (AFPM) which combines computer vision and object recognition algorithms with active feedback to perform sub-micron alignments of single-mode fibers to modulators and laser diodes. We expect to perform sub-micron alignments in less than five minutes with this technology. For fiber attachment, we are building various geometries of silicon microbenches which include onboard heaters to solder metal-coated fibers and other components in place; these designs are completely compatible with an automated process of OE packaging.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128823059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367582
N. Yamanaka, K. Endo, K. Genda, H. Fukuda, T. Kishimoto, S. Sasaki
This paper describes a 320 Gb/s high-speed multi-chip ATM switching system for broadband ISDN. This system employs a copper-polyimide MCM with 4-layer copper-polyimide signal transmission layers and 15-layer ceramic power supply layers. The system uses 64 MCMs that are interconnected by 98-highway flexible printed circuit connector. Si-bipolar VLSIs are mounted on MCM using the 150 /spl mu/m very-thin pitch outer lead TAB technique. In addition, a high-performance heat-pipe air cooling technique is adopted. The system switches ATM cells up to 320 Gb/s throughput and it is applicable for future B-ISDN.<>
{"title":"320 Gb/s high-speed ATM switching system hardware technologies based on copper-polyimide MCM","authors":"N. Yamanaka, K. Endo, K. Genda, H. Fukuda, T. Kishimoto, S. Sasaki","doi":"10.1109/ECTC.1994.367582","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367582","url":null,"abstract":"This paper describes a 320 Gb/s high-speed multi-chip ATM switching system for broadband ISDN. This system employs a copper-polyimide MCM with 4-layer copper-polyimide signal transmission layers and 15-layer ceramic power supply layers. The system uses 64 MCMs that are interconnected by 98-highway flexible printed circuit connector. Si-bipolar VLSIs are mounted on MCM using the 150 /spl mu/m very-thin pitch outer lead TAB technique. In addition, a high-performance heat-pipe air cooling technique is adopted. The system switches ATM cells up to 320 Gb/s throughput and it is applicable for future B-ISDN.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129105575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367636
P. Bujard, G. Kuhnlein, S. Ino, T. Shiobara
Alumina loaded new molding compounds feature a thermal conductivity up to 4.5 W/mK, a water uptake smaller than 0.2 weight %, a coefficient of thermal expansion of 10 ppm/K and an excellent popcorn resistance (0 cracks from 6). The thermal conductivity of such particulate-loaded polymers has been investigated as a function of the volume content (0 to 80%) of aluminum oxide, quartz and fused quartz. The thermal expansion and the specific heat have also been recorded. A new model allows one to calculate the thermal conductivity and the thermal expansion within a couple percent.<>
{"title":"Thermal conductivity of molding compounds for plastic packaging","authors":"P. Bujard, G. Kuhnlein, S. Ino, T. Shiobara","doi":"10.1109/ECTC.1994.367636","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367636","url":null,"abstract":"Alumina loaded new molding compounds feature a thermal conductivity up to 4.5 W/mK, a water uptake smaller than 0.2 weight %, a coefficient of thermal expansion of 10 ppm/K and an excellent popcorn resistance (0 cracks from 6). The thermal conductivity of such particulate-loaded polymers has been investigated as a function of the volume content (0 to 80%) of aluminum oxide, quartz and fused quartz. The thermal expansion and the specific heat have also been recorded. A new model allows one to calculate the thermal conductivity and the thermal expansion within a couple percent.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115722779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367536
Y. Okugawa, T. Yoshida, T. Suzuki, H. Nakayoshi
A new technology of the plastic package is offered in volume production of 16 Mb DRAM. This new package, called the LOC (Lead On Chip) structured package, is characterized by directly bonding the lead frame to the surface of the chip with a adhesive tape. This technology requires some new type packaging materials. Adhesive tape is the key material used in the LOC structure package. We developed the polyimide siloxane as the adhesive for the LOC adhesive tape. The polyimide siloxane has several advantages for use in the LOC adhesive tape, namely, small amount of outgassing volatiles, low content of ionic impurities, low moisture absorption and significant bendability. Moreover, the glass transition temperature of polyimide siloxane adhesive can be controlled over a wide range from 100 to 220/spl deg/C by controlling the content of the component especially the silicone. The single layer adhesive tape which had no base film and was constructed only of the polyimide siloxane was manufactured by the casting method. This single layer structure can enhance the advantage of adhesive polyimide siloxane and reduce the problems due to the interface of adhesive and base film. Actually, the single layer structured LOC tape has the outstanding advantage of low moisture absorption, so can solve the problem of delamination which occurs at the various interfaces of LOC tape and the other materials in the DRAM package.<>
新技术的塑料封装提供量产16mb的DRAM。这种新封装称为LOC (Lead On Chip)结构封装，其特点是用胶带将引线框架直接粘合到芯片表面。这一技术需要一些新型的包装材料。胶带是LOC结构封装中使用的关键材料。我们开发了聚酰亚胺硅氧烷作为LOC胶带的粘合剂。聚酰亚胺硅氧烷用于LOC胶带具有放气挥发物量少、离子杂质含量低、吸湿性低、可弯曲性好等优点。此外，聚酰亚胺硅氧烷胶粘剂的玻璃化转变温度可以通过控制组分特别是硅酮的含量来控制在100 ~ 220℃的范围内。采用浇铸法制备了无基膜的聚酰亚胺硅氧烷单层胶带。这种单层结构可以增强胶粘剂聚酰亚胺硅氧烷的优势，减少胶粘剂与基膜的界面问题。实际上，单层结构的LOC磁带具有吸湿率低的突出优点，因此可以解决LOC磁带与DRAM封装中其他材料的各种接口处发生的分层问题。
{"title":"New type LOC adhesive tapes","authors":"Y. Okugawa, T. Yoshida, T. Suzuki, H. Nakayoshi","doi":"10.1109/ECTC.1994.367536","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367536","url":null,"abstract":"A new technology of the plastic package is offered in volume production of 16 Mb DRAM. This new package, called the LOC (Lead On Chip) structured package, is characterized by directly bonding the lead frame to the surface of the chip with a adhesive tape. This technology requires some new type packaging materials. Adhesive tape is the key material used in the LOC structure package. We developed the polyimide siloxane as the adhesive for the LOC adhesive tape. The polyimide siloxane has several advantages for use in the LOC adhesive tape, namely, small amount of outgassing volatiles, low content of ionic impurities, low moisture absorption and significant bendability. Moreover, the glass transition temperature of polyimide siloxane adhesive can be controlled over a wide range from 100 to 220/spl deg/C by controlling the content of the component especially the silicone. The single layer adhesive tape which had no base film and was constructed only of the polyimide siloxane was manufactured by the casting method. This single layer structure can enhance the advantage of adhesive polyimide siloxane and reduce the problems due to the interface of adhesive and base film. Actually, the single layer structured LOC tape has the outstanding advantage of low moisture absorption, so can solve the problem of delamination which occurs at the various interfaces of LOC tape and the other materials in the DRAM package.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"259 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116220929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367574
H. van Tongeren, J.W. Kokkelink, H. Tjassens
A coaxial laser module based on a small CD laser header is described. The module has a diameter of 5.6 mm and a length of 14 mm. By modifying the standard CD laser header the electrical performance could be up-graded to a 5 GHz bandwidth. The coupling optics is designed for low feedback and includes an optical isolator. Coupling efficiencies up to 80% have been achieved.<>
{"title":"A small coaxial laser module for the Gb/s transmission-speed range","authors":"H. van Tongeren, J.W. Kokkelink, H. Tjassens","doi":"10.1109/ECTC.1994.367574","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367574","url":null,"abstract":"A coaxial laser module based on a small CD laser header is described. The module has a diameter of 5.6 mm and a length of 14 mm. By modifying the standard CD laser header the electrical performance could be up-graded to a 5 GHz bandwidth. The coupling optics is designed for low feedback and includes an optical isolator. Coupling efficiencies up to 80% have been achieved.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123203198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367502
H. Chan
Although hard-defects may be detectable in factory tests, weak products may exhibit failures or degrade only under certain stress conditions. Without stress testing, these weak products may often be shipped to customers causing early failures in the field. A candidate product for stress testing needs to get more business benefits to more than pay off the cost of stress testing. A business measure of the success of the stress testing program is the net benefit, which is the total benefit minus the total cost of the program. The optimum stress testing program maximizes this net benefit. A given unit of a product has a probability of encountering a maximum stress X during its product life. It also has a probability of possessing a product yield strength Y, which is the maximum stress the unit can survive without failure. While the strength distribution depends on the design and manufacture processes, the distribution of the maximum stress is determined by the customers' environment. A convenient picture is to construct the contour map of the joint probability distribution of X and Y. In this contour map, a unit falling in the YX region will not result in field failure. The effects of stress testing at a given maximum stress level, X/sup ST/, are shown by a dividing line on the product strength into stress test failure and stress test pass. The units in the contour map are then divided into four regions by the Y=X line and the X/sup ST/ line. The cost and benefits may now be evaluated for each region. Now the value of X/sup ST/ is a free parameter that determines the relative size of each region. The second free parameter is the fraction of units going through stress testing. These two parameters may be adjusted to maximize the net benefit of the stress testing program.<>
{"title":"A formulation to optimize stress testing","authors":"H. Chan","doi":"10.1109/ECTC.1994.367502","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367502","url":null,"abstract":"Although hard-defects may be detectable in factory tests, weak products may exhibit failures or degrade only under certain stress conditions. Without stress testing, these weak products may often be shipped to customers causing early failures in the field. A candidate product for stress testing needs to get more business benefits to more than pay off the cost of stress testing. A business measure of the success of the stress testing program is the net benefit, which is the total benefit minus the total cost of the program. The optimum stress testing program maximizes this net benefit. A given unit of a product has a probability of encountering a maximum stress X during its product life. It also has a probability of possessing a product yield strength Y, which is the maximum stress the unit can survive without failure. While the strength distribution depends on the design and manufacture processes, the distribution of the maximum stress is determined by the customers' environment. A convenient picture is to construct the contour map of the joint probability distribution of X and Y. In this contour map, a unit falling in the YX region will not result in field failure. The effects of stress testing at a given maximum stress level, X/sup ST/, are shown by a dividing line on the product strength into stress test failure and stress test pass. The units in the contour map are then divided into four regions by the Y=X line and the X/sup ST/ line. The cost and benefits may now be evaluated for each region. Now the value of X/sup ST/ is a free parameter that determines the relative size of each region. The second free parameter is the fraction of units going through stress testing. These two parameters may be adjusted to maximize the net benefit of the stress testing program.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"14 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120904360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367650
M. Karnezos, S. Chang, N. Chidambaram, C. Tak, Ah San Kyu, E. Combs
EDQUAD represents a new family of packages designed for applications that require enhanced thermal and electrical performance not provided by the standard plastic packages. It includes standard Metric QFP, 1.4 mm thick TQFP and PLCC packages ranging from 7 mm-40 mm bodies and leadcounts in the 20-304 range. The packages are designed with an integral heatspreader exposed to air, used as a ground plane as well. The die is attached directly to the heatspreader to minimize the thermal resistance. The power and ground pads of the die can be wire bonded directly on separate internal rings to minimize the inductance. Measurements on a 28/spl times/28 mm, 208 lead EDQUAD show that the power dissipation is doubled to over 4 Watt/chip compared to an equivalent plastic QFP and, with an external heatsink attached, the package can dissipate up to 10 Watt/chip for most applications. The lead impedance can be controlled to 50 Ohm and the inductance of ground/power connections is significantly reduced. The package reliability meets the commonly accepted standards.<>
EDQUAD代表了一个新的包装系列，专为标准塑料包装无法提供的需要增强热和电气性能的应用而设计。它包括标准公制QFP, 1.4 mm厚TQFP和PLCC封装，从7 mm-40 mm的主体和引线数在20-304范围内。这些封装设计了一个暴露在空气中的整体散热器，也用作接地面。模具是直接连接到散热器，以尽量减少热阻。模具的电源和接地垫可以直接在单独的内部环上进行钢丝粘合，以尽量减少电感。对28/spl倍/28 mm, 208引脚EDQUAD的测量表明，与等效的塑料QFP相比，功耗增加了一倍，超过4瓦特/芯片，并且在附加外部散热器的情况下，该封装可以在大多数应用中消耗高达10瓦特/芯片。引线阻抗可控制在50欧姆，接地/电源连接电感显著降低。封装可靠性符合通用标准
{"title":"EDQUAD-an enhanced performance plastic package","authors":"M. Karnezos, S. Chang, N. Chidambaram, C. Tak, Ah San Kyu, E. Combs","doi":"10.1109/ECTC.1994.367650","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367650","url":null,"abstract":"EDQUAD represents a new family of packages designed for applications that require enhanced thermal and electrical performance not provided by the standard plastic packages. It includes standard Metric QFP, 1.4 mm thick TQFP and PLCC packages ranging from 7 mm-40 mm bodies and leadcounts in the 20-304 range. The packages are designed with an integral heatspreader exposed to air, used as a ground plane as well. The die is attached directly to the heatspreader to minimize the thermal resistance. The power and ground pads of the die can be wire bonded directly on separate internal rings to minimize the inductance. Measurements on a 28/spl times/28 mm, 208 lead EDQUAD show that the power dissipation is doubled to over 4 Watt/chip compared to an equivalent plastic QFP and, with an external heatsink attached, the package can dissipate up to 10 Watt/chip for most applications. The lead impedance can be controlled to 50 Ohm and the inductance of ground/power connections is significantly reduced. The package reliability meets the commonly accepted standards.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130346546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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