Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367522
A.F.J. Baggerman, M.J. Batenburg
Au-Sn flip chip bonding is successfully introduced for the mounting of integrated circuits on flexible polyimide prints. Flip chip was used, since in most consumer electronics, and more specific for hearing instruments the useable volume is decreasing very rapidly. Since on the same flex print reflow soldering of other components is required, a high melting soldering process is preferred. An additional advantage of the Au-Sn process is that the bumps do not completely melt, and a certain stand off height is guaranteed. The bumps are deposited on top of the bondpads and are bonded to Cu tracks on a polyimide foil. The required Sn is either deposited on the bump or on the Cu tracks. Both Au-Sn soldering processes are performed by using pulsed heat thermode (gang) bonding. It is found that the quality of the bonds depends on the microstructure formed in the bonding region. EDX measurements indicate that for good quality bonds eutectic (80/20) Au-Sn or /spl zeta/'phases are required. To obtain these phases the temperature at the interface and the initial amount of Sn are optimized.<>
{"title":"Reliable Au-Sn flip chip bonding on flexible prints","authors":"A.F.J. Baggerman, M.J. Batenburg","doi":"10.1109/ECTC.1994.367522","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367522","url":null,"abstract":"Au-Sn flip chip bonding is successfully introduced for the mounting of integrated circuits on flexible polyimide prints. Flip chip was used, since in most consumer electronics, and more specific for hearing instruments the useable volume is decreasing very rapidly. Since on the same flex print reflow soldering of other components is required, a high melting soldering process is preferred. An additional advantage of the Au-Sn process is that the bumps do not completely melt, and a certain stand off height is guaranteed. The bumps are deposited on top of the bondpads and are bonded to Cu tracks on a polyimide foil. The required Sn is either deposited on the bump or on the Cu tracks. Both Au-Sn soldering processes are performed by using pulsed heat thermode (gang) bonding. It is found that the quality of the bonds depends on the microstructure formed in the bonding region. EDX measurements indicate that for good quality bonds eutectic (80/20) Au-Sn or /spl zeta/'phases are required. To obtain these phases the temperature at the interface and the initial amount of Sn are optimized.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130704500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367611
S. Vesudevan, A. Shaikh
One of the major advantages of low temperature cofired ceramic (LTCC) technology is the ability to integrate passive components such as resistors, capacitors and inductors into a monolithic package. Due to materials interaction during processing, it is challenging to develop cofirable resistor, capacitor and inductor materials. This paper describes the development of compatible thick film resistors for Ferro's A6 tape system. The shrinkage behavior of the thick film resistors was matched to that of the tape material during firing. This shrinkage matching resulted in a distortion-free fired LTCC package with buried resistors. The resistor formulations were developed with sheet resistance in decade values starting from 10 /spl Omega///spl square/ up to 100 K/spl Omega///spl square/. The electrical properties of the resistors such as sheet resistance, TCR values, ESD stability and voltage handling were studied and found to be good. The microstructure development of the resistor during firing was studied using the scanning electron microscope (SEM). The electrical properties of the buried resistors such as sheet resistance, TCR, drift on ESD, and voltage handling capacity were studied for different buried levels of the resistor from the surface. The effect of firing time and temperatures and package design on the electrical properties of the resistors at different layers was also studied.<>
{"title":"Shrinkage matched cofireable thick film resistors for LTCC","authors":"S. Vesudevan, A. Shaikh","doi":"10.1109/ECTC.1994.367611","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367611","url":null,"abstract":"One of the major advantages of low temperature cofired ceramic (LTCC) technology is the ability to integrate passive components such as resistors, capacitors and inductors into a monolithic package. Due to materials interaction during processing, it is challenging to develop cofirable resistor, capacitor and inductor materials. This paper describes the development of compatible thick film resistors for Ferro's A6 tape system. The shrinkage behavior of the thick film resistors was matched to that of the tape material during firing. This shrinkage matching resulted in a distortion-free fired LTCC package with buried resistors. The resistor formulations were developed with sheet resistance in decade values starting from 10 /spl Omega///spl square/ up to 100 K/spl Omega///spl square/. The electrical properties of the resistors such as sheet resistance, TCR values, ESD stability and voltage handling were studied and found to be good. The microstructure development of the resistor during firing was studied using the scanning electron microscope (SEM). The electrical properties of the buried resistors such as sheet resistance, TCR, drift on ESD, and voltage handling capacity were studied for different buried levels of the resistor from the surface. The effect of firing time and temperatures and package design on the electrical properties of the resistors at different layers was also studied.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134013212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367501
D.E. Pachucki
Sun Microsystems has strived to be a leader in the workstation market. To maintain and advance in this leadership role, manufacturing process improvements which increase productivity, decrease test process time, and improve customer satisfaction are being pursued. The application of environmental stress screening is a method of achieving these improvements This experiment identifies the significance or relevancy of the selected stress screens for application in the PWA production process by using a statistically significant controlled method. The design of experiments statistical approach (analysis of variance), is applied, combined with the Taguchi two-level, seven-factor design method. This experiment concentrated on three stresses, (temperature cycling, random vibration, power cycling) and two diagnostic levels (a prom- based power-on self test-POST, and a functional test suite-Sundiag). Note that this is not an optimization experiment. Once the significance to the production process is identified, future optimizing of temperature cycling, power cycling, and vibration screens will be conducted. Also, voltage margining is not included so as to reduce the complexity of the experiment-treatment factors and interactions.<>
Sun Microsystems一直努力成为工作站市场的领导者。为了保持和推进这一领导角色，制造过程的改进提高了生产率，减少了测试过程时间，并提高了客户满意度。环境应力筛选的应用是实现这些改进的一种方法。该实验通过使用统计显著的控制方法来确定所选应力筛选在PWA生产过程中应用的重要性或相关性。实验设计采用统计学方法(方差分析)，结合田口二水平七因素设计方法。本实验集中在三个应力(温度循环、随机振动、功率循环)和两个诊断水平(基于prom的上电自检post和功能测试套件sundiag)。注意，这不是一个优化实验。一旦确定了对生产过程的意义，将对温度循环、功率循环和振动筛进行进一步的优化。此外，电压裕度不包括在内，以减少实验处理因素和相互作用的复杂性。
{"title":"Environmental stress screening experiment using the Taguchi method","authors":"D.E. Pachucki","doi":"10.1109/ECTC.1994.367501","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367501","url":null,"abstract":"Sun Microsystems has strived to be a leader in the workstation market. To maintain and advance in this leadership role, manufacturing process improvements which increase productivity, decrease test process time, and improve customer satisfaction are being pursued. The application of environmental stress screening is a method of achieving these improvements This experiment identifies the significance or relevancy of the selected stress screens for application in the PWA production process by using a statistically significant controlled method. The design of experiments statistical approach (analysis of variance), is applied, combined with the Taguchi two-level, seven-factor design method. This experiment concentrated on three stresses, (temperature cycling, random vibration, power cycling) and two diagnostic levels (a prom- based power-on self test-POST, and a functional test suite-Sundiag). Note that this is not an optimization experiment. Once the significance to the production process is identified, future optimizing of temperature cycling, power cycling, and vibration screens will be conducted. Also, voltage margining is not included so as to reduce the complexity of the experiment-treatment factors and interactions.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132970720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367660
K. DeHaven, J. Dietz
Much of the technical information presented herein has been published by either IBM or Motorola This paper provides a higher-level view of the benefits, considerations and leverage applications of the C4 and DCA technologies. A key to acceptance and use of a new or different technology is its application in successful products. Although C4 is not new and has-been utilized extensively by IBM, it is different to Motorola. DCA is a relatively new technology and, thus, has a shorter history. As a foundation, this paper discusses the key C4 and DCA technical features and describes some initial product applications at Motorola. This linkage shows the enabling characteristics of the C4 flip-chip technology. Finally, future trends and directions of C4 and DCA technologies are discussed.<>
{"title":"Controlled collapse chip connection (C4)-an enabling technology","authors":"K. DeHaven, J. Dietz","doi":"10.1109/ECTC.1994.367660","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367660","url":null,"abstract":"Much of the technical information presented herein has been published by either IBM or Motorola This paper provides a higher-level view of the benefits, considerations and leverage applications of the C4 and DCA technologies. A key to acceptance and use of a new or different technology is its application in successful products. Although C4 is not new and has-been utilized extensively by IBM, it is different to Motorola. DCA is a relatively new technology and, thus, has a shorter history. As a foundation, this paper discusses the key C4 and DCA technical features and describes some initial product applications at Motorola. This linkage shows the enabling characteristics of the C4 flip-chip technology. Finally, future trends and directions of C4 and DCA technologies are discussed.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131100005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367548
J. Clech, D. Noctor, J. C. Manock, G.W. Lynott, F.E. Baders
This paper documents improved practices to analyze Surface Mount (SM) attachment failure statistics. These include the use of a failure free time metric obtained from three parameter Weibull analysis of solder joint fatigue data. Compared to two parameter Weibull and lognormal distributions, the three parameter Weibull consistently gives a better fit of early wear out failures across a large test database. The failure free time represents the minimum amount of time required for cracks to initiate and propagate through the weakest solder joints of a population. The failure free metric defines a warranty period during which thermo-mechanical fatigue failures of solder joints are not expected. The Comprehensive Surface Mount Reliability (CSMR) model has been extended by correlating failure free times scaled for the solder crack area to cyclic inelastic strain energy. The three parameter Weibull treatment of SM failure data provides more accurate reliability projections, potentially qualifying component assemblies that would be rated marginal or unacceptable based on more conservative two parameter Weibull or log-normal analysis.<>
{"title":"Surface mount assembly failure statistics and failure free time","authors":"J. Clech, D. Noctor, J. C. Manock, G.W. Lynott, F.E. Baders","doi":"10.1109/ECTC.1994.367548","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367548","url":null,"abstract":"This paper documents improved practices to analyze Surface Mount (SM) attachment failure statistics. These include the use of a failure free time metric obtained from three parameter Weibull analysis of solder joint fatigue data. Compared to two parameter Weibull and lognormal distributions, the three parameter Weibull consistently gives a better fit of early wear out failures across a large test database. The failure free time represents the minimum amount of time required for cracks to initiate and propagate through the weakest solder joints of a population. The failure free metric defines a warranty period during which thermo-mechanical fatigue failures of solder joints are not expected. The Comprehensive Surface Mount Reliability (CSMR) model has been extended by correlating failure free times scaled for the solder crack area to cyclic inelastic strain energy. The three parameter Weibull treatment of SM failure data provides more accurate reliability projections, potentially qualifying component assemblies that would be rated marginal or unacceptable based on more conservative two parameter Weibull or log-normal analysis.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132032713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367498
J. Suhling, R. A. Cordes, Y. Kang, R. Jaeger
Piezoresistive sensors are a powerful tool for measurement of surface stress states in semiconductor die used within electronic packages. A new wafer-level method for calibrating on-chip piezoresistive stress sensors is presented, in which an entire circular silicon wafer (potentially containing hundreds of fabricated stress sensing chips) is supported on its edge as a simply supported plate and loaded using a uniform pressure. Resistors across the surface of the wafer can then be probed using a standard automated probe station with computer-controlled positioners. The capabilities and limitations of the method have been established and discussed. A typical calibration procedure and the theory needed to determine the piezoresistive coefficients from the raw experimental data have been presented. Finally, the new method has been applied in the laboratory to extract the coefficient /spl pi//sub 44/ of p-type silicon.<>
{"title":"Wafer-level calibration of stress sensing test chips","authors":"J. Suhling, R. A. Cordes, Y. Kang, R. Jaeger","doi":"10.1109/ECTC.1994.367498","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367498","url":null,"abstract":"Piezoresistive sensors are a powerful tool for measurement of surface stress states in semiconductor die used within electronic packages. A new wafer-level method for calibrating on-chip piezoresistive stress sensors is presented, in which an entire circular silicon wafer (potentially containing hundreds of fabricated stress sensing chips) is supported on its edge as a simply supported plate and loaded using a uniform pressure. Resistors across the surface of the wafer can then be probed using a standard automated probe station with computer-controlled positioners. The capabilities and limitations of the method have been established and discussed. A typical calibration procedure and the theory needed to determine the piezoresistive coefficients from the raw experimental data have been presented. Finally, the new method has been applied in the laboratory to extract the coefficient /spl pi//sub 44/ of p-type silicon.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130153126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367581
Y. Tsubomatsu, Y. Yoshidomi, H. Ohhata, T. Yamazaki, N. Fukutomi
The transfer laminate circuit (TLC) process is presented which has a vast potential for extending the wiring density of laminated multichip modules (MCM-Ls) to a level of deposited MCMs (MCM-Ds). In this paper, factors affecting the resolution of wiring patterns produced by TLC process are studied and a feasibility of making fine pitch wiring patterns is demonstrated.<>
{"title":"Transfer laminate circuit process for fine pitch wiring technology","authors":"Y. Tsubomatsu, Y. Yoshidomi, H. Ohhata, T. Yamazaki, N. Fukutomi","doi":"10.1109/ECTC.1994.367581","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367581","url":null,"abstract":"The transfer laminate circuit (TLC) process is presented which has a vast potential for extending the wiring density of laminated multichip modules (MCM-Ls) to a level of deposited MCMs (MCM-Ds). In this paper, factors affecting the resolution of wiring patterns produced by TLC process are studied and a feasibility of making fine pitch wiring patterns is demonstrated.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116246596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367626
J. Galvagni, S. Randall, P. Roughan, A. Templeton
High di/dt ratios, large current pulses over short times, are an inevitable part of today's fast electronic circuitry. Though desirable in themselves, they can cause high voltage spikes when pulled through paths that have inductance. The task of the designer then is to have high energies available, but not the associated voltage excursions, by reducing the total inductance. Eliminating wire bonds, reducing path lengths, and using low inductance components is the regimen. This paper describes the availability of capacitors that can go a long way to providing the energies needed, but simultaneously, lower the intrinsic inductance if contributes. We will review the source of the inductance, the current components available, and other advances that will give the designer a more useful menu.<>
{"title":"So many electrons, so little time [Low Inductance Capacitor Arrays]","authors":"J. Galvagni, S. Randall, P. Roughan, A. Templeton","doi":"10.1109/ECTC.1994.367626","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367626","url":null,"abstract":"High di/dt ratios, large current pulses over short times, are an inevitable part of today's fast electronic circuitry. Though desirable in themselves, they can cause high voltage spikes when pulled through paths that have inductance. The task of the designer then is to have high energies available, but not the associated voltage excursions, by reducing the total inductance. Eliminating wire bonds, reducing path lengths, and using low inductance components is the regimen. This paper describes the availability of capacitors that can go a long way to providing the energies needed, but simultaneously, lower the intrinsic inductance if contributes. We will review the source of the inductance, the current components available, and other advances that will give the designer a more useful menu.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114783902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367492
B. Carpenter, K. Pearsall, R. Raines
Water soluble fluxes and pastes contain a high percentage of free acids that increase the activation level and subsequently enhance solderability, but do not contain resins. A method was developed that can be used to predict the printability of a water soluble solder paste. Since a solder paste shear thins and exhibits a yield point during actual printing (paste flow) these two parameters were measured and then correlated to the resultant paste print performance on more than 40 different lots of paste. The measurement techniques used for the in-depth rheological characterization as well as the viscometers employed are discussed in detail.<>
{"title":"Predicting printability of WSPs through rheological characterization","authors":"B. Carpenter, K. Pearsall, R. Raines","doi":"10.1109/ECTC.1994.367492","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367492","url":null,"abstract":"Water soluble fluxes and pastes contain a high percentage of free acids that increase the activation level and subsequently enhance solderability, but do not contain resins. A method was developed that can be used to predict the printability of a water soluble solder paste. Since a solder paste shear thins and exhibits a yield point during actual printing (paste flow) these two parameters were measured and then correlated to the resultant paste print performance on more than 40 different lots of paste. The measurement techniques used for the in-depth rheological characterization as well as the viscometers employed are discussed in detail.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128410481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367633
G. Lewis, G. Ganesan, H. Berg
Cracking of surface mounted plastic packages worsens with increasing die sizes and thinner packages, both are recent trends in packaging. The precursor to failure, delamination at a leadframe to polymer interface, suggests that improvements in mold compounds, die attach adhesives and leadframe surface finishes are key elements in a solution. Identifying which specific materials properties must be improved and to what degree is a major task, followed by working with vendors to supply improved materials. In this study, the strategy is to improve all weak interfaces in parallel, rather than simply strengthen the weakest link. An excellent measurement method capable of detecting small improvements in the measured reflow soldering performance of a test package (148 PQFP) quantified both its delamination and cracking performance. These studies identified a general weakness in polymer to Ag die pad interfaces, implying that improving the adherend is mandatory.<>
{"title":"Role of materials evolution in VLSI plastic packages in improving reflow soldering performance","authors":"G. Lewis, G. Ganesan, H. Berg","doi":"10.1109/ECTC.1994.367633","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367633","url":null,"abstract":"Cracking of surface mounted plastic packages worsens with increasing die sizes and thinner packages, both are recent trends in packaging. The precursor to failure, delamination at a leadframe to polymer interface, suggests that improvements in mold compounds, die attach adhesives and leadframe surface finishes are key elements in a solution. Identifying which specific materials properties must be improved and to what degree is a major task, followed by working with vendors to supply improved materials. In this study, the strategy is to improve all weak interfaces in parallel, rather than simply strengthen the weakest link. An excellent measurement method capable of detecting small improvements in the measured reflow soldering performance of a test package (148 PQFP) quantified both its delamination and cracking performance. These studies identified a general weakness in polymer to Ag die pad interfaces, implying that improving the adherend is mandatory.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132732903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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