Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367598
F.J. Cericola, B. K. Bhattacharyya
In this paper, a theoretical method is described for the optimization of a CMOS driven, center tap terminated network. This method is verified by circuit simulations. In the simulations, we have assumed a 70 ohm characteristic impedance of the board interconnects and at the same time, n number of various loads connected at different points on that line. Each of these loads has some stub length that can vary from 1.0 inch to 1.5 inch depending on the packaging technology. The above example is a shared bus situation. This method will also work on other topologies as long as the effective characteristic impedance of that topology is less than Zmin, where Zmin is the minimum characteristic impedance that the CMOS driver can support for a given noise criteria.<>
{"title":"A method for the optimization of a CMOS driven, center tap terminated (CTT) network in a shared bus design","authors":"F.J. Cericola, B. K. Bhattacharyya","doi":"10.1109/ECTC.1994.367598","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367598","url":null,"abstract":"In this paper, a theoretical method is described for the optimization of a CMOS driven, center tap terminated network. This method is verified by circuit simulations. In the simulations, we have assumed a 70 ohm characteristic impedance of the board interconnects and at the same time, n number of various loads connected at different points on that line. Each of these loads has some stub length that can vary from 1.0 inch to 1.5 inch depending on the packaging technology. The above example is a shared bus situation. This method will also work on other topologies as long as the effective characteristic impedance of that topology is less than Zmin, where Zmin is the minimum characteristic impedance that the CMOS driver can support for a given noise criteria.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"41 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116729646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367537
C. S. Chang, A. Agrawal
The rough surface of the copper foil, introduced to enhance its interfacial adhesion to the dielectric medium, will increase the signal propagation time constant and reduce the characteristic impedance. A high resolution resonant measurement technique will be presented for such study. The internal inductance will increase both the propagation time constant and the characteristic impedance. It adds an additional delay term, proportional to the square root of the signal rise time in the transient measurement. We will compare the results of different measurement techniques in this paper.<>
{"title":"Fine line thin dielectric circuit board characterization","authors":"C. S. Chang, A. Agrawal","doi":"10.1109/ECTC.1994.367537","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367537","url":null,"abstract":"The rough surface of the copper foil, introduced to enhance its interfacial adhesion to the dielectric medium, will increase the signal propagation time constant and reduce the characteristic impedance. A high resolution resonant measurement technique will be presented for such study. The internal inductance will increase both the propagation time constant and the characteristic impedance. It adds an additional delay term, proportional to the square root of the signal rise time in the transient measurement. We will compare the results of different measurement techniques in this paper.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115436985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367551
J. Suhling, R.W. Johnson, J. White, K.W. Matthai, R. Knight, C. S. Romanczuk, S.W. Burcham
For enhanced heat transfer, insulated metal substrates are attractive alternatives to the FR-4 printed circuit boards which have been conventionally used in automotive engine controllers. Although appealing from the viewpoint of enhanced thermal performance, the high coefficient of thermal expansion of aluminum relative that of FR-4 boards leads to a increased probability of fatigue failures of surface mount solder connections subjected to thermal cycling. In this work, the thermal fatigue life and reliability of solder joints used to attach components to insulated metal substrates has been studied using finite element modeling and actual life testing. In particular, this investigation has examined the reliability of solder connections for ceramic chip resistors and chip capacitors. Several two-dimensional (plane stress and plane strain) and three-dimensional nonlinear finite element models have been prepared and executed for both chip resistors and chip capacitors on insulated metal substrates. Several common sizes of the resistors/capacitors have been modeled including 1206, 0805, 0603, and 0402. Attributes of the finite element models included elastic-plastic solder constitutive behavior, large deformations, and thermal cycling. Initiation of solder joint fatigue cracking was estimated using the predicted plastic strains within a Coffin-Manson type fatigue model. The fatigue life predictions of the finite element analyses have been correlated with solder joint crack initiation and life measurements for actual components under thermal cycling. A broad matrix of test configurations with various substrate materials, resistor/capacitor sizes, and encapsulants has been considered.<>
{"title":"Solder joint reliability of surface mount chip resistors/capacitors on insulated metal substrates","authors":"J. Suhling, R.W. Johnson, J. White, K.W. Matthai, R. Knight, C. S. Romanczuk, S.W. Burcham","doi":"10.1109/ECTC.1994.367551","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367551","url":null,"abstract":"For enhanced heat transfer, insulated metal substrates are attractive alternatives to the FR-4 printed circuit boards which have been conventionally used in automotive engine controllers. Although appealing from the viewpoint of enhanced thermal performance, the high coefficient of thermal expansion of aluminum relative that of FR-4 boards leads to a increased probability of fatigue failures of surface mount solder connections subjected to thermal cycling. In this work, the thermal fatigue life and reliability of solder joints used to attach components to insulated metal substrates has been studied using finite element modeling and actual life testing. In particular, this investigation has examined the reliability of solder connections for ceramic chip resistors and chip capacitors. Several two-dimensional (plane stress and plane strain) and three-dimensional nonlinear finite element models have been prepared and executed for both chip resistors and chip capacitors on insulated metal substrates. Several common sizes of the resistors/capacitors have been modeled including 1206, 0805, 0603, and 0402. Attributes of the finite element models included elastic-plastic solder constitutive behavior, large deformations, and thermal cycling. Initiation of solder joint fatigue cracking was estimated using the predicted plastic strains within a Coffin-Manson type fatigue model. The fatigue life predictions of the finite element analyses have been correlated with solder joint crack initiation and life measurements for actual components under thermal cycling. A broad matrix of test configurations with various substrate materials, resistor/capacitor sizes, and encapsulants has been considered.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121188887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367623
P. Tsao, Arkady S. Voloshin
Manufacturing of the electronic packages consisting of different materials leads to the development of the residual stresses due to mismatch in the coefficients of thermal expansion. Thus, to properly assess service life of the packages, those stresses must be taken into account. An experimental technique, the digital image analysis enhanced moire interferometry ( DIAEMI), was used to measure the in-situ out-of-plane displacements of the die due to the die-attach process. This information was related to the residual stresses in the die. Several test dies, with and without coating, were prepared and two different bonding materials, "low-stress" and "high-stress", were used for analysis of the induced stresses. The initial and final (after die-attach) surface contour patterns of the dies were observed and recorded. Out-of-plane displacements of the dies were obtained and induced stresses were calculated by a hybrid finite element method. The results show that stresses in die induced by high-stress bonding material are on average five times higher than the stresses induced by low-stress material. It was also found that during die-attach some of residual stresses induced by chip's coating were released. The obtained results were compared with the straight forward finite element method prediction. It shows that the stresses predicted by the straight forward finite element analysis are much higher than the stresses obtained by the hybrid method.<>
{"title":"Manufacturing stresses in die due to die attach process","authors":"P. Tsao, Arkady S. Voloshin","doi":"10.1109/ECTC.1994.367623","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367623","url":null,"abstract":"Manufacturing of the electronic packages consisting of different materials leads to the development of the residual stresses due to mismatch in the coefficients of thermal expansion. Thus, to properly assess service life of the packages, those stresses must be taken into account. An experimental technique, the digital image analysis enhanced moire interferometry ( DIAEMI), was used to measure the in-situ out-of-plane displacements of the die due to the die-attach process. This information was related to the residual stresses in the die. Several test dies, with and without coating, were prepared and two different bonding materials, \"low-stress\" and \"high-stress\", were used for analysis of the induced stresses. The initial and final (after die-attach) surface contour patterns of the dies were observed and recorded. Out-of-plane displacements of the dies were obtained and induced stresses were calculated by a hybrid finite element method. The results show that stresses in die induced by high-stress bonding material are on average five times higher than the stresses induced by low-stress material. It was also found that during die-attach some of residual stresses induced by chip's coating were released. The obtained results were compared with the straight forward finite element method prediction. It shows that the stresses predicted by the straight forward finite element analysis are much higher than the stresses obtained by the hybrid method.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121569197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367651
P. Hoffman, D. Liang, D. Mahulikar, A. Parthasarathi
A TQFP (Thin Quad Flat Pack) package has been developed that has very superior electrical and thermal performance when compared to a plastic molded TQFP package. The high performance TQFP is based on Olin's MQUAD technology; a packaging scheme where the plastic mold compound is replaced by an anodized aluminum base and lid adhesively sealed to the leadframe. The package uses the same IR or VPR board mounting profile as a plastic package, weighs the same as a plastic package, and is dimensionally equivalent to a plastic package.<>
{"title":"Development of a high performance TQFP package","authors":"P. Hoffman, D. Liang, D. Mahulikar, A. Parthasarathi","doi":"10.1109/ECTC.1994.367651","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367651","url":null,"abstract":"A TQFP (Thin Quad Flat Pack) package has been developed that has very superior electrical and thermal performance when compared to a plastic molded TQFP package. The high performance TQFP is based on Olin's MQUAD technology; a packaging scheme where the plastic mold compound is replaced by an anodized aluminum base and lid adhesively sealed to the leadframe. The package uses the same IR or VPR board mounting profile as a plastic package, weighs the same as a plastic package, and is dimensionally equivalent to a plastic package.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122073808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367648
L. Cao, J. Krusius
Packaging is one of the primary constraints on the performance and partitioning of high density electronic systems. A concurrent design methodology for the design of the physical structure of such systems is presented here. Architecture, electrical, performance and energy management aspects are included. The CAD tool AUDiT implements this design methodology. The concurrent design capability has been illustrated using a model system derived from the high speed Digital Equipment 3000/500 (Alpha) engineering workstation.<>
{"title":"Concurrent packaging architecture design","authors":"L. Cao, J. Krusius","doi":"10.1109/ECTC.1994.367648","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367648","url":null,"abstract":"Packaging is one of the primary constraints on the performance and partitioning of high density electronic systems. A concurrent design methodology for the design of the physical structure of such systems is presented here. Architecture, electrical, performance and energy management aspects are included. The CAD tool AUDiT implements this design methodology. The concurrent design capability has been illustrated using a model system derived from the high speed Digital Equipment 3000/500 (Alpha) engineering workstation.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128664415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367595
N. Gasparini, B. Bhattacharyya
In this paper we are going to show a method of defining a group of C4 bumps that can be placed in a repeated manner on silicon die. It is also shown that for a given package design guideline all these bumps can be routed in a given package layer. This method also allows one to route a maximum number of C4 bumps for a given number of package layers. These groups of bumps can be placed along the die edge, along the diagonals of the die, or both. This method is also verified by extensive experimental drawings on various die sizes, as well as for various package design guidelines. It is shown that this method takes the minimum distance from the die edge for the placement of the maximum number of bumps for a given package routing layer. If the numbers of I/Os are reasonable compared to the die size, then this design methodology can help one design a set of bond pads in the die that can be utilized both for C4 and for wire bond technology.<>
{"title":"A method of designing a group of bumps for C4 packages to maximize the number of bumps and minimize the number of package layers","authors":"N. Gasparini, B. Bhattacharyya","doi":"10.1109/ECTC.1994.367595","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367595","url":null,"abstract":"In this paper we are going to show a method of defining a group of C4 bumps that can be placed in a repeated manner on silicon die. It is also shown that for a given package design guideline all these bumps can be routed in a given package layer. This method also allows one to route a maximum number of C4 bumps for a given number of package layers. These groups of bumps can be placed along the die edge, along the diagonals of the die, or both. This method is also verified by extensive experimental drawings on various die sizes, as well as for various package design guidelines. It is shown that this method takes the minimum distance from the die edge for the placement of the maximum number of bumps for a given package routing layer. If the numbers of I/Os are reasonable compared to the die size, then this design methodology can help one design a set of bond pads in the die that can be utilized both for C4 and for wire bond technology.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123181722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367617
T. Carden, J. Clementi, S. Engle
The Ceramic Quad Flat Pack (CQFP) is a high performance, low cost technology for surface mount applications. It is an extension of the Metallized Ceramic (MC) and Metallized Ceramic with Polyimide (MCP) product base. These finished modules conform to JEDEC I/O and footprint standards. The packages are available in 0.5 mm and 0.4 mm lead pitches with flexibility to address unique application requirements such as body sizes or lead counts/pitches. Semiconductor die interconnection is performed using either flip chip (C4-Controlled Collapse Chip Connection) attach or wirebonding. Excellent package reliability with no intrinsic wear out failure mechanism results by encapsulating solder joints from the silicon C4 die and peripheral lead to ceramic carrier. IBM evaluated several encapsulant configurations, and tested over 2000 encapsulated carriers and 897000 individual solder joints during development and qualification. Epoxy encapsulation of solder joint connections on CQFP's has been successfully implemented in production across several IBM manufacturing sites. This enhancement eliminates any intrinsic failure mechanism associated with fatigue wear out. It is a significant extension of a low cost and high reliability product technology.<>
{"title":"Epoxy encapsulation on Ceramic Quad Flat Packs","authors":"T. Carden, J. Clementi, S. Engle","doi":"10.1109/ECTC.1994.367617","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367617","url":null,"abstract":"The Ceramic Quad Flat Pack (CQFP) is a high performance, low cost technology for surface mount applications. It is an extension of the Metallized Ceramic (MC) and Metallized Ceramic with Polyimide (MCP) product base. These finished modules conform to JEDEC I/O and footprint standards. The packages are available in 0.5 mm and 0.4 mm lead pitches with flexibility to address unique application requirements such as body sizes or lead counts/pitches. Semiconductor die interconnection is performed using either flip chip (C4-Controlled Collapse Chip Connection) attach or wirebonding. Excellent package reliability with no intrinsic wear out failure mechanism results by encapsulating solder joints from the silicon C4 die and peripheral lead to ceramic carrier. IBM evaluated several encapsulant configurations, and tested over 2000 encapsulated carriers and 897000 individual solder joints during development and qualification. Epoxy encapsulation of solder joint connections on CQFP's has been successfully implemented in production across several IBM manufacturing sites. This enhancement eliminates any intrinsic failure mechanism associated with fatigue wear out. It is a significant extension of a low cost and high reliability product technology.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127064636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367588
R. Pantaleón, J. Sánchez-Mendoza, M. Mena
Bond shear testing is becoming an indispensable tool for wirebonder machine set-up and bonding process monitoring. The lower acceptable limits, however, are defined based on historical data. This paper establishes the theoretical and statistical correlation between bond size, wire grain size, strain hardening and ultimate tensile strengths of the gold wire in relation to the Mode 1 (through the gold ball) shear strengths. Results of the study showed that the ball shear strength is strongly correlated with the bond aspect ratio which is the ratio of the ball diameter to the bond height. This parameter is easily obtainable from an automated vision inspection system and could provide initial information on the quality of the bond. The study also showed that the gold ball undergoes strain or work hardening during bonding. Bond shear strengths predicted from this work hardening conforms well with the actual data.<>
{"title":"Rationalization of gold ball bond shear strengths","authors":"R. Pantaleón, J. Sánchez-Mendoza, M. Mena","doi":"10.1109/ECTC.1994.367588","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367588","url":null,"abstract":"Bond shear testing is becoming an indispensable tool for wirebonder machine set-up and bonding process monitoring. The lower acceptable limits, however, are defined based on historical data. This paper establishes the theoretical and statistical correlation between bond size, wire grain size, strain hardening and ultimate tensile strengths of the gold wire in relation to the Mode 1 (through the gold ball) shear strengths. Results of the study showed that the ball shear strength is strongly correlated with the bond aspect ratio which is the ratio of the ball diameter to the bond height. This parameter is easily obtainable from an automated vision inspection system and could provide initial information on the quality of the bond. The study also showed that the gold ball undergoes strain or work hardening during bonding. Bond shear strengths predicted from this work hardening conforms well with the actual data.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126743681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367544
T. Momose, H. Yagi, S. Kawano, T. Ikenaga, Y. Nishikubo
On high performance package like Quad Flat Package (QFP), lead skew of the outer lead exists in its asymmetrical cross-section. For fine pitch lead frame with the range of 0.3-0.5 mm pitch, the cross-section of outer lead seems to accelerate the skew. The skew value depends on the mismatch of top and bottom patterns of photo-imaging process. Reduction of lead width caused by fine pitch, enhances this asymmetry. The results of the experiment and simulation suggest the following mechanism. In the products with the asymmetrical cross-section of outer lead, the mismatch from top to bottom surface forms the geometric moment of inertia. The moment that is rotational brings about the lead skew at bending which is outer lead forming process. The lead skew of outer lead is determined with the computer simulation by FEM and the allowable cross-section of outer lead is obtained. The cross-section that is from right to left and top to bottom, doesn't contribute any lead skew. A shorter width at the top than the bottom makes the skew value smaller. This guides the design of upside-down chip package.<>
{"title":"The effect of the cross-section of outlead on lead skew","authors":"T. Momose, H. Yagi, S. Kawano, T. Ikenaga, Y. Nishikubo","doi":"10.1109/ECTC.1994.367544","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367544","url":null,"abstract":"On high performance package like Quad Flat Package (QFP), lead skew of the outer lead exists in its asymmetrical cross-section. For fine pitch lead frame with the range of 0.3-0.5 mm pitch, the cross-section of outer lead seems to accelerate the skew. The skew value depends on the mismatch of top and bottom patterns of photo-imaging process. Reduction of lead width caused by fine pitch, enhances this asymmetry. The results of the experiment and simulation suggest the following mechanism. In the products with the asymmetrical cross-section of outer lead, the mismatch from top to bottom surface forms the geometric moment of inertia. The moment that is rotational brings about the lead skew at bending which is outer lead forming process. The lead skew of outer lead is determined with the computer simulation by FEM and the allowable cross-section of outer lead is obtained. The cross-section that is from right to left and top to bottom, doesn't contribute any lead skew. A shorter width at the top than the bottom makes the skew value smaller. This guides the design of upside-down chip package.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122550877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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