Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367630
M. Tencer
In this paper the rate of moisture ingress into enclosures was studied theoretically and experimentally. A simple quasi-steady state (QSS) model was developed enabling one to calculate easily time constants for moisture diffusion through plastic walls, rubber gaskets and openings. The characteristic time constant is /spl tau/=VL/AP+L/sup 2//2D where P is permeability, D diffusion constant, V volume of the enclosure, L wall thickness and A surface area. The model clarifies the relative importance of moisture permeability vs. diffusion constant of wall materials and is applicable to both large enclosures and microelectronic packages. For thin and/or nonabsorbing walls the first term (a function of P) predominates while with thick and/or absorbing walls the second term (which depends on D) prevails. For openings, /spl tau/=VL/AD, it was shown that the QSS model is practically equivalent to but simpler than full transient solutions of the Fick's second law. The attenuation of variations of atmospheric humidity by packaging was also modeled with the QSS model. The inside air humidity changes with the same frequency as the ambient but its amplitude is attenuated by a factor f=cos /spl phi/=1/(1+/spl omega//sup 2//spl tau//sup 2/)/sup 1/2/ and is phase shifted by an angle /spl phi/=arccos [1/(1+/spl omega//sup 2//spl tau//sup 2/)/sup 1/2/] where /spl omega/ is the angular frequency of humidity changes. Therefore the protective value of packaging will be different in different geographical areas.<>
{"title":"Moisture ingress into nonhermetic enclosures and packages. A quasi-steady state model for diffusion and attenuation of ambient humidity variations","authors":"M. Tencer","doi":"10.1109/ECTC.1994.367630","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367630","url":null,"abstract":"In this paper the rate of moisture ingress into enclosures was studied theoretically and experimentally. A simple quasi-steady state (QSS) model was developed enabling one to calculate easily time constants for moisture diffusion through plastic walls, rubber gaskets and openings. The characteristic time constant is /spl tau/=VL/AP+L/sup 2//2D where P is permeability, D diffusion constant, V volume of the enclosure, L wall thickness and A surface area. The model clarifies the relative importance of moisture permeability vs. diffusion constant of wall materials and is applicable to both large enclosures and microelectronic packages. For thin and/or nonabsorbing walls the first term (a function of P) predominates while with thick and/or absorbing walls the second term (which depends on D) prevails. For openings, /spl tau/=VL/AD, it was shown that the QSS model is practically equivalent to but simpler than full transient solutions of the Fick's second law. The attenuation of variations of atmospheric humidity by packaging was also modeled with the QSS model. The inside air humidity changes with the same frequency as the ambient but its amplitude is attenuated by a factor f=cos /spl phi/=1/(1+/spl omega//sup 2//spl tau//sup 2/)/sup 1/2/ and is phase shifted by an angle /spl phi/=arccos [1/(1+/spl omega//sup 2//spl tau//sup 2/)/sup 1/2/] where /spl omega/ is the angular frequency of humidity changes. Therefore the protective value of packaging will be different in different geographical areas.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123001227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367651
P. Hoffman, D. Liang, D. Mahulikar, A. Parthasarathi
A TQFP (Thin Quad Flat Pack) package has been developed that has very superior electrical and thermal performance when compared to a plastic molded TQFP package. The high performance TQFP is based on Olin's MQUAD technology; a packaging scheme where the plastic mold compound is replaced by an anodized aluminum base and lid adhesively sealed to the leadframe. The package uses the same IR or VPR board mounting profile as a plastic package, weighs the same as a plastic package, and is dimensionally equivalent to a plastic package.<>
{"title":"Development of a high performance TQFP package","authors":"P. Hoffman, D. Liang, D. Mahulikar, A. Parthasarathi","doi":"10.1109/ECTC.1994.367651","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367651","url":null,"abstract":"A TQFP (Thin Quad Flat Pack) package has been developed that has very superior electrical and thermal performance when compared to a plastic molded TQFP package. The high performance TQFP is based on Olin's MQUAD technology; a packaging scheme where the plastic mold compound is replaced by an anodized aluminum base and lid adhesively sealed to the leadframe. The package uses the same IR or VPR board mounting profile as a plastic package, weighs the same as a plastic package, and is dimensionally equivalent to a plastic package.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122073808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367544
T. Momose, H. Yagi, S. Kawano, T. Ikenaga, Y. Nishikubo
On high performance package like Quad Flat Package (QFP), lead skew of the outer lead exists in its asymmetrical cross-section. For fine pitch lead frame with the range of 0.3-0.5 mm pitch, the cross-section of outer lead seems to accelerate the skew. The skew value depends on the mismatch of top and bottom patterns of photo-imaging process. Reduction of lead width caused by fine pitch, enhances this asymmetry. The results of the experiment and simulation suggest the following mechanism. In the products with the asymmetrical cross-section of outer lead, the mismatch from top to bottom surface forms the geometric moment of inertia. The moment that is rotational brings about the lead skew at bending which is outer lead forming process. The lead skew of outer lead is determined with the computer simulation by FEM and the allowable cross-section of outer lead is obtained. The cross-section that is from right to left and top to bottom, doesn't contribute any lead skew. A shorter width at the top than the bottom makes the skew value smaller. This guides the design of upside-down chip package.<>
{"title":"The effect of the cross-section of outlead on lead skew","authors":"T. Momose, H. Yagi, S. Kawano, T. Ikenaga, Y. Nishikubo","doi":"10.1109/ECTC.1994.367544","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367544","url":null,"abstract":"On high performance package like Quad Flat Package (QFP), lead skew of the outer lead exists in its asymmetrical cross-section. For fine pitch lead frame with the range of 0.3-0.5 mm pitch, the cross-section of outer lead seems to accelerate the skew. The skew value depends on the mismatch of top and bottom patterns of photo-imaging process. Reduction of lead width caused by fine pitch, enhances this asymmetry. The results of the experiment and simulation suggest the following mechanism. In the products with the asymmetrical cross-section of outer lead, the mismatch from top to bottom surface forms the geometric moment of inertia. The moment that is rotational brings about the lead skew at bending which is outer lead forming process. The lead skew of outer lead is determined with the computer simulation by FEM and the allowable cross-section of outer lead is obtained. The cross-section that is from right to left and top to bottom, doesn't contribute any lead skew. A shorter width at the top than the bottom makes the skew value smaller. This guides the design of upside-down chip package.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122550877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367648
L. Cao, J. Krusius
Packaging is one of the primary constraints on the performance and partitioning of high density electronic systems. A concurrent design methodology for the design of the physical structure of such systems is presented here. Architecture, electrical, performance and energy management aspects are included. The CAD tool AUDiT implements this design methodology. The concurrent design capability has been illustrated using a model system derived from the high speed Digital Equipment 3000/500 (Alpha) engineering workstation.<>
{"title":"Concurrent packaging architecture design","authors":"L. Cao, J. Krusius","doi":"10.1109/ECTC.1994.367648","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367648","url":null,"abstract":"Packaging is one of the primary constraints on the performance and partitioning of high density electronic systems. A concurrent design methodology for the design of the physical structure of such systems is presented here. Architecture, electrical, performance and energy management aspects are included. The CAD tool AUDiT implements this design methodology. The concurrent design capability has been illustrated using a model system derived from the high speed Digital Equipment 3000/500 (Alpha) engineering workstation.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128664415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367551
J. Suhling, R.W. Johnson, J. White, K.W. Matthai, R. Knight, C. S. Romanczuk, S.W. Burcham
For enhanced heat transfer, insulated metal substrates are attractive alternatives to the FR-4 printed circuit boards which have been conventionally used in automotive engine controllers. Although appealing from the viewpoint of enhanced thermal performance, the high coefficient of thermal expansion of aluminum relative that of FR-4 boards leads to a increased probability of fatigue failures of surface mount solder connections subjected to thermal cycling. In this work, the thermal fatigue life and reliability of solder joints used to attach components to insulated metal substrates has been studied using finite element modeling and actual life testing. In particular, this investigation has examined the reliability of solder connections for ceramic chip resistors and chip capacitors. Several two-dimensional (plane stress and plane strain) and three-dimensional nonlinear finite element models have been prepared and executed for both chip resistors and chip capacitors on insulated metal substrates. Several common sizes of the resistors/capacitors have been modeled including 1206, 0805, 0603, and 0402. Attributes of the finite element models included elastic-plastic solder constitutive behavior, large deformations, and thermal cycling. Initiation of solder joint fatigue cracking was estimated using the predicted plastic strains within a Coffin-Manson type fatigue model. The fatigue life predictions of the finite element analyses have been correlated with solder joint crack initiation and life measurements for actual components under thermal cycling. A broad matrix of test configurations with various substrate materials, resistor/capacitor sizes, and encapsulants has been considered.<>
{"title":"Solder joint reliability of surface mount chip resistors/capacitors on insulated metal substrates","authors":"J. Suhling, R.W. Johnson, J. White, K.W. Matthai, R. Knight, C. S. Romanczuk, S.W. Burcham","doi":"10.1109/ECTC.1994.367551","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367551","url":null,"abstract":"For enhanced heat transfer, insulated metal substrates are attractive alternatives to the FR-4 printed circuit boards which have been conventionally used in automotive engine controllers. Although appealing from the viewpoint of enhanced thermal performance, the high coefficient of thermal expansion of aluminum relative that of FR-4 boards leads to a increased probability of fatigue failures of surface mount solder connections subjected to thermal cycling. In this work, the thermal fatigue life and reliability of solder joints used to attach components to insulated metal substrates has been studied using finite element modeling and actual life testing. In particular, this investigation has examined the reliability of solder connections for ceramic chip resistors and chip capacitors. Several two-dimensional (plane stress and plane strain) and three-dimensional nonlinear finite element models have been prepared and executed for both chip resistors and chip capacitors on insulated metal substrates. Several common sizes of the resistors/capacitors have been modeled including 1206, 0805, 0603, and 0402. Attributes of the finite element models included elastic-plastic solder constitutive behavior, large deformations, and thermal cycling. Initiation of solder joint fatigue cracking was estimated using the predicted plastic strains within a Coffin-Manson type fatigue model. The fatigue life predictions of the finite element analyses have been correlated with solder joint crack initiation and life measurements for actual components under thermal cycling. A broad matrix of test configurations with various substrate materials, resistor/capacitor sizes, and encapsulants has been considered.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121188887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367617
T. Carden, J. Clementi, S. Engle
The Ceramic Quad Flat Pack (CQFP) is a high performance, low cost technology for surface mount applications. It is an extension of the Metallized Ceramic (MC) and Metallized Ceramic with Polyimide (MCP) product base. These finished modules conform to JEDEC I/O and footprint standards. The packages are available in 0.5 mm and 0.4 mm lead pitches with flexibility to address unique application requirements such as body sizes or lead counts/pitches. Semiconductor die interconnection is performed using either flip chip (C4-Controlled Collapse Chip Connection) attach or wirebonding. Excellent package reliability with no intrinsic wear out failure mechanism results by encapsulating solder joints from the silicon C4 die and peripheral lead to ceramic carrier. IBM evaluated several encapsulant configurations, and tested over 2000 encapsulated carriers and 897000 individual solder joints during development and qualification. Epoxy encapsulation of solder joint connections on CQFP's has been successfully implemented in production across several IBM manufacturing sites. This enhancement eliminates any intrinsic failure mechanism associated with fatigue wear out. It is a significant extension of a low cost and high reliability product technology.<>
{"title":"Epoxy encapsulation on Ceramic Quad Flat Packs","authors":"T. Carden, J. Clementi, S. Engle","doi":"10.1109/ECTC.1994.367617","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367617","url":null,"abstract":"The Ceramic Quad Flat Pack (CQFP) is a high performance, low cost technology for surface mount applications. It is an extension of the Metallized Ceramic (MC) and Metallized Ceramic with Polyimide (MCP) product base. These finished modules conform to JEDEC I/O and footprint standards. The packages are available in 0.5 mm and 0.4 mm lead pitches with flexibility to address unique application requirements such as body sizes or lead counts/pitches. Semiconductor die interconnection is performed using either flip chip (C4-Controlled Collapse Chip Connection) attach or wirebonding. Excellent package reliability with no intrinsic wear out failure mechanism results by encapsulating solder joints from the silicon C4 die and peripheral lead to ceramic carrier. IBM evaluated several encapsulant configurations, and tested over 2000 encapsulated carriers and 897000 individual solder joints during development and qualification. Epoxy encapsulation of solder joint connections on CQFP's has been successfully implemented in production across several IBM manufacturing sites. This enhancement eliminates any intrinsic failure mechanism associated with fatigue wear out. It is a significant extension of a low cost and high reliability product technology.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127064636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367576
E. Nhan, P.M. Lafferty, R. Stilwell, K. Chao
Radio-frequency systems employed in spacecraft and satellites require highly reliable interconnects and electronic components. Thus, systems designers must address and resolve issues such as the proper design and assembly process for connectors and interconnects. We have developed guidelines for the design of a space-qualifiable connector system, based on our experience with defective hybrid couplers and power dividers and an understanding of the material properties of the connector dielectric.<>
{"title":"Radio-frequency connector and interconnect reliability in spaceborne applications","authors":"E. Nhan, P.M. Lafferty, R. Stilwell, K. Chao","doi":"10.1109/ECTC.1994.367576","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367576","url":null,"abstract":"Radio-frequency systems employed in spacecraft and satellites require highly reliable interconnects and electronic components. Thus, systems designers must address and resolve issues such as the proper design and assembly process for connectors and interconnects. We have developed guidelines for the design of a space-qualifiable connector system, based on our experience with defective hybrid couplers and power dividers and an understanding of the material properties of the connector dielectric.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126727088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367588
R. Pantaleón, J. Sánchez-Mendoza, M. Mena
Bond shear testing is becoming an indispensable tool for wirebonder machine set-up and bonding process monitoring. The lower acceptable limits, however, are defined based on historical data. This paper establishes the theoretical and statistical correlation between bond size, wire grain size, strain hardening and ultimate tensile strengths of the gold wire in relation to the Mode 1 (through the gold ball) shear strengths. Results of the study showed that the ball shear strength is strongly correlated with the bond aspect ratio which is the ratio of the ball diameter to the bond height. This parameter is easily obtainable from an automated vision inspection system and could provide initial information on the quality of the bond. The study also showed that the gold ball undergoes strain or work hardening during bonding. Bond shear strengths predicted from this work hardening conforms well with the actual data.<>
{"title":"Rationalization of gold ball bond shear strengths","authors":"R. Pantaleón, J. Sánchez-Mendoza, M. Mena","doi":"10.1109/ECTC.1994.367588","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367588","url":null,"abstract":"Bond shear testing is becoming an indispensable tool for wirebonder machine set-up and bonding process monitoring. The lower acceptable limits, however, are defined based on historical data. This paper establishes the theoretical and statistical correlation between bond size, wire grain size, strain hardening and ultimate tensile strengths of the gold wire in relation to the Mode 1 (through the gold ball) shear strengths. Results of the study showed that the ball shear strength is strongly correlated with the bond aspect ratio which is the ratio of the ball diameter to the bond height. This parameter is easily obtainable from an automated vision inspection system and could provide initial information on the quality of the bond. The study also showed that the gold ball undergoes strain or work hardening during bonding. Bond shear strengths predicted from this work hardening conforms well with the actual data.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126743681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367587
R. Jaeger, J. Suhling, A. Anderson
A new piezoresistive stress sensing test chip for use on (100) silicon wafers is discussed. The die design contains four-element dual-polarity rosettes optimized for use in measurement of the in-plane normal stress difference (/spl sigma//sub 11//sup '/-/spl sigma//sub 22//sup '/) and the in-plane shear stress /spl sigma//sub 12//sup '/. The rosettes offer high sensitivity to stress since their outputs are proportional to the largest piezoresistive coefficients, /spl pi//sub 44/ in p-type silicon and /spl pi//sub D/ in the n-type silicon. The rosette outputs are both temperature compensated and insensitive to rotational alignment errors and are independent of the out-of-plane normal stress /spl sigma//sub 33/'. Thus, they may be used to measure the in-plane stress components in plastic encapsulated packages where /spl sigma//sub 33/' is not zero. Three-element off-axis p-type and n-type rosettes are also included on each chip for use in uniaxial calibration of the required piezoresistive coefficients. The properties of these rosettes are reviewed, and it is shown that the off-axis rosette yields temperature compensated calibration of the values of /spl pi//sub 44/ and /spl pi//sub D/.<>
{"title":"A [100] silicon stress test chip with optimized piezoresistive sensor rosettes","authors":"R. Jaeger, J. Suhling, A. Anderson","doi":"10.1109/ECTC.1994.367587","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367587","url":null,"abstract":"A new piezoresistive stress sensing test chip for use on (100) silicon wafers is discussed. The die design contains four-element dual-polarity rosettes optimized for use in measurement of the in-plane normal stress difference (/spl sigma//sub 11//sup '/-/spl sigma//sub 22//sup '/) and the in-plane shear stress /spl sigma//sub 12//sup '/. The rosettes offer high sensitivity to stress since their outputs are proportional to the largest piezoresistive coefficients, /spl pi//sub 44/ in p-type silicon and /spl pi//sub D/ in the n-type silicon. The rosette outputs are both temperature compensated and insensitive to rotational alignment errors and are independent of the out-of-plane normal stress /spl sigma//sub 33/'. Thus, they may be used to measure the in-plane stress components in plastic encapsulated packages where /spl sigma//sub 33/' is not zero. Three-element off-axis p-type and n-type rosettes are also included on each chip for use in uniaxial calibration of the required piezoresistive coefficients. The properties of these rosettes are reviewed, and it is shown that the off-axis rosette yields temperature compensated calibration of the values of /spl pi//sub 44/ and /spl pi//sub D/.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121459407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367623
P. Tsao, Arkady S. Voloshin
Manufacturing of the electronic packages consisting of different materials leads to the development of the residual stresses due to mismatch in the coefficients of thermal expansion. Thus, to properly assess service life of the packages, those stresses must be taken into account. An experimental technique, the digital image analysis enhanced moire interferometry ( DIAEMI), was used to measure the in-situ out-of-plane displacements of the die due to the die-attach process. This information was related to the residual stresses in the die. Several test dies, with and without coating, were prepared and two different bonding materials, "low-stress" and "high-stress", were used for analysis of the induced stresses. The initial and final (after die-attach) surface contour patterns of the dies were observed and recorded. Out-of-plane displacements of the dies were obtained and induced stresses were calculated by a hybrid finite element method. The results show that stresses in die induced by high-stress bonding material are on average five times higher than the stresses induced by low-stress material. It was also found that during die-attach some of residual stresses induced by chip's coating were released. The obtained results were compared with the straight forward finite element method prediction. It shows that the stresses predicted by the straight forward finite element analysis are much higher than the stresses obtained by the hybrid method.<>
{"title":"Manufacturing stresses in die due to die attach process","authors":"P. Tsao, Arkady S. Voloshin","doi":"10.1109/ECTC.1994.367623","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367623","url":null,"abstract":"Manufacturing of the electronic packages consisting of different materials leads to the development of the residual stresses due to mismatch in the coefficients of thermal expansion. Thus, to properly assess service life of the packages, those stresses must be taken into account. An experimental technique, the digital image analysis enhanced moire interferometry ( DIAEMI), was used to measure the in-situ out-of-plane displacements of the die due to the die-attach process. This information was related to the residual stresses in the die. Several test dies, with and without coating, were prepared and two different bonding materials, \"low-stress\" and \"high-stress\", were used for analysis of the induced stresses. The initial and final (after die-attach) surface contour patterns of the dies were observed and recorded. Out-of-plane displacements of the dies were obtained and induced stresses were calculated by a hybrid finite element method. The results show that stresses in die induced by high-stress bonding material are on average five times higher than the stresses induced by low-stress material. It was also found that during die-attach some of residual stresses induced by chip's coating were released. The obtained results were compared with the straight forward finite element method prediction. It shows that the stresses predicted by the straight forward finite element analysis are much higher than the stresses obtained by the hybrid method.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121569197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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