Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367632
P. Thompson
In Motorola's experience with commercial MCM customers, cost reduction is the largest driving factor for interest in MCMs. Speed and other performance factors are of secondary interest. Development and qualification can add significantly to the total cost of an MCM, so in addition to the normal desire to provide reliable products, the cost of doing so has gained increased importance. Motorola has identified three key factors in providing cost-effective MCMs: leverage single chip package experience, qualify MCM product families (package types), and use only qualified silicon devices in MCM products. This paper describes application of the three key factors to the reliability qualification of the 28 mm MCML Series package, a PQFP- (Plastic Quad Flat Pack) based MCM. An initial reliability evaluation was performed to investigate reliability issues. Subsequent to the results of the initial evaluation, changes were made to assembly processes and materials. The MCM was then submitted to a suite of reliability stresses selected to evaluate mechanical, thermomechanical, moisture and longevity performance. The MCM passed electrical and visual (SAT, or Scanning Acoustic Tomography) reliability requirements for all stresses, and performed well in extended stress tests as well. A procedure is in place to help insure high reliability for subsequent products in the 28 mm PQFP MCM package.<>
在摩托罗拉与商业MCM客户的经验中，成本降低是MCM的最大驱动因素。速度和其他性能因素是次要的。开发和认证会大大增加MCM的总成本，因此除了提供可靠产品的正常愿望之外，这样做的成本变得越来越重要。摩托罗拉确定了提供具有成本效益的MCM的三个关键因素:利用单芯片封装经验，合格的MCM产品系列(封装类型)，以及在MCM产品中仅使用合格的硅器件。本文介绍了这三个关键因素在基于PQFP (Plastic Quad Flat Pack)的28 mm MCML系列封装可靠性鉴定中的应用。进行了初步的可靠性评估，以调查可靠性问题。根据初步评估的结果，对装配工艺和材料进行了更改。然后将MCM提交给一套可靠性应力，以评估机械、热机械、湿度和寿命性能。MCM通过了所有应力下的电气和视觉(SAT，或扫描声层析成像)可靠性要求，并在扩展应力测试中表现良好。一个程序到位，以帮助确保后续产品在28毫米PQFP MCM封装的高可靠性。
{"title":"Reliability development and qualification of a low-cost, PQFP-based MCM","authors":"P. Thompson","doi":"10.1109/ECTC.1994.367632","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367632","url":null,"abstract":"In Motorola's experience with commercial MCM customers, cost reduction is the largest driving factor for interest in MCMs. Speed and other performance factors are of secondary interest. Development and qualification can add significantly to the total cost of an MCM, so in addition to the normal desire to provide reliable products, the cost of doing so has gained increased importance. Motorola has identified three key factors in providing cost-effective MCMs: leverage single chip package experience, qualify MCM product families (package types), and use only qualified silicon devices in MCM products. This paper describes application of the three key factors to the reliability qualification of the 28 mm MCML Series package, a PQFP- (Plastic Quad Flat Pack) based MCM. An initial reliability evaluation was performed to investigate reliability issues. Subsequent to the results of the initial evaluation, changes were made to assembly processes and materials. The MCM was then submitted to a suite of reliability stresses selected to evaluate mechanical, thermomechanical, moisture and longevity performance. The MCM passed electrical and visual (SAT, or Scanning Acoustic Tomography) reliability requirements for all stresses, and performed well in extended stress tests as well. A procedure is in place to help insure high reliability for subsequent products in the 28 mm PQFP MCM package.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128065051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367518
G. Heinen, R.J. Stierman, D. Edwards, L. Nye
A reliable process-for wire bonding over active integrated circuits, which are subsequently assembled in plastic packages, has been developed. This technology accommodates reducing the silicon die area required for bond pads and for on-chip bussing. Further, it supports area array wire bonding by allowing larger bond pads with relaxed pitch without sacrificing silicon area. This is accomplished by processing an additional metal layer on the wafer's protective overcoat for bond pad and bussing metallization. A stress buffer layer of polyimide is applied between the inorganic overcoat and top metal layer. Material characteristics and process requirements that are fully compatible with existing wafer fabrication technology and the wire bond technology required for assembly are defined. Design rules for implementing the process in new chip designs are given. Accelerated reliability tests performed on double-level metal logic devices show no degradation due to these new processes.<>
{"title":"Wire bonds over active circuits","authors":"G. Heinen, R.J. Stierman, D. Edwards, L. Nye","doi":"10.1109/ECTC.1994.367518","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367518","url":null,"abstract":"A reliable process-for wire bonding over active integrated circuits, which are subsequently assembled in plastic packages, has been developed. This technology accommodates reducing the silicon die area required for bond pads and for on-chip bussing. Further, it supports area array wire bonding by allowing larger bond pads with relaxed pitch without sacrificing silicon area. This is accomplished by processing an additional metal layer on the wafer's protective overcoat for bond pad and bussing metallization. A stress buffer layer of polyimide is applied between the inorganic overcoat and top metal layer. Material characteristics and process requirements that are fully compatible with existing wafer fabrication technology and the wire bond technology required for assembly are defined. Design rules for implementing the process in new chip designs are given. Accelerated reliability tests performed on double-level metal logic devices show no degradation due to these new processes.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132423204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367527
E. Reed
Relentless miniaturization of electronic circuitry and the general movement from through-hole to surface-mount manufacturing have generated explosive growth in the use of surface mount tantalum chip capacitors. Many of these applications involve substantial exposure to surge and ripple currents. Such exposure invites questions regarding the impact of surge and ripple current on the long-term reliability of tantalum chip capacitors. To facilitate a better understanding of the impact of surge and ripple current on tantalum chip capacitor reliability, theoretical analyses of generic circuits are supported with discussion of experimental data. Simple circuits that highlight the fundamental theoretical principles behind transient surge and steady-state ripple current applications are analyzed and pertinent reliability issues are discussed. The relationship of device ESR (equivalent series resistance) to surge and ripple current robustness and device temperature rise is established theoretically. Surge and ripple current test and measurement methods are briefly discussed and experimental test data are used to support many of the insights that are drawn from theory.<>
{"title":"Tantalum chip capacitor reliability in high surge and ripple current applications","authors":"E. Reed","doi":"10.1109/ECTC.1994.367527","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367527","url":null,"abstract":"Relentless miniaturization of electronic circuitry and the general movement from through-hole to surface-mount manufacturing have generated explosive growth in the use of surface mount tantalum chip capacitors. Many of these applications involve substantial exposure to surge and ripple currents. Such exposure invites questions regarding the impact of surge and ripple current on the long-term reliability of tantalum chip capacitors. To facilitate a better understanding of the impact of surge and ripple current on tantalum chip capacitor reliability, theoretical analyses of generic circuits are supported with discussion of experimental data. Simple circuits that highlight the fundamental theoretical principles behind transient surge and steady-state ripple current applications are analyzed and pertinent reliability issues are discussed. The relationship of device ESR (equivalent series resistance) to surge and ripple current robustness and device temperature rise is established theoretically. Surge and ripple current test and measurement methods are briefly discussed and experimental test data are used to support many of the insights that are drawn from theory.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134009301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367568
F. Choa, M. Shih, R. Kapre, W. Tsang, R. Logan
Without introducing extra processing steps, the idea of diluted waveguide is proposed and demonstrated to improve laser vertical modes. Such a new laser structures can simplify the work of laser-fiber coupling and relax the alignment tolerance. They may also be applied to obtain high power semiconductor lasers and polarization independent photonic devices.<>
{"title":"Packaging relaxed semiconductor lasers with diluted waveguide structure","authors":"F. Choa, M. Shih, R. Kapre, W. Tsang, R. Logan","doi":"10.1109/ECTC.1994.367568","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367568","url":null,"abstract":"Without introducing extra processing steps, the idea of diluted waveguide is proposed and demonstrated to improve laser vertical modes. Such a new laser structures can simplify the work of laser-fiber coupling and relax the alignment tolerance. They may also be applied to obtain high power semiconductor lasers and polarization independent photonic devices.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134522114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367656
M. Panicker, N. L. Greenman, J. Forster, P. Johnston
Ball grid array (BGA) is emerging as the next significant surface-mount package. This paper describes a simply structured, cost-effective ceramic BGA substrate, which conforms to current JEDEC registrations for flip-chip connections, as an alternative to multilayer co-fired ceramic BGA's. The BGA, processed on VIA/PLANE, a ceramic wafer with hermetic, tungsten-copper vias, uses a thin-film deposition technique, Enhanced Ion Plating (EIP). Controlled-Collapse Chip Connection (C4), solder-bumped flip chips are typically full or partial arrays of 5 mil solder bumps on 10 mil centers. This BGA transforms the C4 density to 35 mil bumps on 50 mil centers, much more compatible with current surface-mount assembly practices. The use of VIA/PLANE maintains the time-proven reliability of C4 on ceramic, and the flatness characteristics of VIA/PLANE eminently complement C4 and BGA technologies.<>
{"title":"Low-cost ceramic thin-film ball grid arrays","authors":"M. Panicker, N. L. Greenman, J. Forster, P. Johnston","doi":"10.1109/ECTC.1994.367656","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367656","url":null,"abstract":"Ball grid array (BGA) is emerging as the next significant surface-mount package. This paper describes a simply structured, cost-effective ceramic BGA substrate, which conforms to current JEDEC registrations for flip-chip connections, as an alternative to multilayer co-fired ceramic BGA's. The BGA, processed on VIA/PLANE, a ceramic wafer with hermetic, tungsten-copper vias, uses a thin-film deposition technique, Enhanced Ion Plating (EIP). Controlled-Collapse Chip Connection (C4), solder-bumped flip chips are typically full or partial arrays of 5 mil solder bumps on 10 mil centers. This BGA transforms the C4 density to 35 mil bumps on 50 mil centers, much more compatible with current surface-mount assembly practices. The use of VIA/PLANE maintains the time-proven reliability of C4 on ceramic, and the flatness characteristics of VIA/PLANE eminently complement C4 and BGA technologies.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"290 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127556935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367645
R.W. Kotlowitz, A. Rizzo
The long-term reliability of surface mount (SM) solder interconnections remains an important issue in many critical electronics packaging applications. Compliant leads are typically post-attached to leadless ceramic chip carriers (LCCCs) and multichip modules (MCMs) to enhance the SM attachment reliability margin on organic substrates. The various lead-forms are commercially available in edge-clip, soldered, and thermocompression (TC) bonded designs for component attachment. Compliance evaluation was performed for a representative corner-most solder connection on a LCCC. The effective stiffness of the solder joint and commercial post-attached lead designs were compared in order to demonstrate the SM interconnection reliability advantage provided by certain edge-clip and TC-bonded lead-forms. Commercial high-compliance edge-clip, soldered, and TC-bonded lead designs have diagonal-direction stiffness between nominally 10-40 lb/in, prior to circuit-board attachment. The compliant leads accommodate a large part of the component-substrate thermal expansion mismatch, significantly reducing the cyclic loads transmitted to the comparatively noncompliant solder connections. The diagonal stiffness results for the corner-most solder joint are specific for the particular contour and dimensions of the FE structural model. However, the current study provides fundamental understanding of the compliance advantage of post-attached leads compared to leadless SM interconnections.<>
{"title":"Comparative compliance of a representative surface mount leadless solder connection and commercial lead designs","authors":"R.W. Kotlowitz, A. Rizzo","doi":"10.1109/ECTC.1994.367645","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367645","url":null,"abstract":"The long-term reliability of surface mount (SM) solder interconnections remains an important issue in many critical electronics packaging applications. Compliant leads are typically post-attached to leadless ceramic chip carriers (LCCCs) and multichip modules (MCMs) to enhance the SM attachment reliability margin on organic substrates. The various lead-forms are commercially available in edge-clip, soldered, and thermocompression (TC) bonded designs for component attachment. Compliance evaluation was performed for a representative corner-most solder connection on a LCCC. The effective stiffness of the solder joint and commercial post-attached lead designs were compared in order to demonstrate the SM interconnection reliability advantage provided by certain edge-clip and TC-bonded lead-forms. Commercial high-compliance edge-clip, soldered, and TC-bonded lead designs have diagonal-direction stiffness between nominally 10-40 lb/in, prior to circuit-board attachment. The compliant leads accommodate a large part of the component-substrate thermal expansion mismatch, significantly reducing the cyclic loads transmitted to the comparatively noncompliant solder connections. The diagonal stiffness results for the corner-most solder joint are specific for the particular contour and dimensions of the FE structural model. However, the current study provides fundamental understanding of the compliance advantage of post-attached leads compared to leadless SM interconnections.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"305 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132793360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367655
A. Switky, V. Sajja, J. Darnauer, W. Dai
Described in this paper is a 1024-pin ball grid array package (BGA) that contains an area array die flip-chip mounted to a silicon transposer. The transposer, which fans the area array to two rows of pads on its periphery, is wire bonded to a printed circuit board substrate. Mechanical and electrical design considerations of the BGA are discussed, as well as the results of SPICE models.<>
{"title":"A 1024-pin plastic ball grid array for flip chip die","authors":"A. Switky, V. Sajja, J. Darnauer, W. Dai","doi":"10.1109/ECTC.1994.367655","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367655","url":null,"abstract":"Described in this paper is a 1024-pin ball grid array package (BGA) that contains an area array die flip-chip mounted to a silicon transposer. The transposer, which fans the area array to two rows of pads on its periphery, is wire bonded to a printed circuit board substrate. Mechanical and electrical design considerations of the BGA are discussed, as well as the results of SPICE models.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126596862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367635
J. Sauber, L. Lee, S. Hsu, T. Hongsmatip
The technique of linear elastic fracture mechanics was employed to characterize the fracture toughness of different molding compound materials. The effect of fast thermal loading rate as in a wave soldering condition was studied by performing the fracture toughness tests at different mechanical loading speeds. The effects of storage conditions and accelerated testing environments were studied by varying the test temperatures from liquid nitrogen temperature to 150/spl deg/C. Models were built of 208 I/O PQFP devices with cracks in the molding compound at the corner of the die pad. These models were solved to evaluate the effect of CTE mismatches, initial flaw sizes and die pad delamination on molding compound stress intensity factors. Finite element results were then compared with crack growth measurements from PQFP packages which had been subjected to accelerated thermal cycling.<>
{"title":"Fracture properties of molding compound materials for IC plastic packaging","authors":"J. Sauber, L. Lee, S. Hsu, T. Hongsmatip","doi":"10.1109/ECTC.1994.367635","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367635","url":null,"abstract":"The technique of linear elastic fracture mechanics was employed to characterize the fracture toughness of different molding compound materials. The effect of fast thermal loading rate as in a wave soldering condition was studied by performing the fracture toughness tests at different mechanical loading speeds. The effects of storage conditions and accelerated testing environments were studied by varying the test temperatures from liquid nitrogen temperature to 150/spl deg/C. Models were built of 208 I/O PQFP devices with cracks in the molding compound at the corner of the die pad. These models were solved to evaluate the effect of CTE mismatches, initial flaw sizes and die pad delamination on molding compound stress intensity factors. Finite element results were then compared with crack growth measurements from PQFP packages which had been subjected to accelerated thermal cycling.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130698220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367646
W. Huang, J. Casto
Electrical performance and printed circuit board routability tradeoff are studied in ceramic ball grid array packages (CBGAs). CBGA package design is described for a high speed chip with peripheral drivers. Three general types of array patterns are compared. First, the best routability design, where all the power and ground balls on the CBGA are routed in the center area. Second, a design with four pairs of P/G balls moved to the corners of the CBGA is evaluated, resulting in improvement of electrical performance by 50%, as measured by SSN reduction. The reasons for this improvement are analyzed. Third, even more P/G balls are moved closer to the onchip drivers, achieving an additional 30% reduction in SSN. In each case, the implications on board routability and simultaneous switching noise are assessed.<>
{"title":"CBGA package design for C4 PowerPC microprocessor chips: trade-off between substrate routability and performance","authors":"W. Huang, J. Casto","doi":"10.1109/ECTC.1994.367646","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367646","url":null,"abstract":"Electrical performance and printed circuit board routability tradeoff are studied in ceramic ball grid array packages (CBGAs). CBGA package design is described for a high speed chip with peripheral drivers. Three general types of array patterns are compared. First, the best routability design, where all the power and ground balls on the CBGA are routed in the center area. Second, a design with four pairs of P/G balls moved to the corners of the CBGA is evaluated, resulting in improvement of electrical performance by 50%, as measured by SSN reduction. The reasons for this improvement are analyzed. Third, even more P/G balls are moved closer to the onchip drivers, achieving an additional 30% reduction in SSN. In each case, the implications on board routability and simultaneous switching noise are assessed.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131230130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367625
E. Paulus
As electronic systems become more sensitive and sophisticated, they also become more susceptible to upset or failure caused by stray transient surges and noise. This is partially due to the use of integrated circuits and other vulnerable components. Suppression is therefore a vital part of today's military and commercial electronic systems. This article covers the methods of suppression which can be integrated within electrical connectors, how this is accomplished, the corresponding electrical performance, and the details needed for proper documentation.<>
{"title":"Surge/noise suppression within electrical connectors","authors":"E. Paulus","doi":"10.1109/ECTC.1994.367625","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367625","url":null,"abstract":"As electronic systems become more sensitive and sophisticated, they also become more susceptible to upset or failure caused by stray transient surges and noise. This is partially due to the use of integrated circuits and other vulnerable components. Suppression is therefore a vital part of today's military and commercial electronic systems. This article covers the methods of suppression which can be integrated within electrical connectors, how this is accomplished, the corresponding electrical performance, and the details needed for proper documentation.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"288 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133278564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：