Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367613
T. Knight, D. Salzman
Capacitive coupling of off-chip interconnects offers a number of advantages, including low manufacturing and repair costs, dense form factors, low power, high speed, extremely high junction pitch, and easy testing. In this paper, we review and compare the practicalities of conductive and capacitive coupling, and discuss novel issues of manufacturability and materials optimization for capacitively coupled electronic packages.<>
{"title":"Manufacturability of capacitively coupled multichip modules","authors":"T. Knight, D. Salzman","doi":"10.1109/ECTC.1994.367613","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367613","url":null,"abstract":"Capacitive coupling of off-chip interconnects offers a number of advantages, including low manufacturing and repair costs, dense form factors, low power, high speed, extremely high junction pitch, and easy testing. In this paper, we review and compare the practicalities of conductive and capacitive coupling, and discuss novel issues of manufacturability and materials optimization for capacitively coupled electronic packages.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132590291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367658
K. Puttlitz, W. Shutler
Future applications will require higher I/O counts, more densification, lower cost and greater performance. This paper demonstrates why area-array based chip-to-substrate and substrate-to-card interconnections are strategic, particularly solder bump flip chips (SBFC or C-4) and solder grid arrays (SGA) respectively. That is, SBFC are capable of high pin counts coupled with high yields, performance and reliability. Moreover, recently introduced SGA interconnections, both ball and column, provide substantial benefits over standard pin grid array (PGA) packages. Also, SGA packages possess the highest density achievable at the card level when utilized in conjunction with SBFC-mounted die.<>
{"title":"C-4/BGA comparison with other MLC single chip package alternatives","authors":"K. Puttlitz, W. Shutler","doi":"10.1109/ECTC.1994.367658","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367658","url":null,"abstract":"Future applications will require higher I/O counts, more densification, lower cost and greater performance. This paper demonstrates why area-array based chip-to-substrate and substrate-to-card interconnections are strategic, particularly solder bump flip chips (SBFC or C-4) and solder grid arrays (SGA) respectively. That is, SBFC are capable of high pin counts coupled with high yields, performance and reliability. Moreover, recently introduced SGA interconnections, both ball and column, provide substantial benefits over standard pin grid array (PGA) packages. Also, SGA packages possess the highest density achievable at the card level when utilized in conjunction with SBFC-mounted die.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128820451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367504
V. Bhagavatula, B. Boller, R.J. Hagerty, P. A. Sachenik
In this report, a number of novel, compact planar optical device (CPOD) concepts are described. The application of these novel structures for the fabrication of planar devices, such as 1/spl times/N couplers, is described. The requirements of these devices for various applications are given. The advantages of this approach for device fabrication and packaging are given. Performance results of a number of these devices made by a CVD planar process are presented.<>
{"title":"Compact planar optical devices (CPODs) by CVD technology","authors":"V. Bhagavatula, B. Boller, R.J. Hagerty, P. A. Sachenik","doi":"10.1109/ECTC.1994.367504","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367504","url":null,"abstract":"In this report, a number of novel, compact planar optical device (CPOD) concepts are described. The application of these novel structures for the fabrication of planar devices, such as 1/spl times/N couplers, is described. The requirements of these devices for various applications are given. The advantages of this approach for device fabrication and packaging are given. Performance results of a number of these devices made by a CVD planar process are presented.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114419368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367641
C. Wong, R. McBride
We have prepared well-controlled substrates (such as SiO/sub 2/, SiN, SiON) for our cleaning experiments and have developed a series of cleaning processes that achieve the best cleaning results prior to encapsulation. These cleaning processes consist of both chlorofluorohydrocarbon (CFC) and non-CFC solutions including (d-limonene), isopropanol, new surfactants, high purity, deionized water (DI H/sub 2/O) and peroxide (H/sub 2/O/sub 2/), etc. Furthermore, we have demonstrated that contact angle measurements in a 100% RH environment are simple, fast and reliable in detecting the substrate surface cleanliness particularly with respect to hydrocarbon contamination on the first /spl sim/10 angstroms of surface layers. ESCA and contact angle measurement analyses are also used to quantify and correlate the cleaning processes. Results of these processes are given in this report.<>
我们已经为我们的清洁实验准备了良好控制的衬底(如SiO/sub 2/， SiN, SiON)，并开发了一系列清洁工艺，在封装之前达到最佳清洁效果。这些清洗过程包括氯氟烃(CFC)和非CFC溶液，包括(d-柠檬烯)，异丙醇，新型表面活性剂，高纯度，去离子水(DI H/sub 2/O)和过氧化氢(H/sub 2/O/sub 2/)等。此外，我们已经证明，在100% RH环境下测量接触角在检测基材表面清洁度方面是简单、快速和可靠的，特别是在表面层的第一/spl sim/10埃上的碳氢化合物污染。ESCA和接触角测量分析也用于量化和关联清洗过程。这些过程的结果在本报告中给出。
{"title":"Preencapsulation cleaning methods and control for microelectronics packaging","authors":"C. Wong, R. McBride","doi":"10.1109/ECTC.1994.367641","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367641","url":null,"abstract":"We have prepared well-controlled substrates (such as SiO/sub 2/, SiN, SiON) for our cleaning experiments and have developed a series of cleaning processes that achieve the best cleaning results prior to encapsulation. These cleaning processes consist of both chlorofluorohydrocarbon (CFC) and non-CFC solutions including (d-limonene), isopropanol, new surfactants, high purity, deionized water (DI H/sub 2/O) and peroxide (H/sub 2/O/sub 2/), etc. Furthermore, we have demonstrated that contact angle measurements in a 100% RH environment are simple, fast and reliable in detecting the substrate surface cleanliness particularly with respect to hydrocarbon contamination on the first /spl sim/10 angstroms of surface layers. ESCA and contact angle measurement analyses are also used to quantify and correlate the cleaning processes. Results of these processes are given in this report.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114813016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367526
L. Yip
Standard plastic quad flatpacks have difficulty meeting the thermal performance requirements of devices with high power dissipation. The development of plastic thermally enhanced quad flat Packs (TEQFP), which incorporate heat slugs or heat spreaders in the leadframes, provide a cost effective solution. Because the final packages are of molded plastic, TEQFP's are susceptible to moisture induced cracking and other plastic reliability problems. This paper discusses the impact of moisture on package cracking during the board mounting process and the overall reliability of TEQFP's. Based on-our study using scanning acoustic tomography and reliability stress tests, our findings reveal that TEQFP's have comparable reliability to standard PQFP's if proper storage and drying guidelines are followed.<>
{"title":"Moisture sensitivity and reliability of plastic thermally enhanced QFP packages","authors":"L. Yip","doi":"10.1109/ECTC.1994.367526","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367526","url":null,"abstract":"Standard plastic quad flatpacks have difficulty meeting the thermal performance requirements of devices with high power dissipation. The development of plastic thermally enhanced quad flat Packs (TEQFP), which incorporate heat slugs or heat spreaders in the leadframes, provide a cost effective solution. Because the final packages are of molded plastic, TEQFP's are susceptible to moisture induced cracking and other plastic reliability problems. This paper discusses the impact of moisture on package cracking during the board mounting process and the overall reliability of TEQFP's. Based on-our study using scanning acoustic tomography and reliability stress tests, our findings reveal that TEQFP's have comparable reliability to standard PQFP's if proper storage and drying guidelines are followed.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117246277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367539
J. Zheng
A general purpose electromagnetic simulator 1E3D has been developed for the analysis and design of high frequency and high speed electronic circuit structures. For an arbitrarily shaped 3D metallic structure in a layered structure, the integral equation and method of moments based simulator solves the current distribution on the structure expanded into roof-top functions on a set of 3D triangular and rectangular cells. The simulator is interfaced with standard MS-Windows application programs for layout and schematic editing and post-processing.<>
{"title":"A 3D electromagnetic simulator for microwave and RF circuit boards","authors":"J. Zheng","doi":"10.1109/ECTC.1994.367539","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367539","url":null,"abstract":"A general purpose electromagnetic simulator 1E3D has been developed for the analysis and design of high frequency and high speed electronic circuit structures. For an arbitrarily shaped 3D metallic structure in a layered structure, the integral equation and method of moments based simulator solves the current distribution on the structure expanded into roof-top functions on a set of 3D triangular and rectangular cells. The simulator is interfaced with standard MS-Windows application programs for layout and schematic editing and post-processing.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129404050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367571
L. Hornak, S. Tewksbury, V.K. Konkimalla
Suggests various ways in which conventional silicon electronics might be used in an MCM daughterboard configuration to support optical interconnection modules for MCM-to-MCM optical interconnections. The emphasis is on achieving a synergistic merging of silicon electronic functions and III-V optoelectronics within a compact module that appears to be an electronic component at one end and appears to be a reliable optical interconnection component at the other end.<>
{"title":"Active mini-MCM daughterboard for optical interconnect insertion into microelectronic systems","authors":"L. Hornak, S. Tewksbury, V.K. Konkimalla","doi":"10.1109/ECTC.1994.367571","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367571","url":null,"abstract":"Suggests various ways in which conventional silicon electronics might be used in an MCM daughterboard configuration to support optical interconnection modules for MCM-to-MCM optical interconnections. The emphasis is on achieving a synergistic merging of silicon electronic functions and III-V optoelectronics within a compact module that appears to be an electronic component at one end and appears to be a reliable optical interconnection component at the other end.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132037548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367565
R. Patel, T. Wassick, C.Y. Ralston
A laser process to provide a thin barrier or capping metal, over the copper features of a multichip module thin film (MCM-D) structure is described. Capping of copper features is required to avoid copper corrosion and diffusion into overlaying dielectric layers of thin film structure. Furthermore, in a multilevel thin film structure, certain barrier metals provide improved adhesion for the subsequent dielectric layer. Experiments with XeCl and Nd:YAG lasers were performed to determine the best laser source for a copper/polymer/ceramic material set. The laser capping process is more robust and quicker than conventional photolithography or electroless plating capping processes, while eliminating the wet chemical operations. Also, the laser capping process eliminates the undercapping and variable capping metal thickness problems associated with photolithography and/or electroless plating techniques. The results of capping metal features on bare glass ceramic and polymer surfaces are described.<>
{"title":"Metal capping of MCM thin film features using a laser","authors":"R. Patel, T. Wassick, C.Y. Ralston","doi":"10.1109/ECTC.1994.367565","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367565","url":null,"abstract":"A laser process to provide a thin barrier or capping metal, over the copper features of a multichip module thin film (MCM-D) structure is described. Capping of copper features is required to avoid copper corrosion and diffusion into overlaying dielectric layers of thin film structure. Furthermore, in a multilevel thin film structure, certain barrier metals provide improved adhesion for the subsequent dielectric layer. Experiments with XeCl and Nd:YAG lasers were performed to determine the best laser source for a copper/polymer/ceramic material set. The laser capping process is more robust and quicker than conventional photolithography or electroless plating capping processes, while eliminating the wet chemical operations. Also, the laser capping process eliminates the undercapping and variable capping metal thickness problems associated with photolithography and/or electroless plating techniques. The results of capping metal features on bare glass ceramic and polymer surfaces are described.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130868301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367600
A. Nakamura, J. Mano, T. Nagata, H. Shimizu, M. Yagyu, K. Nishi, K. Otsuka
Accuracy of a circuit simulation for the simultaneous switching noise associated with a conventional plastic package was significantly improved by taking into account mutual inductances among leads. The effective inductance of a lead on a plastic package was suspected to be influenced by many other leads in the package. We have thus formulated a three dimensional conductor model for bonding wires, leads, and socket conductors to take into account their three dimensional structure. We calculated the mutual inductances and simulated the simultaneous switching noise by either including elements in the mutual inductance matrix or not. We clarified the contribution by the elements in the matrix, and a modeling technique for accurately simulating the simultaneous switching noise was proposed. This technique was developed for predicting characteristics of a assembled high-speed and multiple-bit device accurately during the circuit design stage. This would allow us to tailor the output circuit for maximum performance of devices under assembled condition. The design of the output circuit affects the simultaneous switching noise through the effective inductance of the ground line.<>
{"title":"Handling of mutual inductance in simulation of simultaneous switching noise","authors":"A. Nakamura, J. Mano, T. Nagata, H. Shimizu, M. Yagyu, K. Nishi, K. Otsuka","doi":"10.1109/ECTC.1994.367600","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367600","url":null,"abstract":"Accuracy of a circuit simulation for the simultaneous switching noise associated with a conventional plastic package was significantly improved by taking into account mutual inductances among leads. The effective inductance of a lead on a plastic package was suspected to be influenced by many other leads in the package. We have thus formulated a three dimensional conductor model for bonding wires, leads, and socket conductors to take into account their three dimensional structure. We calculated the mutual inductances and simulated the simultaneous switching noise by either including elements in the mutual inductance matrix or not. We clarified the contribution by the elements in the matrix, and a modeling technique for accurately simulating the simultaneous switching noise was proposed. This technique was developed for predicting characteristics of a assembled high-speed and multiple-bit device accurately during the circuit design stage. This would allow us to tailor the output circuit for maximum performance of devices under assembled condition. The design of the output circuit affects the simultaneous switching noise through the effective inductance of the ground line.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130270706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367572
S. Robinson, M. S. Acarlar, Y.C. Chen, L. Manzione, G. Shevchuk, D. Stefanik
In order to lower the cost of optical data link packaging, a new technology has been developed which integrates optical and electrical components in a single, sealed, transfer molded package. This technology utilizes leadframes for low cost and mass handling. Overmolding is used for package sealing and optical port alignment. A unique process, two step transfer molding, allows for internal shielding, intermediate IC testing, ease of assembly and IC package sealing. An injection molded outer housing is used for connector insertion and external shielding (through the use of conductive plastics). The first application of this technology is a high performance optical transceiver package for the growing FDDI market (125 MB/s). With a duplex MIC connector, this package conforms to an industry standard outline and pinout. The optical transceiver easily meets full FDDI specifications. The design integrates an LED, PIN, transmitter IC, receiver IC and two capacitors in a single, overmolded package. The final assembly sequence was conceived using the latest Design For Simplicity (DFS) principles. This paper describes the design concept and prototype model performance results.<>
{"title":"Low cost molded packaging for optical data links","authors":"S. Robinson, M. S. Acarlar, Y.C. Chen, L. Manzione, G. Shevchuk, D. Stefanik","doi":"10.1109/ECTC.1994.367572","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367572","url":null,"abstract":"In order to lower the cost of optical data link packaging, a new technology has been developed which integrates optical and electrical components in a single, sealed, transfer molded package. This technology utilizes leadframes for low cost and mass handling. Overmolding is used for package sealing and optical port alignment. A unique process, two step transfer molding, allows for internal shielding, intermediate IC testing, ease of assembly and IC package sealing. An injection molded outer housing is used for connector insertion and external shielding (through the use of conductive plastics). The first application of this technology is a high performance optical transceiver package for the growing FDDI market (125 MB/s). With a duplex MIC connector, this package conforms to an industry standard outline and pinout. The optical transceiver easily meets full FDDI specifications. The design integrates an LED, PIN, transmitter IC, receiver IC and two capacitors in a single, overmolded package. The final assembly sequence was conceived using the latest Design For Simplicity (DFS) principles. This paper describes the design concept and prototype model performance results.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121429667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：