Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283889
Dan Zhao, Yi Wang
This paper focuses on a novel self-configurable multihop wireless on-chip micronetwork, namely MTNet, to serve as the test access architecture for testing next generation billion-transistor SoCs. A geographic routing algorithm is proposed to find the test access paths for deeply embedded cores. Further, a path driven test scheduling algorithm is developed to design and optimize the MTNet-based SoC test access architecture. Extensive simulation study show the feasibility and applicability of using MTNet for nanoscale SoC testing.
{"title":"MTNET: Design and Optimization of a Wireless SOC Test Framework","authors":"Dan Zhao, Yi Wang","doi":"10.1109/SOCC.2006.283889","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283889","url":null,"abstract":"This paper focuses on a novel self-configurable multihop wireless on-chip micronetwork, namely MTNet, to serve as the test access architecture for testing next generation billion-transistor SoCs. A geographic routing algorithm is proposed to find the test access paths for deeply embedded cores. Further, a path driven test scheduling algorithm is developed to design and optimize the MTNet-based SoC test access architecture. Extensive simulation study show the feasibility and applicability of using MTNet for nanoscale SoC testing.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"340 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125795307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283880
J. Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang
With the rapid increase of complexity in system-on-a-chip (SoC) design, the electronic design automation (EDA) community is moving from RTL (Register Transfer Level) synthesis to behavioral-level and system-level synthesis. The needs of system-level verification and software/hardware co-design also prefer behavior-level executable specifications, such as C or SystemC. In this paper we present the platform-based synthesis system, named xPilot, being developed at UCLA. The first objective of xPilot is to provide novel behavioral synthesis capability for automatically generating efficient RTL code from a C or SystemC description for a given system platform and optimizing the logic, interconnects, performance, and power simultaneously. The second objective of xPilot is to provide a platform-based system-level synthesis capability, including both synthesis for application-specific configurable processors and heterogeneous multi-core systems. Preliminary experiments on FPGAs demonstrate the efficacy of our approach on a wide range of applications and its value in exploring various design tradeoffs.
{"title":"Platform-Based Behavior-Level and System-Level Synthesis","authors":"J. Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang","doi":"10.1109/SOCC.2006.283880","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283880","url":null,"abstract":"With the rapid increase of complexity in system-on-a-chip (SoC) design, the electronic design automation (EDA) community is moving from RTL (Register Transfer Level) synthesis to behavioral-level and system-level synthesis. The needs of system-level verification and software/hardware co-design also prefer behavior-level executable specifications, such as C or SystemC. In this paper we present the platform-based synthesis system, named xPilot, being developed at UCLA. The first objective of xPilot is to provide novel behavioral synthesis capability for automatically generating efficient RTL code from a C or SystemC description for a given system platform and optimizing the logic, interconnects, performance, and power simultaneously. The second objective of xPilot is to provide a platform-based system-level synthesis capability, including both synthesis for application-specific configurable processors and heterogeneous multi-core systems. Preliminary experiments on FPGAs demonstrate the efficacy of our approach on a wide range of applications and its value in exploring various design tradeoffs.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132149708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283852
Ranjith Kumar, V. Kursun
In this paper, the supply and threshold voltage optimization techniques to achieve temperature variation insensitive circuit performance are compared. The speed and energy tradeoffs with the two optimization techniques are presented.
{"title":"Supply and Threshold Voltage Optimization for Temperature Variation Insensitive Circuit Performance: A Comparison","authors":"Ranjith Kumar, V. Kursun","doi":"10.1109/SOCC.2006.283852","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283852","url":null,"abstract":"In this paper, the supply and threshold voltage optimization techniques to achieve temperature variation insensitive circuit performance are compared. The speed and energy tradeoffs with the two optimization techniques are presented.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125514110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283866
Li Jing-hu, Yu Ming-yan, Wang Yong-sheng, W. Jin-xiang
An 8-bit analog-to-digital (A/D) converter from 1.3 V supply voltage in 0.18 mum CMOS technology without use of low-threshold MOS transistor is presented. The A/D converter features a low voltage reference generator, modified pipeline chopper amplifier and pre-equalized comparator. Simulation result shows the A/D converter achieves + 0.17 LSB differential nonlinearity (DNL), + 0.34 LSB integral nonlinearity (INL) and 48 dB SNDR at 166 MHz sampling rate with 1.79 MHZ sinusoidal input. The total power consumption is 30 mW.
{"title":"A 1.3 V 30-mW 8-BIT 166-MS/s A/D Converter in 0.18 μm CMOS with Reference Generator","authors":"Li Jing-hu, Yu Ming-yan, Wang Yong-sheng, W. Jin-xiang","doi":"10.1109/SOCC.2006.283866","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283866","url":null,"abstract":"An 8-bit analog-to-digital (A/D) converter from 1.3 V supply voltage in 0.18 mum CMOS technology without use of low-threshold MOS transistor is presented. The A/D converter features a low voltage reference generator, modified pipeline chopper amplifier and pre-equalized comparator. Simulation result shows the A/D converter achieves + 0.17 LSB differential nonlinearity (DNL), + 0.34 LSB integral nonlinearity (INL) and 48 dB SNDR at 166 MHz sampling rate with 1.79 MHZ sinusoidal input. The total power consumption is 30 mW.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124953633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283871
S. Mukhopadhyay, Swaroop Ghosh, Keejong Kim, K. Roy
Inter-die and intra-die variation in process parameters increases parametric failures and leakage spread in nano-scale memories, leading to significant yield degradation. Design level optimization methods are not sufficient to address the leakage and parametric failures, particularly, under large variation. In this paper, we propose two post-silicon tuning techniques which can simultaneously reduce the leakage spread and improve parametric yield in memories. We show that, self- repairing and self-adaptive systems with post-silicon tuning are essential for designing low-power and robust memories in sub- 90 nm technologies.
{"title":"Low-Power and Process Variation Tolerant Memories in sub-90nm Technologies","authors":"S. Mukhopadhyay, Swaroop Ghosh, Keejong Kim, K. Roy","doi":"10.1109/SOCC.2006.283871","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283871","url":null,"abstract":"Inter-die and intra-die variation in process parameters increases parametric failures and leakage spread in nano-scale memories, leading to significant yield degradation. Design level optimization methods are not sufficient to address the leakage and parametric failures, particularly, under large variation. In this paper, we propose two post-silicon tuning techniques which can simultaneously reduce the leakage spread and improve parametric yield in memories. We show that, self- repairing and self-adaptive systems with post-silicon tuning are essential for designing low-power and robust memories in sub- 90 nm technologies.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122485812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283874
A. Su, Robert Chen
We applied electronic system level design methodology (ESL) in the dual-core system-on-a-chip (SoC) platform designing. It included implementing components at transaction level (TL) using SystemC, adapting a self designed digital signal processor (DSP) into system-level simulators and modeling virtual platform architectures to conduct an experiment to compare inter-process communication (IPC) mechanisms using mailbox and shared memory. We also experimented in applying a new transaction level component (TLC) definition for modeling training and discussed the need for separating transaction passing implementation from computation.
{"title":"Applying ESL in A Dual-Core SoC Platform Designing","authors":"A. Su, Robert Chen","doi":"10.1109/SOCC.2006.283874","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283874","url":null,"abstract":"We applied electronic system level design methodology (ESL) in the dual-core system-on-a-chip (SoC) platform designing. It included implementing components at transaction level (TL) using SystemC, adapting a self designed digital signal processor (DSP) into system-level simulators and modeling virtual platform architectures to conduct an experiment to compare inter-process communication (IPC) mechanisms using mailbox and shared memory. We also experimented in applying a new transaction level component (TLC) definition for modeling training and discussed the need for separating transaction passing implementation from computation.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131487368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283872
Thanh-Tung Hoang, J. Son, Yu-Ri Kang, Chae-Ryung Kim, Hae-Young Chung, Soo-Won Kim
This paper presents a QRS detector operating in multi-mode with low complexity, power saving consumption for implantable pacemaker IC. The complexity of detector is optimized after testing dynamic range of internal signals. Correspondingly, static power consumption is reduced significantly. The dynamic power consumption is saved by using down-sampling rate structure and turning off de- active filter banks bases on noise estimation. This QRS detector is evaluated with MIT-BIH Arrhythmia database archives >99% detection ratio. A soft IP core is prototyped on FPGA and synthesized by Samsung 0.18um standard library.
{"title":"A low complexity, low power, programmable QRS detector based on wavelet transform for Implantable Pacemaker IC","authors":"Thanh-Tung Hoang, J. Son, Yu-Ri Kang, Chae-Ryung Kim, Hae-Young Chung, Soo-Won Kim","doi":"10.1109/SOCC.2006.283872","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283872","url":null,"abstract":"This paper presents a QRS detector operating in multi-mode with low complexity, power saving consumption for implantable pacemaker IC. The complexity of detector is optimized after testing dynamic range of internal signals. Correspondingly, static power consumption is reduced significantly. The dynamic power consumption is saved by using down-sampling rate structure and turning off de- active filter banks bases on noise estimation. This QRS detector is evaluated with MIT-BIH Arrhythmia database archives >99% detection ratio. A soft IP core is prototyped on FPGA and synthesized by Samsung 0.18um standard library.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133278110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283861
G. Chen, Liping Xue, Jungsub Kim, K. Sobti, L. Deng, Xiaobai Sun, N. Pitsianis, C. Chakrabarti, M. Kandemir, N. Vijaykrishnan
This work focuses on reducing power consumption while maintaining the efficiency and accuracy of matrix computations using both algorithmic and architectural means. We transform the algorithms, in adaptation to application specifics, to translate the matrix structures into power saving potential via geometric tiling. Instead of using blind tiling, we index and partition matrix elements according to the underlying geometry to claim a better estimate and control of numerical range within and across geometric tiles, which can then be exploited for power saving.
{"title":"Geometric Tiling for Reducing Power Consumption in Structured Matrix Operations","authors":"G. Chen, Liping Xue, Jungsub Kim, K. Sobti, L. Deng, Xiaobai Sun, N. Pitsianis, C. Chakrabarti, M. Kandemir, N. Vijaykrishnan","doi":"10.1109/SOCC.2006.283861","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283861","url":null,"abstract":"This work focuses on reducing power consumption while maintaining the efficiency and accuracy of matrix computations using both algorithmic and architectural means. We transform the algorithms, in adaptation to application specifics, to translate the matrix structures into power saving potential via geometric tiling. Instead of using blind tiling, we index and partition matrix elements according to the underlying geometry to claim a better estimate and control of numerical range within and across geometric tiles, which can then be exploited for power saving.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124908706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283904
N. Mohan, M. Sachdev
Architectural innovations are reducing the dynamic power in ternary content addressable memories (TCAMs). Thus, the static power is becoming a significant portion of the total TCAM power. This paper presents two novel ternary storage cells that exploit the unique properties of TCAMs for reducing the cell leakage. Simulation results of the proposed cells show up to 41% leakage reduction over the conventional TCAM cell.
{"title":"Novel Ternary Storage Cells and Techniques for Leakage Reduction in Ternary CAM","authors":"N. Mohan, M. Sachdev","doi":"10.1109/SOCC.2006.283904","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283904","url":null,"abstract":"Architectural innovations are reducing the dynamic power in ternary content addressable memories (TCAMs). Thus, the static power is becoming a significant portion of the total TCAM power. This paper presents two novel ternary storage cells that exploit the unique properties of TCAMs for reducing the cell leakage. Simulation results of the proposed cells show up to 41% leakage reduction over the conventional TCAM cell.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129950850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283882
T. Kouno, H. Onodera
This paper discusses the treatment of the transition-time variability in statistical static timing analysis (SSTA). In SSTA, the signal arrival time is treated as a statistical variable. In reality, the signal transition time also fluctuates due to process variations, which effect should be taken into account. Also, in a multiple fan-in gate, there exist multiple transition-time variabilities associated with each input. Effective treatment of the multiple possibilities is required. This paper first discusses the effect of transition-time variability on the delay distribution. A method is proposed that derives the variability of transition time from the delay variability and considers the effect of transition-time variability using a linearized model. An experiment shows that the error of the method is less than 0.2% whereas the error grows to 4% if we neglect the effect of transition-time variability. For multiple fan-in gates, we convert multiple transition time variabilities into a single variability by taking a weighted average of the variabilities. The error of the conversion is around 1% in our experiments. The proposed treatments of the transition-time variability improve the accuracy of SSTA without changing the framework of existing SSTA methods.
{"title":"Consideration of Transition-Time Variability in Statistical Timing Analysis","authors":"T. Kouno, H. Onodera","doi":"10.1109/SOCC.2006.283882","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283882","url":null,"abstract":"This paper discusses the treatment of the transition-time variability in statistical static timing analysis (SSTA). In SSTA, the signal arrival time is treated as a statistical variable. In reality, the signal transition time also fluctuates due to process variations, which effect should be taken into account. Also, in a multiple fan-in gate, there exist multiple transition-time variabilities associated with each input. Effective treatment of the multiple possibilities is required. This paper first discusses the effect of transition-time variability on the delay distribution. A method is proposed that derives the variability of transition time from the delay variability and considers the effect of transition-time variability using a linearized model. An experiment shows that the error of the method is less than 0.2% whereas the error grows to 4% if we neglect the effect of transition-time variability. For multiple fan-in gates, we convert multiple transition time variabilities into a single variability by taking a weighted average of the variabilities. The error of the conversion is around 1% in our experiments. The proposed treatments of the transition-time variability improve the accuracy of SSTA without changing the framework of existing SSTA methods.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129270893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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