Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283890
Q. Ding, Rong Luo, Hui Wang, Huazhong Yang, Yuan Xie
In this paper, we investigate the impact of process variation on soft error vulnerability with Monte Carlo analysis. Our simulation results show that Qcritical variation (3sigma/mean) of four types of storage circuits caused by process variation can be as large as 13.6%. We also propose an empirical model to estimate the Qcritical variation caused by gate length and threshold voltage variations. Simulation results show that this simple model is very accurate. Based on this model, the dependence of Qcritical variation on gate length variation, threshold voltage variation, and correlation between gate lengths is studied, using 70 nm SRAM as benchmark circuit.
{"title":"Modeling the Impact of Process Variation on Critical Charge Distribution","authors":"Q. Ding, Rong Luo, Hui Wang, Huazhong Yang, Yuan Xie","doi":"10.1109/SOCC.2006.283890","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283890","url":null,"abstract":"In this paper, we investigate the impact of process variation on soft error vulnerability with Monte Carlo analysis. Our simulation results show that Qcritical variation (3sigma/mean) of four types of storage circuits caused by process variation can be as large as 13.6%. We also propose an empirical model to estimate the Qcritical variation caused by gate length and threshold voltage variations. Simulation results show that this simple model is very accurate. Based on this model, the dependence of Qcritical variation on gate length variation, threshold voltage variation, and correlation between gate lengths is studied, using 70 nm SRAM as benchmark circuit.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134150299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283859
D. Mathaikutty, S. Shukla
Given a SystemC IP library, constructing SoC simulation models for design space exploration often distract designers from system architecture concerns to software engineering and programming concerns. Fast design space exploration using a visual architectural specification framework followed by automated IP selection and construction of simulation models without having to programmatically composing the IPs is the main attractive feature of the component composition framework developed and described in this paper. We employ concepts of metamodeling for the visual specification, meta-data for the IP reflection, and algorithmic analysis of metadata for IP selection, matching and executable model construction.
{"title":"SoC Design Space Exploration through Automated IP Selection from SystemC IP Library","authors":"D. Mathaikutty, S. Shukla","doi":"10.1109/SOCC.2006.283859","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283859","url":null,"abstract":"Given a SystemC IP library, constructing SoC simulation models for design space exploration often distract designers from system architecture concerns to software engineering and programming concerns. Fast design space exploration using a visual architectural specification framework followed by automated IP selection and construction of simulation models without having to programmatically composing the IPs is the main attractive feature of the component composition framework developed and described in this paper. We employ concepts of metamodeling for the visual specification, meta-data for the IP reflection, and algorithmic analysis of metadata for IP selection, matching and executable model construction.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132140581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283863
R. Tang, Yong-Bin Kim
A novel phase-locked-loop (PLL) topology for pulse width modulation (PWM) technique in high speed I/O circuits is presented in this paper. The VCO of the PLL generates the eight phase clocks of the same frequency. A simple level shifter structure is used to amplify the VCO output signal to the full voltage swing and guarantee 50% duty cycle for a wide range of frequency. The performance of the charge-pump and phase- frequency detector is improved from the previous research. The proposed PLL can be used in both transmitter end and receiver end and the performance satisfies the requirements of high speed wireline communication.
{"title":"A Novel 8-Phase PLL Design for PWM Scheme in High Speed I/O Circuits","authors":"R. Tang, Yong-Bin Kim","doi":"10.1109/SOCC.2006.283863","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283863","url":null,"abstract":"A novel phase-locked-loop (PLL) topology for pulse width modulation (PWM) technique in high speed I/O circuits is presented in this paper. The VCO of the PLL generates the eight phase clocks of the same frequency. A simple level shifter structure is used to amplify the VCO output signal to the full voltage swing and guarantee 50% duty cycle for a wide range of frequency. The performance of the charge-pump and phase- frequency detector is improved from the previous research. The proposed PLL can be used in both transmitter end and receiver end and the performance satisfies the requirements of high speed wireline communication.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115099970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283903
W. Reohr
The disciplines of process development, circuit design, and microarchitecture too often remain isolated. This paper on memories explores the benefit of their unification by taking a retrospective look at a L1 cache memory design, a current view of embedded DRAM, and a speculative peek at emerging memories (e.g. MTJ MRAM). In the midst, a novel refresh operation is proposed for DRAM that relies on read and write activity ongoing within a cache to refresh the DRAM.
{"title":"Memories: Exploiting Them and Developing Them","authors":"W. Reohr","doi":"10.1109/SOCC.2006.283903","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283903","url":null,"abstract":"The disciplines of process development, circuit design, and microarchitecture too often remain isolated. This paper on memories explores the benefit of their unification by taking a retrospective look at a L1 cache memory design, a current view of embedded DRAM, and a speculative peek at emerging memories (e.g. MTJ MRAM). In the midst, a novel refresh operation is proposed for DRAM that relies on read and write activity ongoing within a cache to refresh the DRAM.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132805849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283884
Raj Varada, S. Tarn, J. Benoit, Kris Chou
A multi-threaded dual-core Xeonreg MP processor with 16 MB of L3 cache and operating at a top frequency of 3.4 GHz has been developed using a non-traditional SOC design methodology on a 65 nm process technology. The design methodology embodied highly controlled, customized, and high impact changes to the underlying pre-existing processor cores resulting in performance and functionality that approaches a fully custom design while maintaining high re-use of the existing processor core. This paper presents the key design methodologies and the challenges.
{"title":"SOC Design Challenges in a Multi-threaded 65nm Dual Core Xeon® MP Processor","authors":"Raj Varada, S. Tarn, J. Benoit, Kris Chou","doi":"10.1109/SOCC.2006.283884","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283884","url":null,"abstract":"A multi-threaded dual-core Xeonreg MP processor with 16 MB of L3 cache and operating at a top frequency of 3.4 GHz has been developed using a non-traditional SOC design methodology on a 65 nm process technology. The design methodology embodied highly controlled, customized, and high impact changes to the underlying pre-existing processor cores resulting in performance and functionality that approaches a fully custom design while maintaining high re-use of the existing processor core. This paper presents the key design methodologies and the challenges.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129438835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283900
V. Venkatraman, M. Anders, Himanshu Kaul, W. Burleson, R. Krishnamurthy
This paper describes a low-swing on-chip interconnect signaling technique. A simple receiver circuit enables significant total energy and delay reduction compared to conventional repeaters over intermediate and global interconnects. A 5 mm minimum pitch global interconnect in 65nm CMOS technology using 1.1V supply exhibits a reduction of 56% in total energy, 21% in delay, and 86% in area.
{"title":"A Low-swing Signaling Circuit Technique for 65nm On-chip Interconnects","authors":"V. Venkatraman, M. Anders, Himanshu Kaul, W. Burleson, R. Krishnamurthy","doi":"10.1109/SOCC.2006.283900","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283900","url":null,"abstract":"This paper describes a low-swing on-chip interconnect signaling technique. A simple receiver circuit enables significant total energy and delay reduction compared to conventional repeaters over intermediate and global interconnects. A 5 mm minimum pitch global interconnect in 65nm CMOS technology using 1.1V supply exhibits a reduction of 56% in total energy, 21% in delay, and 86% in area.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124303416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283887
Appaya Devaraj Swaminathan, T. Seceleanu
In this study, we discuss communication aspects concerning a segmented bus platform. The segmented bus architecture provides certain performance improvements compared to the traditional bus systems, while employing a much simpler communication structure and algorithm than those thought for networks-on-chip. Our implementation strategy targets an FPGA technology and considers multiple clock domains. By means of interrupt-like procedures, we obtain both improvements in performance and accurate throughput characterization.
{"title":"Interrupt Communication on the SegBus platform","authors":"Appaya Devaraj Swaminathan, T. Seceleanu","doi":"10.1109/SOCC.2006.283887","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283887","url":null,"abstract":"In this study, we discuss communication aspects concerning a segmented bus platform. The segmented bus architecture provides certain performance improvements compared to the traditional bus systems, while employing a much simpler communication structure and algorithm than those thought for networks-on-chip. Our implementation strategy targets an FPGA technology and considers multiple clock domains. By means of interrupt-like procedures, we obtain both improvements in performance and accurate throughput characterization.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115241871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283873
M. Agarwal, P. Elakkumanan, R. Sridhar
With aggressive technology scaling, leakage power is fast becoming a significant component of the total power consumption of high-performance circuits. In this paper, we analyse the gate leakage and subthreshold leakage current characteristics of domino circuits and propose a circuit which reduces both gate and subthreshold leakage, and thus the overall leakage of sub-65 nm domino circuits. Simulation results based on 45 nm BSIM4 models show that the gate leakage, subthreshold leakage and overall leakage are reduced by up to 94%, 64% and 89% respectively, as compared to the conventional dual-Vt designs. The proposed circuit maintains the inputs, the dynamic node and the output node at logic high, to reduce the gate leakage. It reduces subthreshold leakage by enhancing the stack effect and source biasing effect.
{"title":"Leakage Reduction for Domino Circuits in Sub-65nm Technologies","authors":"M. Agarwal, P. Elakkumanan, R. Sridhar","doi":"10.1109/SOCC.2006.283873","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283873","url":null,"abstract":"With aggressive technology scaling, leakage power is fast becoming a significant component of the total power consumption of high-performance circuits. In this paper, we analyse the gate leakage and subthreshold leakage current characteristics of domino circuits and propose a circuit which reduces both gate and subthreshold leakage, and thus the overall leakage of sub-65 nm domino circuits. Simulation results based on 45 nm BSIM4 models show that the gate leakage, subthreshold leakage and overall leakage are reduced by up to 94%, 64% and 89% respectively, as compared to the conventional dual-Vt designs. The proposed circuit maintains the inputs, the dynamic node and the output node at logic high, to reduce the gate leakage. It reduces subthreshold leakage by enhancing the stack effect and source biasing effect.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116039088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283902
B. Mohammad, P. Bassett, J. Abraham, A. Aziz
Caches are becoming an increasingly important part of embedded processor design because of the impact they have on performance as well as implementation, specifically, area, power and timing. Different cache organizations make tradeoffs between these metrics. One of the main architectural choices is whether to use standard SRAM-based tag design or to go with a CAM- based organization. This choice has far reaching consequences on all other aspects of the cache design. We will compare these two cache styles using results from a recently completed DSP core design. Our conclusion is that, contrary to popular belief, an SRAM-tag based design provided a more optimal overall design point and is superior in energy respect. Some of driving factors such as the increasing dominance of wire and leakage power will be extrapolated forward to next generation processes.
{"title":"Cache Organization for Embeded Processors: CAM-vs-SRAM","authors":"B. Mohammad, P. Bassett, J. Abraham, A. Aziz","doi":"10.1109/SOCC.2006.283902","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283902","url":null,"abstract":"Caches are becoming an increasingly important part of embedded processor design because of the impact they have on performance as well as implementation, specifically, area, power and timing. Different cache organizations make tradeoffs between these metrics. One of the main architectural choices is whether to use standard SRAM-based tag design or to go with a CAM- based organization. This choice has far reaching consequences on all other aspects of the cache design. We will compare these two cache styles using results from a recently completed DSP core design. Our conclusion is that, contrary to popular belief, an SRAM-tag based design provided a more optimal overall design point and is superior in energy respect. Some of driving factors such as the increasing dominance of wire and leakage power will be extrapolated forward to next generation processes.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117264318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283853
Xiaoxia Wu, Feng Wang, Yuan Xie
In this paper, we first explore sub-threshold Fin-FET circuits design space, finding their optimal power supply point for minimum energy consumption. We then study soft error vulnerability in sub-threshold region. Our experiments indicate that the energy consumption in sub-threshold region can achieve 4 orders of magnitude energy saving. Compared to bulk CMOS technology, FinFET circuits have lower functional power supply and lower optimal energy consumption in subthreshold region. In addition, FinFET has better soft error immunity in sub-threshold region.
{"title":"Analysis of Subthreshold Finfet Circuits for Ultra-Low Power Design","authors":"Xiaoxia Wu, Feng Wang, Yuan Xie","doi":"10.1109/SOCC.2006.283853","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283853","url":null,"abstract":"In this paper, we first explore sub-threshold Fin-FET circuits design space, finding their optimal power supply point for minimum energy consumption. We then study soft error vulnerability in sub-threshold region. Our experiments indicate that the energy consumption in sub-threshold region can achieve 4 orders of magnitude energy saving. Compared to bulk CMOS technology, FinFET circuits have lower functional power supply and lower optimal energy consumption in subthreshold region. In addition, FinFET has better soft error immunity in sub-threshold region.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"100 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122882723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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