Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283901
E. Salman, E. Friedman, R. Secareanu
The interaction of the substrate with the inductive on-chip ground distribution network is analyzed in this paper. A transistor level approach is presented to illustrate the effects of the substrate on ground noise. The substrate can have a significant effect on ground noise due to the inductance of the ground lines. For a CMOS inverter, the substrate can reduce negative peak ground noise by 49% during the high-to-low output transition. The substrate, however, increases the positive peak ground noise by 72% during the low-to-high output transition. The effect of the substrate should therefore not be neglected if the inductance of the on-chip ground distribution network is non-negligible. Furthermore, conventional triangle or trapezoid type current demand estimations of the nonlinear circuits are shown to be significantly inaccurate if the ground lines exhibit inductive behavior.
{"title":"Substrate and Ground Noise Interactions in Mixed-Signal Circuits","authors":"E. Salman, E. Friedman, R. Secareanu","doi":"10.1109/SOCC.2006.283901","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283901","url":null,"abstract":"The interaction of the substrate with the inductive on-chip ground distribution network is analyzed in this paper. A transistor level approach is presented to illustrate the effects of the substrate on ground noise. The substrate can have a significant effect on ground noise due to the inductance of the ground lines. For a CMOS inverter, the substrate can reduce negative peak ground noise by 49% during the high-to-low output transition. The substrate, however, increases the positive peak ground noise by 72% during the low-to-high output transition. The effect of the substrate should therefore not be neglected if the inductance of the on-chip ground distribution network is non-negligible. Furthermore, conventional triangle or trapezoid type current demand estimations of the nonlinear circuits are shown to be significantly inaccurate if the ground lines exhibit inductive behavior.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128881462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283907
A. Agarwal, R. Krishnamurthy
This tutorial discusses challenges and design solutions for high-performance energy efficient memory/register file circuit design. Technology scaling trends for leakage and process variation for sub-45nm technologies are analyzed, with special emphasis on their impact on wide fan in OR gates found in high performance register file. Novel high-speed and leakage/process tolerant circuits are reviewed. Leakage/process sensors which enable these processes compensating techniques are presented.
{"title":"High-performance energy-efficient memory circuit technologies for sub-45nm technologies","authors":"A. Agarwal, R. Krishnamurthy","doi":"10.1109/SOCC.2006.283907","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283907","url":null,"abstract":"This tutorial discusses challenges and design solutions for high-performance energy efficient memory/register file circuit design. Technology scaling trends for leakage and process variation for sub-45nm technologies are analyzed, with special emphasis on their impact on wide fan in OR gates found in high performance register file. Novel high-speed and leakage/process tolerant circuits are reviewed. Leakage/process sensors which enable these processes compensating techniques are presented.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128900481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283857
P. Sundararajan, S. Krishnamurthy, N. Vijaykrishnan, K. Chaudhary, R. Jayaraman
Platform FPGAs have introduced complex reconfigurable black-boxes for complete system on chip implementation. With rising expectations from these architectures there is a need to perform optimizations across the FPGA slice fabric and the newly introduced black boxes to maximize performance gains. In this paper, we discuss a timing driven reconfiguration technique to improve performance of DSP designs on platform FPGAs by (i) optimal register placement algorithms within the DSP 48 block and (ii) timing driven mechanism to have maximal pipeline depth.
{"title":"Performance Improvements through Timing Driven Reconfiguration of Black-Boxes in Platform FPGAs","authors":"P. Sundararajan, S. Krishnamurthy, N. Vijaykrishnan, K. Chaudhary, R. Jayaraman","doi":"10.1109/SOCC.2006.283857","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283857","url":null,"abstract":"Platform FPGAs have introduced complex reconfigurable black-boxes for complete system on chip implementation. With rising expectations from these architectures there is a need to perform optimizations across the FPGA slice fabric and the newly introduced black boxes to maximize performance gains. In this paper, we discuss a timing driven reconfiguration technique to improve performance of DSP designs on platform FPGAs by (i) optimal register placement algorithms within the DSP 48 block and (ii) timing driven mechanism to have maximal pipeline depth.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127505555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283847
Haolu Xie, S. Fan, Xin Wang, Albert Z. H. Wang, Zhihua Wang, Hongyi Chen
In this paper, a single-chip pulse-based, non- carrier, full-band, low power ultra wideband (UWB) transceiver system-on-a-chip (SoC) for high data rate wireless video/audio/multimedia streaming applications is presented. This UWB SoC features a single full-band (7.5 GHz bandwidth from 3.1 GHz to 10.6 GHz), pulse-based non-carrier architecture to achieve high throughput (>100 Mbps) and high simplicity. It consists of low-noise amplifier (LNA), correlator, integrator, pulse generator, power switches and timing controller. This digital-ready UWB SoC features an on-chip analog-to-digital converter (ADC). The SoC uses BPSK modulation, Gaussian pulsing, and a global switching technique for power reduction. As the result, the average power consumption of the transceiver (no ADC) is 6 mW only. The SoC is designed in a commercial 0.18 mum SiGe BiCMOS technology.
{"title":"A Pulse-Based Full-Band UWB Transceiver SoC in 0.18μm SiGe BiCMOS","authors":"Haolu Xie, S. Fan, Xin Wang, Albert Z. H. Wang, Zhihua Wang, Hongyi Chen","doi":"10.1109/SOCC.2006.283847","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283847","url":null,"abstract":"In this paper, a single-chip pulse-based, non- carrier, full-band, low power ultra wideband (UWB) transceiver system-on-a-chip (SoC) for high data rate wireless video/audio/multimedia streaming applications is presented. This UWB SoC features a single full-band (7.5 GHz bandwidth from 3.1 GHz to 10.6 GHz), pulse-based non-carrier architecture to achieve high throughput (>100 Mbps) and high simplicity. It consists of low-noise amplifier (LNA), correlator, integrator, pulse generator, power switches and timing controller. This digital-ready UWB SoC features an on-chip analog-to-digital converter (ADC). The SoC uses BPSK modulation, Gaussian pulsing, and a global switching technique for power reduction. As the result, the average power consumption of the transceiver (no ADC) is 6 mW only. The SoC is designed in a commercial 0.18 mum SiGe BiCMOS technology.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127606877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283869
J. Bhadra, E. Trofimova, Leonard J. Giordano, M. Abadir
Multi-processor systems-on-chip pose a great challenge to validation due to their size and complexity. We approach the problem of MP SoC validation through a tool that uses a reusable scheme to effectively leverage a simulation-based abstraction scheme. Our tool checks an abstract representation of the system across traces obtained by simulating a system level implementation and analyzes the results for correctness. We have effectively used the tool on various live MP SoC design projects.
{"title":"A Trace-Driven Validation Methodology for Multi-Processor SOCS","authors":"J. Bhadra, E. Trofimova, Leonard J. Giordano, M. Abadir","doi":"10.1109/SOCC.2006.283869","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283869","url":null,"abstract":"Multi-processor systems-on-chip pose a great challenge to validation due to their size and complexity. We approach the problem of MP SoC validation through a tool that uses a reusable scheme to effectively leverage a simulation-based abstraction scheme. Our tool checks an abstract representation of the system across traces obtained by simulating a system level implementation and analyzes the results for correctness. We have effectively used the tool on various live MP SoC design projects.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121958118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283885
S. Provost, Bruno Lavigueur, G. Bois, G. Nicolescu
To reach current SoCs constraint of flexibility without loosing performance, system designers need to avoid custom logic and replace it by multiple processors and custom instruction extensions. In this paper, we bring a new codesign methodology which targets MPSoC comprising of multiple configurable processors. By applying this methodology to an MPEG-4 encoder we show that the approach gives a speedup factor that is almost linear with the number of processors.
{"title":"Integration of Configurable Processors in a Multiprocessor Platform","authors":"S. Provost, Bruno Lavigueur, G. Bois, G. Nicolescu","doi":"10.1109/SOCC.2006.283885","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283885","url":null,"abstract":"To reach current SoCs constraint of flexibility without loosing performance, system designers need to avoid custom logic and replace it by multiple processors and custom instruction extensions. In this paper, we bring a new codesign methodology which targets MPSoC comprising of multiple configurable processors. By applying this methodology to an MPEG-4 encoder we show that the approach gives a speedup factor that is almost linear with the number of processors.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131885283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283894
Joyce Yeung, H. Mahmoodi
Variation in transistor characteristics and particularly threshold voltage (Vt) has emerged as a major challenge for circuit design in scaled technologies. Process variations result in increased mismatch among neighboring transistors which can affect the correct functionality of circuits such as sense amplifiers. In this paper, we will analyze the impact of process variations on sense amplifier circuits in detail. We will explore statistical design and optimization techniques based on transistor sizing to improve the reliability of sense amplifiers under process variations. Furthermore, we will exploit dual Vt option to enhance the sense amplifier robustness. According to simulation results in a 70 nm process, by optimal transistor sizing and dual Vt assignment, failure probability of sense amplifiers can be greatly reduced (by more than 80%).
{"title":"Robust Sense Amplifier Design under Random Dopant Fluctuations in Nano-Scale CMOS Technologies","authors":"Joyce Yeung, H. Mahmoodi","doi":"10.1109/SOCC.2006.283894","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283894","url":null,"abstract":"Variation in transistor characteristics and particularly threshold voltage (Vt) has emerged as a major challenge for circuit design in scaled technologies. Process variations result in increased mismatch among neighboring transistors which can affect the correct functionality of circuits such as sense amplifiers. In this paper, we will analyze the impact of process variations on sense amplifier circuits in detail. We will explore statistical design and optimization techniques based on transistor sizing to improve the reliability of sense amplifiers under process variations. Furthermore, we will exploit dual Vt option to enhance the sense amplifier robustness. According to simulation results in a 70 nm process, by optimal transistor sizing and dual Vt assignment, failure probability of sense amplifiers can be greatly reduced (by more than 80%).","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124679670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283854
P. Lakshmikanthan, Karan Sahni, A. Nunez
Leakage power loss is a major concern as it drains the battery even when a circuit is completely idle. Efficient leakage control mechanisms are necessary to maximize battery life. In this paper, the design and characterization of an ultra-low power combinational CMOS standard cell library is presented. A novel technique that achieves cancellation of leakage effects in both the pull-up network (PUN) as well as the pull-down network (PDN) of CMOS cells is presented. A combination of high-VT and standard-VT sleep transistors is used for voltage balancing in the PUN and PDN paths. Experimental results show significant leakage power savings (average of 21X for a 180 nm process technology at 27degC) in CMOS library cells employing this sleep-circuitry when compared to standard CMOS cells.
{"title":"Design of Ultra-Low Power Combinational Standard Library Cells Using A Novel Leakage Reduction Methodology","authors":"P. Lakshmikanthan, Karan Sahni, A. Nunez","doi":"10.1109/SOCC.2006.283854","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283854","url":null,"abstract":"Leakage power loss is a major concern as it drains the battery even when a circuit is completely idle. Efficient leakage control mechanisms are necessary to maximize battery life. In this paper, the design and characterization of an ultra-low power combinational CMOS standard cell library is presented. A novel technique that achieves cancellation of leakage effects in both the pull-up network (PUN) as well as the pull-down network (PDN) of CMOS cells is presented. A combination of high-VT and standard-VT sleep transistors is used for voltage balancing in the PUN and PDN paths. Experimental results show significant leakage power savings (average of 21X for a 180 nm process technology at 27degC) in CMOS library cells employing this sleep-circuitry when compared to standard CMOS cells.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127129361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283843
Yuhua Chen
Wormhole routing has been widely adopted for network-on-chip (NoC). We demonstrate that the common belief that wormhole routing requires very little buffer space is no longer true when deployed in billion-transistor SoCs. We propose a Cell Switched NoC (CS-NoC) paradigm that requires less buffer space than wormhole routing. It has been demonstrated that cell switched network has higher throughput, lower latency than wormhole routing, and are less sensitive to bursty traffic. Therefore, CS-NoC is a promising candidate for billion-transistor SoCs.
{"title":"Cell Switched Network-on-Chip -- Candidate for Billion-Transistor System-on-Chips","authors":"Yuhua Chen","doi":"10.1109/SOCC.2006.283843","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283843","url":null,"abstract":"Wormhole routing has been widely adopted for network-on-chip (NoC). We demonstrate that the common belief that wormhole routing requires very little buffer space is no longer true when deployed in billion-transistor SoCs. We propose a Cell Switched NoC (CS-NoC) paradigm that requires less buffer space than wormhole routing. It has been demonstrated that cell switched network has higher throughput, lower latency than wormhole routing, and are less sensitive to bursty traffic. Therefore, CS-NoC is a promising candidate for billion-transistor SoCs.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116991260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283840
Hongjiang Song
A low power, small area receiver equalizer circuit based on novel threshold multiplexing (TMX) technique is presented. Simulation results based on the proposed sampler circuit and a 3-level 2-tap TMX equalizer circuit implementation show achievable 20~30 ps eye margin improvement for a 5 Gb/s high-speed serial I/O application. This circuit demonstrates a very low PVT sensitivity and extremely wideband operation, which is fully digital and highly scalable and therefore very suitable for SOC applications.
{"title":"Architecture and Implementation of Power and Area Efficient Receiver Equalization Circuit for High-Speed Serial Data Communication","authors":"Hongjiang Song","doi":"10.1109/SOCC.2006.283840","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283840","url":null,"abstract":"A low power, small area receiver equalizer circuit based on novel threshold multiplexing (TMX) technique is presented. Simulation results based on the proposed sampler circuit and a 3-level 2-tap TMX equalizer circuit implementation show achievable 20~30 ps eye margin improvement for a 5 Gb/s high-speed serial I/O application. This circuit demonstrates a very low PVT sensitivity and extremely wideband operation, which is fully digital and highly scalable and therefore very suitable for SOC applications.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117070723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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