Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283858
Imran Ahmed, T. Arslan
The trace back operation as used in Viterbi decoding is presented. The trace back is used for a new large constraint length, soft decision Viterbi decoder designed to be implemented reusing components of turbo decoding array. The Viterbi decoder can be reconfigured for standards such as CDMA2000, WCDMA (UMTS), ADSL, IEEE 802.11 and GSM. The proposed trace back operation supports all of these multiple standards. The Viterbi decoding is made reconfigurable between different trellis types, constraint lengths and rates that can be reconfigured for the desired standard. The reconfigurable fabric is implemented as a subset of turbo decoder array on a 180 nm UMC process technology.
{"title":"A Reconfigurable Viterbi Traceback for Implemenation on Turbo Decoding Array","authors":"Imran Ahmed, T. Arslan","doi":"10.1109/SOCC.2006.283858","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283858","url":null,"abstract":"The trace back operation as used in Viterbi decoding is presented. The trace back is used for a new large constraint length, soft decision Viterbi decoder designed to be implemented reusing components of turbo decoding array. The Viterbi decoder can be reconfigured for standards such as CDMA2000, WCDMA (UMTS), ADSL, IEEE 802.11 and GSM. The proposed trace back operation supports all of these multiple standards. The Viterbi decoding is made reconfigurable between different trellis types, constraint lengths and rates that can be reconfigured for the desired standard. The reconfigurable fabric is implemented as a subset of turbo decoder array on a 180 nm UMC process technology.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129893932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283860
Zhenyu Qi, Wei Huang, A. C. Cabe, Wenqian Wu, Yan Zhang, G. Rose, M. Stan
Power and thermal considerations are becoming limiting factors for SoC designs as technology scales down. In this paper, a design methodology targeting a low-power and temperature-aware system is proposed. Dynamic voltage scaling (DVS) and dynamic thermal management (DTM) techniques are included. In order to demonstrate its effectiveness, we present an ongoing SoC design project of an ultrasound medical image processor incorporating a computationally intensive image enhancement algorithm. In particular, we show how DVS and DTM are adopted. A novel adaptive body-bias circuit that mitigates thermal sensitivity of circuits is also introduced.
{"title":"A Design Methodology for a Low-Power, Temperature-Aware SoC Developed for Medical Image Processors","authors":"Zhenyu Qi, Wei Huang, A. C. Cabe, Wenqian Wu, Yan Zhang, G. Rose, M. Stan","doi":"10.1109/SOCC.2006.283860","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283860","url":null,"abstract":"Power and thermal considerations are becoming limiting factors for SoC designs as technology scales down. In this paper, a design methodology targeting a low-power and temperature-aware system is proposed. Dynamic voltage scaling (DVS) and dynamic thermal management (DTM) techniques are included. In order to demonstrate its effectiveness, we present an ongoing SoC design project of an ultrasound medical image processor incorporating a computationally intensive image enhancement algorithm. In particular, we show how DVS and DTM are adopted. A novel adaptive body-bias circuit that mitigates thermal sensitivity of circuits is also introduced.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115953273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283868
O. Adamo, S. Mohanty, E. Kougianos, M. Varanasi
Considerable amount of research is directed at putting biometric data in conventional forms of identification such as passports. However, putting biometric data in passports makes the data vulnerable to theft, causing privacy related issues. To address such issues, we present a new approach and architecture in the framework of a digital camera, conceptualized as a "Secure Digital Camera (SDC)". The SDC uses watermarking and encryption processes for image security and authentication. The Rijndael AES algorithm and a DCT-based visible watermarking algorithm were chosen for implementation in our camera. The proposed architectures were modeled, simulated and synthesized in Xilinx ISE.
{"title":"VLSI Architecture for Encryption and Watermarking Units Towards the Making of a Secure Camera","authors":"O. Adamo, S. Mohanty, E. Kougianos, M. Varanasi","doi":"10.1109/SOCC.2006.283868","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283868","url":null,"abstract":"Considerable amount of research is directed at putting biometric data in conventional forms of identification such as passports. However, putting biometric data in passports makes the data vulnerable to theft, causing privacy related issues. To address such issues, we present a new approach and architecture in the framework of a digital camera, conceptualized as a \"Secure Digital Camera (SDC)\". The SDC uses watermarking and encryption processes for image security and authentication. The Rijndael AES algorithm and a DCT-based visible watermarking algorithm were chosen for implementation in our camera. The proposed architectures were modeled, simulated and synthesized in Xilinx ISE.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121223198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283908
A. Naeemi, M. Bakir
Introduction Interconnects are considered as one of the grandest challenges facing gigaand tera-scale integration (GSI/TSI). One may define interconnects as media for energy transfer in a GSI chip including electrical, thermal and potentially optical energies (power, signal and thermal interconnects). At the chip level, interconnects have become the major component in the delay of critical paths, are the largest source of power dissipation, generate crosstalk and power supply noise, and cause reliability problems due to electromigration and fragile low-k materials. Additional constraints on the performance of GSI/TSI chips are imposed by today's inferior heat removal technologies (thermal interconnects), inadequate off-chip Input/Output (I/0) bandwidth and the challenges of delivering hundreds of amperes of power supply current with ever decreasing noise margins. In this tutorial, quantitative models will be presented for the physical limits of interconnects and promising solutions for addressing the 'interconnect problem' will be discussed.
{"title":"Chip-level and Input/Output Interconnects for Gigascale SOCs: Limits and Opportunities","authors":"A. Naeemi, M. Bakir","doi":"10.1109/SOCC.2006.283908","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283908","url":null,"abstract":"Introduction Interconnects are considered as one of the grandest challenges facing gigaand tera-scale integration (GSI/TSI). One may define interconnects as media for energy transfer in a GSI chip including electrical, thermal and potentially optical energies (power, signal and thermal interconnects). At the chip level, interconnects have become the major component in the delay of critical paths, are the largest source of power dissipation, generate crosstalk and power supply noise, and cause reliability problems due to electromigration and fragile low-k materials. Additional constraints on the performance of GSI/TSI chips are imposed by today's inferior heat removal technologies (thermal interconnects), inadequate off-chip Input/Output (I/0) bandwidth and the challenges of delivering hundreds of amperes of power supply current with ever decreasing noise margins. In this tutorial, quantitative models will be presented for the physical limits of interconnects and promising solutions for addressing the 'interconnect problem' will be discussed.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117344629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283839
A. Dinh, B. Pham
A filter was designed for use either in narrowband or UWB system by switching the function. In the NB function, the filter performs as a channel select filter at 5.25GHz with adjustable gain and BW. In the UWB function, the filter acts as an LNA from 3.6-10.1 GHz with the capacity of eliminating the 5.25GHz NB interference signal. The design uses the mainstream 0.18 mum CMOS technology. The filter consumes 27 mW at 1.8V supply and exhibits a good performance in both functions. This filter allows the same receiver front- end to provide NB or UWB service and reduces system complexity and cost.
通过开关功能，设计了窄带或超宽带系统中使用的滤波器。在NB功能中，该滤波器作为5.25GHz的通道选择滤波器，具有可调的增益和BW。在UWB功能中，滤波器作为3.6-10.1 GHz的LNA，具有消除5.25GHz NB干扰信号的能力。本设计采用主流的0.18 μ m CMOS技术。该滤波器在1.8V电源下功耗为27mw，在两种功能中均表现出良好的性能。该滤波器允许同一接收机前端同时提供NB或UWB业务，降低了系统的复杂性和成本。
{"title":"A Dual-Function Filter for 5.25GHZ Narrowband and 3.6GHZ-10.1GHZ Ultrawideband Systems","authors":"A. Dinh, B. Pham","doi":"10.1109/SOCC.2006.283839","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283839","url":null,"abstract":"A filter was designed for use either in narrowband or UWB system by switching the function. In the NB function, the filter performs as a channel select filter at 5.25GHz with adjustable gain and BW. In the UWB function, the filter acts as an LNA from 3.6-10.1 GHz with the capacity of eliminating the 5.25GHz NB interference signal. The design uses the mainstream 0.18 mum CMOS technology. The filter consumes 27 mW at 1.8V supply and exhibits a good performance in both functions. This filter allows the same receiver front- end to provide NB or UWB service and reduces system complexity and cost.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128172535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Automatic interface synthesis generates product FSM from interface FSMs of IP. But complicated interface FSM may lead to a very large product FSM which results in large interface circuits. So we propose a simplified interface FSM description scheme where transactions are represented based on transfers and several parameters. In addition, the interface circuit is generated by considering only those transactions which are involved in matching information. By virtue of matching information we could generate the interface circuits which may not be easy to generate with previous methods due to inability to consider the differences in characteristics of interface protocols of IP. Through experiments we observed that our description scheme helps reduce the size of interface circuits and our synthesis method correctly generates the interface circuits between IPs with different characteristics.
{"title":"Automatic Synthesis of Interface Circuits from Simplified IP Interface Protocols and Matching Information","authors":"ChangRyul Yun, Younghwan Bae, Hanjin Cho, Kyoung-Son Jhang","doi":"10.1109/SOCC.2006.283856","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283856","url":null,"abstract":"Automatic interface synthesis generates product FSM from interface FSMs of IP. But complicated interface FSM may lead to a very large product FSM which results in large interface circuits. So we propose a simplified interface FSM description scheme where transactions are represented based on transfers and several parameters. In addition, the interface circuit is generated by considering only those transactions which are involved in matching information. By virtue of matching information we could generate the interface circuits which may not be easy to generate with previous methods due to inability to consider the differences in characteristics of interface protocols of IP. Through experiments we observed that our description scheme helps reduce the size of interface circuits and our synthesis method correctly generates the interface circuits between IPs with different characteristics.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"416 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131964794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283906
M. Margala
In recent years, a growing class of SOCs has emerged for mobile applications, such as portable desktops, digital pens, audio- and video-based multimedia products, wireless communications and imaging systems, personal digital assistants, personal communicators and smart cards. These SOCs demand high-speed, high-throughput computations, complex functionalities and often real-time processing capabilities. The performance of these SOCs is mostly limited by lifetime of batteries. Thus, new design approaches and methodologies that produce more power-efficient and higher throughput designs are greatly desired. In recent years, the use of SIMD (single instruction multiple data) or MIMD (multiple instruction multiple data) architectures is spreading into the general DSP domain due to recent innovations that boost performance and flexibility of the architectures by several orders of magnitude. The Processor-in-Memory (PIM) environment provides a unique prospective because the impact of low-power techniques on performance is more sensitive in PIM than in standard RAM. The performance balancing in PIM architectures plays a critical role. Even though PIM concept is not new, recent breakthroughs pushed the application domain from traditional multimedia use to general signal processing use. This tutorial provides a unique overview and prospective of these recent developments to a much broader audience. The tutorial covers recent developments presented in literature and the most recent advances proposed by the author and his research group.
{"title":"Tutorial: RAM-based Circuits and Architectures for Multimedia and Signal Processing SOCs","authors":"M. Margala","doi":"10.1109/SOCC.2006.283906","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283906","url":null,"abstract":"In recent years, a growing class of SOCs has emerged for mobile applications, such as portable desktops, digital pens, audio- and video-based multimedia products, wireless communications and imaging systems, personal digital assistants, personal communicators and smart cards. These SOCs demand high-speed, high-throughput computations, complex functionalities and often real-time processing capabilities. The performance of these SOCs is mostly limited by lifetime of batteries. Thus, new design approaches and methodologies that produce more power-efficient and higher throughput designs are greatly desired. In recent years, the use of SIMD (single instruction multiple data) or MIMD (multiple instruction multiple data) architectures is spreading into the general DSP domain due to recent innovations that boost performance and flexibility of the architectures by several orders of magnitude. The Processor-in-Memory (PIM) environment provides a unique prospective because the impact of low-power techniques on performance is more sensitive in PIM than in standard RAM. The performance balancing in PIM architectures plays a critical role. Even though PIM concept is not new, recent breakthroughs pushed the application domain from traditional multimedia use to general signal processing use. This tutorial provides a unique overview and prospective of these recent developments to a much broader audience. The tutorial covers recent developments presented in literature and the most recent advances proposed by the author and his research group.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"33 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134055674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283834
Zahid Khan, T. Arslan, Scott MacDougall
This paper presents a real time programmable irregular low density parity check (LDPC) Encoder as specified in the IEEE P802.16E/D7 standard. The encoder is programmable for frame sizes from 576 to 2304 and for five different code rates. H matrix is efficiently generated and stored for a particular frame size and code rate. The encoder is implemented on SC140 Processor and different optimization techniques are applied to enhance the throughput. With SC140, a reduction of 2.6 times in the number of effective MAC operations has been achieved, with further reduction in cycle counts possible. A pipelined architecture is also presented for possible ASIC or FPGA implementation.
{"title":"A Real Time Programmable Encoder for Low Density Parity Check Code as specified in the IEEE P802.16E/D7 Standard and its Efficient Implementation on a DSP Processor","authors":"Zahid Khan, T. Arslan, Scott MacDougall","doi":"10.1109/SOCC.2006.283834","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283834","url":null,"abstract":"This paper presents a real time programmable irregular low density parity check (LDPC) Encoder as specified in the IEEE P802.16E/D7 standard. The encoder is programmable for frame sizes from 576 to 2304 and for five different code rates. H matrix is efficiently generated and stored for a particular frame size and code rate. The encoder is implemented on SC140 Processor and different optimization techniques are applied to enhance the throughput. With SC140, a reduction of 2.6 times in the number of effective MAC operations has been achieved, with further reduction in cycle counts possible. A pipelined architecture is also presented for possible ASIC or FPGA implementation.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126385106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283835
Shuli Gao, D. Al-Khalili, N. Chabini, Pierre Langlois
This paper presents an efficient design methodology and a systematic approach for the implementation of squaring of complex numbers and their conjugate, using small-size embedded multipliers. Various benchmarks were tested for operands with size ranging from 19 to 85 bits targeting Xilinx Spartan-3 FPGA. Our proposed approach was compared with the traditional technique. The results illustrate that our design approach is very efficient in terms of timing and area saving. For the complex squarer, the combinational delay is reduced by an average of 16.8% and area saving, in terms of 4-inputs LUTs, is about 27.2%. For the complex conjugate realization, combinational delay and area are reduced by about 18.6% and 41.6%, respectively.
{"title":"Efficient FPGA-Based Realization of Complex Squarer and Complex Conjugate using Embedded Multipliers","authors":"Shuli Gao, D. Al-Khalili, N. Chabini, Pierre Langlois","doi":"10.1109/SOCC.2006.283835","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283835","url":null,"abstract":"This paper presents an efficient design methodology and a systematic approach for the implementation of squaring of complex numbers and their conjugate, using small-size embedded multipliers. Various benchmarks were tested for operands with size ranging from 19 to 85 bits targeting Xilinx Spartan-3 FPGA. Our proposed approach was compared with the traditional technique. The results illustrate that our design approach is very efficient in terms of timing and area saving. For the complex squarer, the combinational delay is reduced by an average of 16.8% and area saving, in terms of 4-inputs LUTs, is about 27.2%. For the complex conjugate realization, combinational delay and area are reduced by about 18.6% and 41.6%, respectively.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125506097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283910
N. Dakwala
Nanometer circuits and fabrication process both are becoming increasingly complex at the same time. The very nature of silicon defects continue to evolve with these ground shift and are now focused on timing, signal integrity and process variations [1]. It is not enough to simply have full scan ATPG vectors. There will be diagnostics built into the ATPG tools to fall back on when the ATPG tests fail, but these don't help debug timing defects and when the fail test data is compressed [2]. When yields fall and there is a danger to miss the TTM, TTP, TTx windows, the SOC integrator must be ready for quick debug. Silicon Debug has evolved to be a process that requires planning, tools, and engineering resources. The basic DFT principles of controllability and observability need to be extended to isolate a failing IP. Last but not the least, both SOC IP provider and integrator need to support diagnostics or Failure Analysis to zero-in on a defect. Nanometer fails require a paradigm shift, from Design ¿ for-Test to Design-for-Debug. This tutorial will help the attendees recognize, enjoin and improve the Debug paradigm.
{"title":"Silicon Debug and DFT for SOC IP","authors":"N. Dakwala","doi":"10.1109/SOCC.2006.283910","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283910","url":null,"abstract":"Nanometer circuits and fabrication process both are becoming increasingly complex at the same time. The very nature of silicon defects continue to evolve with these ground shift and are now focused on timing, signal integrity and process variations [1]. It is not enough to simply have full scan ATPG vectors. There will be diagnostics built into the ATPG tools to fall back on when the ATPG tests fail, but these don't help debug timing defects and when the fail test data is compressed [2]. When yields fall and there is a danger to miss the TTM, TTP, TTx windows, the SOC integrator must be ready for quick debug. Silicon Debug has evolved to be a process that requires planning, tools, and engineering resources. The basic DFT principles of controllability and observability need to be extended to isolate a failing IP. Last but not the least, both SOC IP provider and integrator need to support diagnostics or Failure Analysis to zero-in on a defect. Nanometer fails require a paradigm shift, from Design ¿ for-Test to Design-for-Debug. This tutorial will help the attendees recognize, enjoin and improve the Debug paradigm.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121076273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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