Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283844
J. Maunu, J. Marku, M. Laiho, A. Paasio
We present an on-chip measurement circuit for current source calibration by combination selection in current and future CMOS technologies. The circuit evaluates the output current values and selects a current that ensures 99% mismatch compensation accuracy with 4 sigma yield.
{"title":"An On-Chip Measurement Circuit for Calibration by Combination Selection","authors":"J. Maunu, J. Marku, M. Laiho, A. Paasio","doi":"10.1109/SOCC.2006.283844","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283844","url":null,"abstract":"We present an on-chip measurement circuit for current source calibration by combination selection in current and future CMOS technologies. The circuit evaluates the output current values and selects a current that ensures 99% mismatch compensation accuracy with 4 sigma yield.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124885263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SOCC.2006.283838
Hongjiang Song, S. R. Naqvi, B. Bakkaloglu
Design of integrated very low intermediate frequency (VLIF) RF receivers with better than 35 dB image rejection (IR) usually requires detection and calibration of l/Q channel mismatches less than 0.1 dB in amplitude and 1.8 degree in phase. A mismatch amplification technique for improving detection sensitivity is presented in this paper. The proposed mismatch transfer function technique provides an effective method to calculate internal amplitude and phase mismatches from the measured EVM at the receiver output. Experimental data from an integrated VLIF receiver test chip is used to demonstrate the theory. By utilizing this technique, an l/Q mismatch measurement resolution as low as 0.01 dB in amplitude and 0.18 degree in phase is achieved.
{"title":"I/Q-Channel Mismatch Transfer and Amplification Effects and Applications to the Measurement and Calibration of Integrated VLIF RF Receivers","authors":"Hongjiang Song, S. R. Naqvi, B. Bakkaloglu","doi":"10.1109/SOCC.2006.283838","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283838","url":null,"abstract":"Design of integrated very low intermediate frequency (VLIF) RF receivers with better than 35 dB image rejection (IR) usually requires detection and calibration of l/Q channel mismatches less than 0.1 dB in amplitude and 1.8 degree in phase. A mismatch amplification technique for improving detection sensitivity is presented in this paper. The proposed mismatch transfer function technique provides an effective method to calculate internal amplitude and phase mismatches from the measured EVM at the receiver output. Experimental data from an integrated VLIF receiver test chip is used to demonstrate the theory. By utilizing this technique, an l/Q mismatch measurement resolution as low as 0.01 dB in amplitude and 0.18 degree in phase is achieved.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127764857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SOCC.2006.283842
Phi-Hung Pham, Yogendera Kumar, Chulwoo Kim
Compact switch architecture and its fast path-setup scheme for circuit-switched on chip network adopting 4times4 torus topology has been presented. Proposed switch has been synthesized and analyzed using 0.13 mum CMOS process technology. Performance evaluation shows considerable energy efficiency and almost 5 times smaller area compared to the other switches.
提出了采用4倍4环面拓扑的片上电路交换网络的紧凑开关结构及其快速路径设置方案。采用0.13 μ m CMOS工艺技术对所提出的开关进行了合成和分析。性能评估显示出相当高的能源效率和几乎比其他开关小5倍的面积。
{"title":"A Compact and High Performance Switch for Circuit-Switched Network-On-Chip","authors":"Phi-Hung Pham, Yogendera Kumar, Chulwoo Kim","doi":"10.1109/SOCC.2006.283842","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283842","url":null,"abstract":"Compact switch architecture and its fast path-setup scheme for circuit-switched on chip network adopting 4times4 torus topology has been presented. Proposed switch has been synthesized and analyzed using 0.13 mum CMOS process technology. Performance evaluation shows considerable energy efficiency and almost 5 times smaller area compared to the other switches.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129724982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SOCC.2006.283883
Ming-Ching Lu, Meng-Chen Wu, Hung-Ming Chen, I. Jiang
Using voltage island methodology to reduce power consumption for system-on-a-chip (SoC) designs has become more and more popular recently. Currently this approach has been considered either in system-level architecture or post-placement stage. Since hierarchical design and reusable intellectual property (IP) are widely used, it is necessary to optimize floorplanning/placement methodology considering voltage islands generation to solve power and critical path delay problems. In this paper, we propose a floorplanning methodology considering voltage islands generation and performance constraints. Our method is flexible and can be extended to hierarchical design. The experimental results on some MCNC benchmarks show that our method is effective in meeting performance constraints and simultaneously considers the tradeoff between power routing cost and the assignment of supply voltage in modules.
{"title":"Performance Constraints Aware Voltage Islands Generation in SoC Floorplan Design","authors":"Ming-Ching Lu, Meng-Chen Wu, Hung-Ming Chen, I. Jiang","doi":"10.1109/SOCC.2006.283883","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283883","url":null,"abstract":"Using voltage island methodology to reduce power consumption for system-on-a-chip (SoC) designs has become more and more popular recently. Currently this approach has been considered either in system-level architecture or post-placement stage. Since hierarchical design and reusable intellectual property (IP) are widely used, it is necessary to optimize floorplanning/placement methodology considering voltage islands generation to solve power and critical path delay problems. In this paper, we propose a floorplanning methodology considering voltage islands generation and performance constraints. Our method is flexible and can be extended to hierarchical design. The experimental results on some MCNC benchmarks show that our method is effective in meeting performance constraints and simultaneously considers the tradeoff between power routing cost and the assignment of supply voltage in modules.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129869292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ICSICT.2006.306270
Chung-Yuan Chen, Jia-Hong Wang, T. Sun
This paper presents the design of receiver circuits for flat-plane application. Due to the differential transmission technique and the low voltage swing, mini-LVDS (low-voltage differential signaling) allows high transmission speeds and low power consumption at the same time. In the proposed receiver, high transmission speed with the minimum common-mode and differential voltage at the input for mini-LVDS application was achieved. The circuit was designed in a 3.3-V 0.35- mum CMOS technology, and the transmission operations is more than 500 Mb/s with random data patterns. The total power consumption is 3.5 mW.
本文介绍了平面应用的接收电路设计。由于差分传输技术和低电压摆幅，mini-LVDS(低压差分信号)可以同时实现高传输速度和低功耗。在该接收机中，实现了以最小的共模和差分电压输入的高传输速度，适用于微型lvds应用。电路采用3.3 v 0.35 μ m CMOS技术设计，传输速度大于500mb /s，数据模式随机。总功耗为3.5 mW。
{"title":"A Novel Mini-LVDS Receiver in 0.35-um CMOS","authors":"Chung-Yuan Chen, Jia-Hong Wang, T. Sun","doi":"10.1109/ICSICT.2006.306270","DOIUrl":"https://doi.org/10.1109/ICSICT.2006.306270","url":null,"abstract":"This paper presents the design of receiver circuits for flat-plane application. Due to the differential transmission technique and the low voltage swing, mini-LVDS (low-voltage differential signaling) allows high transmission speeds and low power consumption at the same time. In the proposed receiver, high transmission speed with the minimum common-mode and differential voltage at the input for mini-LVDS application was achieved. The circuit was designed in a 3.3-V 0.35- mum CMOS technology, and the transmission operations is more than 500 Mb/s with random data patterns. The total power consumption is 3.5 mW.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132902504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose a novel SoC design methodology referred to as multi-project system-on-a-chip (MP-SoC), which can integrate multiple heterogeneous SoC design projects into a single chip such that the total silicon prototyping cost for these projects can be greatly reduced due to the sharing of a common SoC platform. The design flows for the system architecture, individual IP blocks, as well as the logic and physical implementations of MP-SoC are explored. The isolation mechanism to prevent interference among the IPs and the arbitration mechanism to grant the bus usage for master IPs are also presented. A test chip named MP-SoC-l that includes 8 SoC projects from 4 universities was selected as a demonstration example for verifying the MP-SoC design concept. This chip is designed and implemented in TSMC 0.13 mum CMOS generic logic process technology, and the total silicon area for MP-SoC-l test chip is 4950 mum x 4938 mum. Experimental results of MP-SoC-l test chip show that all projects are successfully implemented in the common platform and 82.91% silicon area is saved with this MP- SoC methodology as compared with the case where multiple SoC projects are fabricated individually.
在本文中，我们提出了一种新的SoC设计方法，称为多项目片上系统(MP-SoC)，它可以将多个异构SoC设计项目集成到单个芯片中，这样由于共享公共SoC平台，这些项目的总硅原型成本可以大大降低。探讨了系统架构、单个IP块以及MP-SoC的逻辑和物理实现的设计流程。提出了防止ip间干扰的隔离机制和允许主ip使用总线的仲裁机制。选取了包含4所大学8个SoC项目的MP-SoC- 1测试芯片作为验证MP-SoC设计概念的演示示例。该芯片采用台积电0.13 μ m CMOS通用逻辑工艺设计实现，mp - soc - 1测试芯片的总硅面积为4950 μ m x 4938 μ m。MP-SoC- 1测试芯片的实验结果表明，与单独制造多个SoC项目的情况相比，采用MP-SoC方法可以成功地在通用平台上实现所有项目，节省了82.91%的硅面积。
{"title":"Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping","authors":"Chun-Ming Huang, Kuen-Jong Lee, Chih-Chyau Yang, Wen-Hsiang Hu, Shi-Shen Wang, Jeng-Bin Chen, Chi-Shi Chen, Lan-Da Van, Chien‐Ming Wu, W. Tsai, Jing-Yang Jou","doi":"10.1109/SOCC.2006.283867","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283867","url":null,"abstract":"In this paper, we propose a novel SoC design methodology referred to as multi-project system-on-a-chip (MP-SoC), which can integrate multiple heterogeneous SoC design projects into a single chip such that the total silicon prototyping cost for these projects can be greatly reduced due to the sharing of a common SoC platform. The design flows for the system architecture, individual IP blocks, as well as the logic and physical implementations of MP-SoC are explored. The isolation mechanism to prevent interference among the IPs and the arbitration mechanism to grant the bus usage for master IPs are also presented. A test chip named MP-SoC-l that includes 8 SoC projects from 4 universities was selected as a demonstration example for verifying the MP-SoC design concept. This chip is designed and implemented in TSMC 0.13 mum CMOS generic logic process technology, and the total silicon area for MP-SoC-l test chip is 4950 mum x 4938 mum. Experimental results of MP-SoC-l test chip show that all projects are successfully implemented in the common platform and 82.91% silicon area is saved with this MP- SoC methodology as compared with the case where multiple SoC projects are fabricated individually.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133873764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SOCC.2006.283881
Huang-Liang Chen, Hung-Ming Chen
Clock power dissipation has become a significant issue since it occupies around half of the total system power. Due to high working frequency in modern system designs, the transition time of the clock signal is extremely short. In order to keep up with this trend and to use less wire area, a large number of buffers have to be inserted in the network. As a consequence, short-circuit power of the clock buffers is no longer negligible. In this paper, we introduce a methodology which can be applied in global clock tree synthesis to achieve low short-circuit power. It is based on the analysis of any given buffer library in manipulating buffer transition time and hierarchical clustering of loads during buffer insertion. The experimental results are encouraging. Since there are very few works on gate/buffer sizing or buffer library analysis to overcome clocking power problem, we compare our approach with a greedy buffer sizing approach and obtain 13.7% clock power saving for a 10,000 flip-flop design under user-specified clock skew constraints.
{"title":"On Achieving Low-Power SoC Clock Tree Synthesis by Transition Time Planning via Buffer Library Study","authors":"Huang-Liang Chen, Hung-Ming Chen","doi":"10.1109/SOCC.2006.283881","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283881","url":null,"abstract":"Clock power dissipation has become a significant issue since it occupies around half of the total system power. Due to high working frequency in modern system designs, the transition time of the clock signal is extremely short. In order to keep up with this trend and to use less wire area, a large number of buffers have to be inserted in the network. As a consequence, short-circuit power of the clock buffers is no longer negligible. In this paper, we introduce a methodology which can be applied in global clock tree synthesis to achieve low short-circuit power. It is based on the analysis of any given buffer library in manipulating buffer transition time and hierarchical clustering of loads during buffer insertion. The experimental results are encouraging. Since there are very few works on gate/buffer sizing or buffer library analysis to overcome clocking power problem, we compare our approach with a greedy buffer sizing approach and obtain 13.7% clock power saving for a 10,000 flip-flop design under user-specified clock skew constraints.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132843703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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