Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283893
B. Mesgarzadeh, A. Alvandpour
This paper presents a low-power small-area DLL-based frequency multiplier. Instead of using edge combiner-based clock synthesis scheme, the proposed frequency multiplier utilizes a ring oscillator, which is controlled by a DLL. An injection-locked slave ring oscillator is used for jitter suppression. The implementation of the proposed structure in 130-nm CMOS occupies an area of 0.02 mm2. It operates in the frequency range of 100 MHz to 1.5 GHz while consuming 24-mW power from a 1.2-V supply at 1.5 GHz. The measured output phase noise at 1.5 GHz is -100.1 dBc/Hz at a 4-MHz frequency offset.
{"title":"A 24-mW 0.02-mm2 1.5-GHz DLL-Based Frequency Multiplier in 130-nm CMOS","authors":"B. Mesgarzadeh, A. Alvandpour","doi":"10.1109/SOCC.2006.283893","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283893","url":null,"abstract":"This paper presents a low-power small-area DLL-based frequency multiplier. Instead of using edge combiner-based clock synthesis scheme, the proposed frequency multiplier utilizes a ring oscillator, which is controlled by a DLL. An injection-locked slave ring oscillator is used for jitter suppression. The implementation of the proposed structure in 130-nm CMOS occupies an area of 0.02 mm2. It operates in the frequency range of 100 MHz to 1.5 GHz while consuming 24-mW power from a 1.2-V supply at 1.5 GHz. The measured output phase noise at 1.5 GHz is -100.1 dBc/Hz at a 4-MHz frequency offset.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121786002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283846
Seok-Oh Yun, Hyung-Joun Yoo
A reconfigurable CMOS power amplifier for WPAN application is designed in CMOS 0.25 mum technology. It is composed of driver stage, power stage, interstage matching, and output matching stages. Power amplifier can be operated in various frequencies by controlling interstage matching and has the characteristic at required frequencies. The proposed power amplifier has 42-57% power added efficiency and 21.8-27.5 dB gain characteristic at frequencies of 0.9-2.4 GHz with 20 dBm output power.
{"title":"A Reconfigurable CMOS Power Amplifier Operating from 0.9 TO 2.4 GHZ for WPAN Application","authors":"Seok-Oh Yun, Hyung-Joun Yoo","doi":"10.1109/SOCC.2006.283846","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283846","url":null,"abstract":"A reconfigurable CMOS power amplifier for WPAN application is designed in CMOS 0.25 mum technology. It is composed of driver stage, power stage, interstage matching, and output matching stages. Power amplifier can be operated in various frequencies by controlling interstage matching and has the characteristic at required frequencies. The proposed power amplifier has 42-57% power added efficiency and 21.8-27.5 dB gain characteristic at frequencies of 0.9-2.4 GHz with 20 dBm output power.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127926155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283851
Hosun Shin, Naeun Zang, Juho Kim
Statistical power optimization using the probabilistic delay model is introduced in this paper. We propose a new method for power optimization that uses path balancing based on stochastic estimation of glitch in statistical static timing analysis (SSTA). The proposed method estimates the probability of glitch occurrence using tightness probability of each node in timing graph. In addition, we propose efficient gate sizing technique for glitch reduction using accurate calculation of sizing effect in delay considering probability of glitch occurrence. The efficiency of the proposed method has been verified on ISCAS 85 benchmark circuits with 0.16 mum model parameters. Experimental results show up to 8.6% of accuracy improvement in glitch estimation and 9.5% of optimization improvement.
{"title":"Stochastic Glitch Estimation and Path Balancing for Statistical Optimization","authors":"Hosun Shin, Naeun Zang, Juho Kim","doi":"10.1109/SOCC.2006.283851","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283851","url":null,"abstract":"Statistical power optimization using the probabilistic delay model is introduced in this paper. We propose a new method for power optimization that uses path balancing based on stochastic estimation of glitch in statistical static timing analysis (SSTA). The proposed method estimates the probability of glitch occurrence using tightness probability of each node in timing graph. In addition, we propose efficient gate sizing technique for glitch reduction using accurate calculation of sizing effect in delay considering probability of glitch occurrence. The efficiency of the proposed method has been verified on ISCAS 85 benchmark circuits with 0.16 mum model parameters. Experimental results show up to 8.6% of accuracy improvement in glitch estimation and 9.5% of optimization improvement.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133407058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283911
T. Seceleanu, A. Jantsch, H. Tenhunen
Currently, the semiconductor industry continues to develop and implement smaller technology nodes, creating the premises for increasingly more powerful applications to find support within the limits of single chip boundaries. Moreover, as technological sizes continue to decrease, interconnect becomes one of the main design constraints, which dominates the power consumption and degrades the performance due to its poor scalability. Thus, some of the major problems in actually delivering complex system-on-chip designs may be identified as: a) global interconnects turn un-manageable (electromigration, voltage drop, on-chip variations, noise constraints etc), interconnect dominates the chip's cost and performance; b) the inability of the designer to track the Moore curve, resulting in "bad" design flows, requiring rework and iteration of design cycles; c) dependability issues caused by effects at submicron technological figures, mixed-signal coupling, availability of pre-designed components to match the specific requirements, etc; d) power consumption, power and clock distribution, scalability. Some of the above problems are tackled by reuse and intellectual property (IP) based design. At the same time, alternative architectures are brought to light, in order to support ever increasing requirements concerning design features like performance, power consumption, adaptability, reusability. In general, these novel architectures try to extract maximum of benefits from current technologies, with respect to the mentioned design characteristics, while also providing a smooth transition to future ones. In this tutorial, we concentrate on two architectural solutions to the above stated challenges. We address issues related to segmented bus and network on-chip systems, starting from motivational background, continuing with technological requirements and possibilities, communication mechanisms, towards design methodologies and application perspectives.
{"title":"On-Chip Distributed Architectures","authors":"T. Seceleanu, A. Jantsch, H. Tenhunen","doi":"10.1109/SOCC.2006.283911","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283911","url":null,"abstract":"Currently, the semiconductor industry continues to develop and implement smaller technology nodes, creating the premises for increasingly more powerful applications to find support within the limits of single chip boundaries. Moreover, as technological sizes continue to decrease, interconnect becomes one of the main design constraints, which dominates the power consumption and degrades the performance due to its poor scalability. Thus, some of the major problems in actually delivering complex system-on-chip designs may be identified as: a) global interconnects turn un-manageable (electromigration, voltage drop, on-chip variations, noise constraints etc), interconnect dominates the chip's cost and performance; b) the inability of the designer to track the Moore curve, resulting in \"bad\" design flows, requiring rework and iteration of design cycles; c) dependability issues caused by effects at submicron technological figures, mixed-signal coupling, availability of pre-designed components to match the specific requirements, etc; d) power consumption, power and clock distribution, scalability. Some of the above problems are tackled by reuse and intellectual property (IP) based design. At the same time, alternative architectures are brought to light, in order to support ever increasing requirements concerning design features like performance, power consumption, adaptability, reusability. In general, these novel architectures try to extract maximum of benefits from current technologies, with respect to the mentioned design characteristics, while also providing a smooth transition to future ones. In this tutorial, we concentrate on two architectural solutions to the above stated challenges. We address issues related to segmented bus and network on-chip systems, starting from motivational background, continuing with technological requirements and possibilities, communication mechanisms, towards design methodologies and application perspectives.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130269942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283837
Hongjiang Song
A general approach to the analysis and design of polyphase filters is presented. This method, which is based on the symmetry property and the polyphase signal constraint of the VLSI polyphase filter circuit structures, provides a systematic and significantly simplified path for the analysis and design of various types of VLSI polyphase filters.
{"title":"A General Method to VLSI Polyphase Filter Analysis and Design for Integrated RF Applications","authors":"Hongjiang Song","doi":"10.1109/SOCC.2006.283837","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283837","url":null,"abstract":"A general approach to the analysis and design of polyphase filters is presented. This method, which is based on the symmetry property and the polyphase signal constraint of the VLSI polyphase filter circuit structures, provides a systematic and significantly simplified path for the analysis and design of various types of VLSI polyphase filters.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123777154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283888
A. Garg, P. Dubey
Embedded memory yield dominates manufacturing yield of the chip and yield enhancement techniques for embedded memories are important for entire SoC yield increase. Laser fuses and anti fuses are two commonly used mechanisms for hard repair and they consume a lot of area. Analysis based upon yield prediction methods as well as silicon yield database shows that putting fuse to repair all the memories on the chip is not worth the expense, when only few fuse bits are needed. In this paper, we present the background for fuse reduction (cost analysis) and propose methodology to compress total number of fuses to repair the memories such that cost reduction through hard repair circuitry is maximized. The idea is to take into consideration factors like memory yield, fuse yield and repair logic yield, together with the number of memories on chip, to finally decide the fuse compression ratio.
{"title":"Fuse Area Reduction Based on Quantitative Yield Analysis and Effective Chip Cost","authors":"A. Garg, P. Dubey","doi":"10.1109/SOCC.2006.283888","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283888","url":null,"abstract":"Embedded memory yield dominates manufacturing yield of the chip and yield enhancement techniques for embedded memories are important for entire SoC yield increase. Laser fuses and anti fuses are two commonly used mechanisms for hard repair and they consume a lot of area. Analysis based upon yield prediction methods as well as silicon yield database shows that putting fuse to repair all the memories on the chip is not worth the expense, when only few fuse bits are needed. In this paper, we present the background for fuse reduction (cost analysis) and propose methodology to compress total number of fuses to repair the memories such that cost reduction through hard repair circuitry is maximized. The idea is to take into consideration factors like memory yield, fuse yield and repair logic yield, together with the number of memories on chip, to finally decide the fuse compression ratio.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121927197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283898
E. Demircan
With the development of new sub micron very large scale integration (VLSI) technologies the importance of interconnect parasitics on delay and noise has been in an ever increasing trend [1]. Consequently, the variations in interconnect parameters have a larger impact on final timing and functional yield of the product. Therefore, it is necessary to handle process variations as accurately as possible in layout parasitic extraction (LPE), static timing (ST) and signal integrity (SI) in deep sub-micron designs. In this paper we analyze the sources of process variation that induce interconnect parasitic variations. We present the relatively important ones through the usage of a response surface model (RSM). It was found that, in addition to metal thickness and width variation, damaged dielectric regions on the side of the metal lines are important contributions to cross-talk. We demonstrate the importance of accounting for the correlation between parameters for a given interconnect line such as interconnect line resistance and thickness. Finally we present a Monte Carlo (MC) methodology based on the RSM which can significantly reduce separation of corners and lead to tighter product specs and hence smaller die area and lower power.
{"title":"Effects of Interconnect Process Variations on Signal Integrity","authors":"E. Demircan","doi":"10.1109/SOCC.2006.283898","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283898","url":null,"abstract":"With the development of new sub micron very large scale integration (VLSI) technologies the importance of interconnect parasitics on delay and noise has been in an ever increasing trend [1]. Consequently, the variations in interconnect parameters have a larger impact on final timing and functional yield of the product. Therefore, it is necessary to handle process variations as accurately as possible in layout parasitic extraction (LPE), static timing (ST) and signal integrity (SI) in deep sub-micron designs. In this paper we analyze the sources of process variation that induce interconnect parasitic variations. We present the relatively important ones through the usage of a response surface model (RSM). It was found that, in addition to metal thickness and width variation, damaged dielectric regions on the side of the metal lines are important contributions to cross-talk. We demonstrate the importance of accounting for the correlation between parameters for a given interconnect line such as interconnect line resistance and thickness. Finally we present a Monte Carlo (MC) methodology based on the RSM which can significantly reduce separation of corners and lead to tighter product specs and hence smaller die area and lower power.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126614379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283870
Juergen Saalmueller, J. Würtz
Complex industry automation as well as complex compute nodes like high-end servers require an infrastructure for maintenance and control. An off-the-shelf embedded controller is usually the first choice for such purposes. This approach is challenged for complex applications by the fact that a large amount of distributed industry standard interfaces has to be controlled and realtime responses have to be provided. In our paper we show a concept solving the above challenges. Our solution is based on an embedded PowerPC 440* controller that allows for flexible attachment and control of hundreds of industry standard interfaces like digital I/O, I2C, JTAG, RS232/422 etc. The solution further allows a redundant implementation of controllers for fail save applications. This approach was implemented first in a set of IBM servers and can be generalized to other application areas like compute clusters or industry automation. We describe the challenges in complex applications for system control, show our solutions on a system level and finally describe how a concrete SoC chip is realized in PowerPC* CoreConnect* technology.
{"title":"Embedded Controllers for Solving Complex Industry Applications","authors":"Juergen Saalmueller, J. Würtz","doi":"10.1109/SOCC.2006.283870","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283870","url":null,"abstract":"Complex industry automation as well as complex compute nodes like high-end servers require an infrastructure for maintenance and control. An off-the-shelf embedded controller is usually the first choice for such purposes. This approach is challenged for complex applications by the fact that a large amount of distributed industry standard interfaces has to be controlled and realtime responses have to be provided. In our paper we show a concept solving the above challenges. Our solution is based on an embedded PowerPC 440* controller that allows for flexible attachment and control of hundreds of industry standard interfaces like digital I/O, I2C, JTAG, RS232/422 etc. The solution further allows a redundant implementation of controllers for fail save applications. This approach was implemented first in a set of IBM servers and can be generalized to other application areas like compute clusters or industry automation. We describe the challenges in complex applications for system control, show our solutions on a system level and finally describe how a concrete SoC chip is realized in PowerPC* CoreConnect* technology.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129596859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283831
W. Yan, H. Zimmermann
This paper proposes a fully differential opamp implemented in 120 nm digital CMOS technology, with rail-to-rail input common-mode range, realized by a novel approach of constant small- and large-signal behavior control. The small-signal response is improved to an extremely slim deviation of 2.4%. Also a new class-AB rail-to-rail output stage is designed, targeting at high drive capability down to 33Omega resistive load, high power transfer efficiency and linearity. A modified measurement circuitry for fully differential opamps is introduced as well.
{"title":"A 120nm CMOS Fully Differential Rail-to-Rail I/O Opamp with Highly Constant Signal Behavior","authors":"W. Yan, H. Zimmermann","doi":"10.1109/SOCC.2006.283831","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283831","url":null,"abstract":"This paper proposes a fully differential opamp implemented in 120 nm digital CMOS technology, with rail-to-rail input common-mode range, realized by a novel approach of constant small- and large-signal behavior control. The small-signal response is improved to an extremely slim deviation of 2.4%. Also a new class-AB rail-to-rail output stage is designed, targeting at high drive capability down to 33Omega resistive load, high power transfer efficiency and linearity. A modified measurement circuitry for fully differential opamps is introduced as well.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122701228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/SOCC.2006.283855
K. Chow, D. Abercrombie, M. Basel
Like design for manufacturing (DFM), design for reliability (DFR) of a chip identifies design features that are potentially vulnerable to various physical effects that can degrade circuit performance. The difference is that DFR attempts to model long-term effects, such as electromigration. Tools extract design information (resistances and current densities) and apply the data to simulation tools to estimate the degree of reliability. The weakness in this methodology is that these extraction technologies assume that the "as drawn" feature is a good representation of the "as manufactured" chip. DFM has shown that individual features on the "as manufactured" chip can vary dramatically from the intended layout in both critical dimension and thickness. The technologies developed to identify and characterize these DFM variations need to be incorporated into the DFR tools to accurately predict the long-term life of SoC nanometer designs.
{"title":"Method for Managing Electromigration in SOC'S When Designing for Both Reliability and Manufacturing","authors":"K. Chow, D. Abercrombie, M. Basel","doi":"10.1109/SOCC.2006.283855","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283855","url":null,"abstract":"Like design for manufacturing (DFM), design for reliability (DFR) of a chip identifies design features that are potentially vulnerable to various physical effects that can degrade circuit performance. The difference is that DFR attempts to model long-term effects, such as electromigration. Tools extract design information (resistances and current densities) and apply the data to simulation tools to estimate the degree of reliability. The weakness in this methodology is that these extraction technologies assume that the \"as drawn\" feature is a good representation of the \"as manufactured\" chip. DFM has shown that individual features on the \"as manufactured\" chip can vary dramatically from the intended layout in both critical dimension and thickness. The technologies developed to identify and characterize these DFM variations need to be incorporated into the DFR tools to accurately predict the long-term life of SoC nanometer designs.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"289 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117303052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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