Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824042
M. Weng, Jiin-Chuan Wu
A fully integrated CMOS temperature sensor is presented. The design uses parasitic substrate bipolar transistors as a temperature sensor. The temperature and reference signals are first converted into current signals by a voltage-to-current converter and then converted to a digital output by a sigma-delta analog-to-digital converter. Fabricated in a 0.6 /spl mu/m CMOS process, this circuit occupies an active area of 0.7 mm/sup 2/. In the temperature range from 40 to 130/spl deg/C, the error is /spl plusmn/1.5/spl deg/C after one-point calibration.
{"title":"A temperature sensor in 0.6 /spl mu/m CMOS technology","authors":"M. Weng, Jiin-Chuan Wu","doi":"10.1109/APASIC.1999.824042","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824042","url":null,"abstract":"A fully integrated CMOS temperature sensor is presented. The design uses parasitic substrate bipolar transistors as a temperature sensor. The temperature and reference signals are first converted into current signals by a voltage-to-current converter and then converted to a digital output by a sigma-delta analog-to-digital converter. Fabricated in a 0.6 /spl mu/m CMOS process, this circuit occupies an active area of 0.7 mm/sup 2/. In the temperature range from 40 to 130/spl deg/C, the error is /spl plusmn/1.5/spl deg/C after one-point calibration.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131715987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824041
Y. Hung, Bin-Da Liu
A linear mean-absolute-difference (MAD) cell is designed. Based on this cell and winner-take-all circuit, we propose a parallel analog vector-quantizer for pattern recognition. The experimental circuit is constituted by one input pattern and 16 template patterns with 16 elements. This circuit had been simulated using 0.5 /spl mu/m CMOS technology by HSPICE. The results show that a pattern can be correctly identified if the difference of the MAD distance metric is larger or smaller than 100 mV. Simulation results demonstrate 250 ns identified time and 16 mW power dissipation for single 3.3 V voltage supply.
设计了一种线性平均绝对差分(MAD)单元。基于该单元和赢者通吃电路，我们提出了一种用于模式识别的并行模拟矢量量化器。实验电路由一个输入模式和16个模板模式组成，包含16个元件。利用HSPICE软件采用0.5 /spl μ m CMOS技术对该电路进行了仿真。结果表明，当MAD距离度量的差值大于或小于100 mV时，可以正确识别出一种模式。仿真结果表明，单个3.3 V电压电源的识别时间为250 ns，功耗为16 mW。
{"title":"A CMOS analog vector quantizer for pattern recognition","authors":"Y. Hung, Bin-Da Liu","doi":"10.1109/APASIC.1999.824041","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824041","url":null,"abstract":"A linear mean-absolute-difference (MAD) cell is designed. Based on this cell and winner-take-all circuit, we propose a parallel analog vector-quantizer for pattern recognition. The experimental circuit is constituted by one input pattern and 16 template patterns with 16 elements. This circuit had been simulated using 0.5 /spl mu/m CMOS technology by HSPICE. The results show that a pattern can be correctly identified if the difference of the MAD distance metric is larger or smaller than 100 mV. Simulation results demonstrate 250 ns identified time and 16 mW power dissipation for single 3.3 V voltage supply.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"518 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127616469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Micro-electro-mechanical circuit for 30 W high power Piezoelectric Transformer (PT) with modeling and characterizations to be used in Electronic Ballast (EB) is designed for the first time. Significant parameters at 77.6 KHz of frequency and 87 mA of low input current result in excellent efficiency of 84% and high voltage gain of 0.9 for 30 W high power for electronic ballast, which can save much energy and be a great domestic asset. Our proposed PT circuit with proper optimization of circuit parameters can also enhance further power and efficiency for future high power applications.
{"title":"High power 30 W and high efficiency 80% piezoelectric transformer for EB","authors":"Jin-H. Chung, Seung-Min Lee, Mike-Myung-Ok Lee, Yang-Ho Moon","doi":"10.1109/APASIC.1999.824045","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824045","url":null,"abstract":"Micro-electro-mechanical circuit for 30 W high power Piezoelectric Transformer (PT) with modeling and characterizations to be used in Electronic Ballast (EB) is designed for the first time. Significant parameters at 77.6 KHz of frequency and 87 mA of low input current result in excellent efficiency of 84% and high voltage gain of 0.9 for 30 W high power for electronic ballast, which can save much energy and be a great domestic asset. Our proposed PT circuit with proper optimization of circuit parameters can also enhance further power and efficiency for future high power applications.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129839783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824043
Zheng Zheng, Raminder, J. Singh, U. Sridhar, Tan Khen-Sang
This paper described a low cost universal sensor signal condition ASIC for bridge type sensors. The ASIC was produced with standard double metal, double poly 0.8 /spl mu/m silicon CMOS process and can correct the sensor's offset, offset temperature coefficient, sensitivity and sensitivity temperature coefficient. We have used this ASIC to signal condition silicon piezo-resistive pressure sensor to a total error of less than /spl plusmn/1% of the sensor's full scale output (FSO) in a temperature range of -40/spl deg/C to 125/spl deg/C. The ASIC can provide a low cost solution for the calibration of bridge type sensors such as pressure sensor, Hall effect sensor and MR/GMR sensor.
{"title":"A universal sensor signal conditioning ASIC","authors":"Zheng Zheng, Raminder, J. Singh, U. Sridhar, Tan Khen-Sang","doi":"10.1109/APASIC.1999.824043","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824043","url":null,"abstract":"This paper described a low cost universal sensor signal condition ASIC for bridge type sensors. The ASIC was produced with standard double metal, double poly 0.8 /spl mu/m silicon CMOS process and can correct the sensor's offset, offset temperature coefficient, sensitivity and sensitivity temperature coefficient. We have used this ASIC to signal condition silicon piezo-resistive pressure sensor to a total error of less than /spl plusmn/1% of the sensor's full scale output (FSO) in a temperature range of -40/spl deg/C to 125/spl deg/C. The ASIC can provide a low cost solution for the calibration of bridge type sensors such as pressure sensor, Hall effect sensor and MR/GMR sensor.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"178 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129640209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824124
H. Yoshizawa, T. Tsuruta, N. Kumamoto, M. Kurita
This paper describes the architecture of the "MSPM: Multimedia Signal Processor with embedded Memory". It has been developed to evaluate the architectural effects of 0.35-micron embedded DRAM technologies on the performance. The chip has achieved 24 times the performance of an ordinary RISC processor at the same frequency, and also ten times the performance of an ordinary 16 bit DSP. The improvement has been made possible by the following architectural characteristics: direct-memory-referring instruction sets; SIMD-type-parallel-executing features; byte-aligned-word-access features; and multi-instruction migrating features. The MSPM achieved 800 MOPS@66 MHz with 1.1 Gbyte/s bandwidth. Integration of a 16 Mb DRAM with 128 bit data bus is also reported.
{"title":"A high performance DSP architecture \"MSPM\" for digital image processing using embedded DRAM ASIC technologies","authors":"H. Yoshizawa, T. Tsuruta, N. Kumamoto, M. Kurita","doi":"10.1109/APASIC.1999.824124","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824124","url":null,"abstract":"This paper describes the architecture of the \"MSPM: Multimedia Signal Processor with embedded Memory\". It has been developed to evaluate the architectural effects of 0.35-micron embedded DRAM technologies on the performance. The chip has achieved 24 times the performance of an ordinary RISC processor at the same frequency, and also ten times the performance of an ordinary 16 bit DSP. The improvement has been made possible by the following architectural characteristics: direct-memory-referring instruction sets; SIMD-type-parallel-executing features; byte-aligned-word-access features; and multi-instruction migrating features. The MSPM achieved 800 MOPS@66 MHz with 1.1 Gbyte/s bandwidth. Integration of a 16 Mb DRAM with 128 bit data bus is also reported.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117023138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824065
Kyung-Saeng Kim, Dong-Jae Lee, H. Yoo, Kwyro Lee
We propose a new motion estimator with two types of embedded memory banks. Its overall system efficiency is extremely high for full-search block match algorithm (FBMA). The results show that its power-area product is nearly 1.13 and switching-overhead is low between FBMA and random-search block match algorithm in the case of CCIR-601 format.
{"title":"Low-power full-search motion estimator architecture suitable for random-block match","authors":"Kyung-Saeng Kim, Dong-Jae Lee, H. Yoo, Kwyro Lee","doi":"10.1109/APASIC.1999.824065","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824065","url":null,"abstract":"We propose a new motion estimator with two types of embedded memory banks. Its overall system efficiency is extremely high for full-search block match algorithm (FBMA). The results show that its power-area product is nearly 1.13 and switching-overhead is low between FBMA and random-search block match algorithm in the case of CCIR-601 format.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122746654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824082
Seongmo Park, Inhag Park, J. Cha, Hanjin Cho
In this paper, we describe the interface specification and core block design methods for a run length coder of video compression application. It offers high performance and many features to meet multimedia, and digital video applications. We designed the VLSI architecture of the run length coder using VHDL. This design can achieve a high performance for the video coder and is based on H.263 Recommendation. The format of the outputs is compatible with the stream of the variable length coding. The run length coder is implemented by the register transfer level (RTL) of VHDL. The designed block is synthesized by Compass synthesis with 0.5 /spl mu/m CMOS, 3.3 V, technology and reuse as core IP (Intellectual Property) of H.263 and MPEG4 application. The run length coder block contains 4,000 logic gates and a total 1,536 bits of static RAM. The fully synchronous design allows for fast operation while maintaining a low gate count. The core will reuse for multimedia system and digital video applications.
本文描述了一种视频压缩应用中运行长度编码器的接口规范和核心模块设计方法。它提供了高性能和许多功能，以满足多媒体和数字视频应用。我们使用VHDL设计了运行长度编码器的VLSI架构。本设计是基于H.263标准的高性能视频编码器。输出格式与变长编码流兼容。运行长度编码器由VHDL的寄存器传输层(RTL)实现。设计的模块采用Compass合成技术，采用0.5 /spl μ l /m CMOS, 3.3 V，技术和重用作为H.263和MPEG4应用的核心IP(知识产权)。运行长度编码块包含4,000个逻辑门和总共1,536位静态RAM。完全同步设计允许快速操作，同时保持低栅极计数。该核心将用于多媒体系统和数字视频应用。
{"title":"Reusable design of run length coder for image compression application","authors":"Seongmo Park, Inhag Park, J. Cha, Hanjin Cho","doi":"10.1109/APASIC.1999.824082","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824082","url":null,"abstract":"In this paper, we describe the interface specification and core block design methods for a run length coder of video compression application. It offers high performance and many features to meet multimedia, and digital video applications. We designed the VLSI architecture of the run length coder using VHDL. This design can achieve a high performance for the video coder and is based on H.263 Recommendation. The format of the outputs is compatible with the stream of the variable length coding. The run length coder is implemented by the register transfer level (RTL) of VHDL. The designed block is synthesized by Compass synthesis with 0.5 /spl mu/m CMOS, 3.3 V, technology and reuse as core IP (Intellectual Property) of H.263 and MPEG4 application. The run length coder block contains 4,000 logic gates and a total 1,536 bits of static RAM. The fully synchronous design allows for fast operation while maintaining a low gate count. The core will reuse for multimedia system and digital video applications.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122819799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824026
K. Shimamura, S. Yamaguchi, N. Kanekawa, N. Miyazaki, H. Yamada, Y. Takahashi, T. Hirotsu, K. Tomobe, K. Satoh, T. Hotta, R. Fujita
A chip level redundant self-checking fail-safe microprocessor has been developed using a 0.35 /spl mu/m CMOS embedded gate array. The microprocessor integrates two synthesizable processor cores and a self-checking comparator in a single chip. A full-custom processor core was transformed into each of the synthesizable cores for this purpose. Design methodologies suitable for reusing synthesizable processor cores has also been developed. Developed synthesizable processor cores and design methodologies reduce the cost of process migration of the chip. Migrating to the newer process improves the performance of the developed microprocessor with low development cost.
采用0.35 /spl μ m CMOS嵌入式门阵列，研制了一种芯片级冗余自检故障安全微处理器。该微处理器在单个芯片中集成了两个可合成的处理器内核和一个自检比较器。为此，将一个完全自定义的处理器核心转换为每个可合成的核心。适合重用可合成处理器内核的设计方法也得到了发展。开发的可合成处理器内核和设计方法降低了芯片的工艺迁移成本。迁移到较新的工艺可以提高已开发微处理器的性能，同时降低开发成本。
{"title":"A fail-safe microprocessor using dual synthesizable processor cores","authors":"K. Shimamura, S. Yamaguchi, N. Kanekawa, N. Miyazaki, H. Yamada, Y. Takahashi, T. Hirotsu, K. Tomobe, K. Satoh, T. Hotta, R. Fujita","doi":"10.1109/APASIC.1999.824026","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824026","url":null,"abstract":"A chip level redundant self-checking fail-safe microprocessor has been developed using a 0.35 /spl mu/m CMOS embedded gate array. The microprocessor integrates two synthesizable processor cores and a self-checking comparator in a single chip. A full-custom processor core was transformed into each of the synthesizable cores for this purpose. Design methodologies suitable for reusing synthesizable processor cores has also been developed. Developed synthesizable processor cores and design methodologies reduce the cost of process migration of the chip. Migrating to the newer process improves the performance of the developed microprocessor with low development cost.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117087843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824088
Jing-Jou Tang
In this paper, a novel circuit design that can detect faults resulting in intermediate voltage values is presented. This design can also be used to detect slow transition faults and the metastability of a circuit under test. The power supply of this circuit is only 1 V. Thus it can be used for not only conventional circuits but also the low voltage (LV) circuits.
{"title":"A 1 V built-in intermediate voltage sensor","authors":"Jing-Jou Tang","doi":"10.1109/APASIC.1999.824088","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824088","url":null,"abstract":"In this paper, a novel circuit design that can detect faults resulting in intermediate voltage values is presented. This design can also be used to detect slow transition faults and the metastability of a circuit under test. The power supply of this circuit is only 1 V. Thus it can be used for not only conventional circuits but also the low voltage (LV) circuits.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116921457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824098
Yi-Cheng Chang, E.W. Greeneich
A wide range phase-locked loop (PLL) circuit using a coarse-steering technique is designed for implementation in MOSIS 1.2 /spl mu/m CMOS technology. The entire PLL circuit has been simulated and can obtain lock in over a frequency range of 160-440 MHz with a 3 volt power supply on HSPICE.
{"title":"Wide operating-range acquisition technique for PLL circuits","authors":"Yi-Cheng Chang, E.W. Greeneich","doi":"10.1109/APASIC.1999.824098","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824098","url":null,"abstract":"A wide range phase-locked loop (PLL) circuit using a coarse-steering technique is designed for implementation in MOSIS 1.2 /spl mu/m CMOS technology. The entire PLL circuit has been simulated and can obtain lock in over a frequency range of 160-440 MHz with a 3 volt power supply on HSPICE.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123533519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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