Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824047
Keun-Sup Lee, N. Jeong, K. Bang, D. Youn
This paper presents a real-time MPEG-2 AAC decoding system, which can decode 2-channel main profile MPEG-2 AAC bitstream. The system consists of a simple fixed-point programmable DSP core and two hardwired logic modules, which perform Huffman decoding and prediction respectively. To verify the designed decoding system, simulator model has been developed based on C-language. For the verification of decoding algorithm, the 16-bit PCM output of the system was compared with the result of the floating-point simulation, and the result showed the maximum of 2-bit difference. For the verification of real-time decoding, the number of the clock cycles in the worst simulation case was compared with that of the required clock cycles for the real-time decoding, and the result verified the real-time decoding of designed system.
{"title":"A VLSI implementation of MPEG-2 AAC decoder system","authors":"Keun-Sup Lee, N. Jeong, K. Bang, D. Youn","doi":"10.1109/APASIC.1999.824047","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824047","url":null,"abstract":"This paper presents a real-time MPEG-2 AAC decoding system, which can decode 2-channel main profile MPEG-2 AAC bitstream. The system consists of a simple fixed-point programmable DSP core and two hardwired logic modules, which perform Huffman decoding and prediction respectively. To verify the designed decoding system, simulator model has been developed based on C-language. For the verification of decoding algorithm, the 16-bit PCM output of the system was compared with the result of the floating-point simulation, and the result showed the maximum of 2-bit difference. For the verification of real-time decoding, the number of the clock cycles in the worst simulation case was compared with that of the required clock cycles for the real-time decoding, and the result verified the real-time decoding of designed system.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125732815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824055
Hee-Cheol Choi, Hojin Park, Sungbo Hwang, Shin-Kyu Bae, Jae-Whui Kim, P. Chung
A 1.5 V 10-bit 25 MSPS pipelined analog-to-digital converter was implemented using 0.25 /spl mu/m CMOS technology. The converter is based on low-voltage two-stage opamps and a current reference generator for low-voltage operation. It also employs a novel dual-mode voltage booster to achieve good low-voltage operation as well as cost reduction. The current reference generator adopts a newly proposed self charge-pumping architecture with ring oscillator that keeps a reference current constant regardless of temperature and voltage variations under the low-voltage environment. The ADC occupies a die area of 2.21 mm/sup 2/ (1700 um/spl times/1300 um) and dissipates 45 mW at 25 MHz clock rate with 1.5 V single supply voltage in measurement result. Typical differential nonlinearity (DNL) and integral nonlinearity (INL) are /spl plusmn/0.44 LSB and /spl plusmn/0.82 LSB, respectively.
{"title":"A 1.5 V 10-bit 25 MSPS pipelined A/D converter","authors":"Hee-Cheol Choi, Hojin Park, Sungbo Hwang, Shin-Kyu Bae, Jae-Whui Kim, P. Chung","doi":"10.1109/APASIC.1999.824055","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824055","url":null,"abstract":"A 1.5 V 10-bit 25 MSPS pipelined analog-to-digital converter was implemented using 0.25 /spl mu/m CMOS technology. The converter is based on low-voltage two-stage opamps and a current reference generator for low-voltage operation. It also employs a novel dual-mode voltage booster to achieve good low-voltage operation as well as cost reduction. The current reference generator adopts a newly proposed self charge-pumping architecture with ring oscillator that keeps a reference current constant regardless of temperature and voltage variations under the low-voltage environment. The ADC occupies a die area of 2.21 mm/sup 2/ (1700 um/spl times/1300 um) and dissipates 45 mW at 25 MHz clock rate with 1.5 V single supply voltage in measurement result. Typical differential nonlinearity (DNL) and integral nonlinearity (INL) are /spl plusmn/0.44 LSB and /spl plusmn/0.82 LSB, respectively.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124674262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824084
Y. Shyu, Jiin-Chuan Wu
An on-chip oscillator with small frequency variation in a digital 0.6 /spl mu/m CMOS technology is described. The oscillator utilizes a bias technique to compensate for the influences on the oscillation frequency caused by both temperature and process variations. No external components are needed in the oscillator. Simulation results show that the frequency of the proposed oscillator has a peak variation of /spl plusmn/6.8% for all process corners and a temperature range of 120/spl deg/C. The oscillator is measured to operate at a center frequency of 680 kHz and have a peak variation of /spl plusmn/4.7% over 29 sample chips in two different lots and a temperature range of 35/spl deg/C to 115/spl deg/C. As a comparison, a conventional inverter chain oscillator is made on the same chip. The frequency variation of the conventional inverter chain is /spl plusmn/14.6%.
{"title":"A process and temperature compensated ring oscillator","authors":"Y. Shyu, Jiin-Chuan Wu","doi":"10.1109/APASIC.1999.824084","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824084","url":null,"abstract":"An on-chip oscillator with small frequency variation in a digital 0.6 /spl mu/m CMOS technology is described. The oscillator utilizes a bias technique to compensate for the influences on the oscillation frequency caused by both temperature and process variations. No external components are needed in the oscillator. Simulation results show that the frequency of the proposed oscillator has a peak variation of /spl plusmn/6.8% for all process corners and a temperature range of 120/spl deg/C. The oscillator is measured to operate at a center frequency of 680 kHz and have a peak variation of /spl plusmn/4.7% over 29 sample chips in two different lots and a temperature range of 35/spl deg/C to 115/spl deg/C. As a comparison, a conventional inverter chain oscillator is made on the same chip. The frequency variation of the conventional inverter chain is /spl plusmn/14.6%.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129331876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents an analog-signal processor chip design for its application on the wireless bio-signal transmission system. The processor is used to handle the physiological signal such as the electrocardiography (ECG), electroencephalography (EEG), or the electromyography (EMG), and so on. All analog blocks in the processor chip are realized in a 0.5 /spl mu/m double-poly and double-metal CMOS technology. The measured results show the processor chip can capture the bio-signal with the frequency range of 0.5 Hz to 220 Hz, and has a total voltage gain of 54 dB, good agreement has been found between computer simulation and measured performance. Compared to the on-board prototype system, on-chip processor system can minimize the hardware area and reduce the product cost.
{"title":"Analog integrated circuit design for the wireless bio-signal transmission system","authors":"Chih-Jen Yen, Wen-Yaw Chung, Kang-Ping Lin, Cheng-Lun Tsai, Shing-Hao Lee, Te-Shin Chen","doi":"10.1109/APASIC.1999.824099","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824099","url":null,"abstract":"This paper presents an analog-signal processor chip design for its application on the wireless bio-signal transmission system. The processor is used to handle the physiological signal such as the electrocardiography (ECG), electroencephalography (EEG), or the electromyography (EMG), and so on. All analog blocks in the processor chip are realized in a 0.5 /spl mu/m double-poly and double-metal CMOS technology. The measured results show the processor chip can capture the bio-signal with the frequency range of 0.5 Hz to 220 Hz, and has a total voltage gain of 54 dB, good agreement has been found between computer simulation and measured performance. Compared to the on-board prototype system, on-chip processor system can minimize the hardware area and reduce the product cost.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116754860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824075
Young San Seo, Jae-Hee You
This paper presents a motion estimation processor that has regular and simple structure and achieves 100% hardware utilization without image data fill time. It can compute half-pel precision estimation and I/O bottleneck is eliminated using a small distributed on-chip image memory. The number of processing elements is scalable according to the degree of parallel processing and throughput requirements. It has been designed and verified with C++ and VHDL.
{"title":"A VLSI design of hierarchical search motion estimation processor chip","authors":"Young San Seo, Jae-Hee You","doi":"10.1109/APASIC.1999.824075","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824075","url":null,"abstract":"This paper presents a motion estimation processor that has regular and simple structure and achieves 100% hardware utilization without image data fill time. It can compute half-pel precision estimation and I/O bottleneck is eliminated using a small distributed on-chip image memory. The number of processing elements is scalable according to the degree of parallel processing and throughput requirements. It has been designed and verified with C++ and VHDL.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116781304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/APASIC.1999.824109
M. Lin, H. Lin, C. Chen, S. Jou
This paper describes a digitally programmable DC-DC voltage down converter (VDC) with a new structure of pulse width modulation (PWM) circuit. The PWM circuit is constructed by a cascaded digitally controlled oscillator (DCO) delay cells and provides two control words to select the operating frequency and duty cycle respectively. The VDC was implemented with a 0.6-/spl mu/m triple-metal CMOS process on 1000/spl times/1000 /spl mu/m/sup 2/ core size. The simulation results show that it can convert +5 V input voltage to +2/spl sim/+5 V output voltage in the 50 /spl mu/s settling time.
{"title":"Digitally programmable DC-DC voltage down converter","authors":"M. Lin, H. Lin, C. Chen, S. Jou","doi":"10.1109/APASIC.1999.824109","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824109","url":null,"abstract":"This paper describes a digitally programmable DC-DC voltage down converter (VDC) with a new structure of pulse width modulation (PWM) circuit. The PWM circuit is constructed by a cascaded digitally controlled oscillator (DCO) delay cells and provides two control words to select the operating frequency and duty cycle respectively. The VDC was implemented with a 0.6-/spl mu/m triple-metal CMOS process on 1000/spl times/1000 /spl mu/m/sup 2/ core size. The simulation results show that it can convert +5 V input voltage to +2/spl sim/+5 V output voltage in the 50 /spl mu/s settling time.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116633294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/APASIC.1999.824039
C. Jeong, W. Park, Tack-Don Dan, Shin-Dug Kim
Geometry processing in three dimensional (3D) graphics application is characterized by a large amount of inherent parallelism and floating-point instructions. This processing is accelerated with multiple geometry processors that have fast floating-point unit (FPU). There are many design alternatives in the geometry processor design that are suitable for multiple configurations. With these alternatives, designers have to consider design cost and complexity. In this paper design considerations and trade-off factors are evaluated with floating-point arithmetic unit organization and implementation. First, geometry-processing steps are described and consideration factors are summarized to find design considerations of FPU for geometry processing Then, based on these design considerations, implementation trade-off factors are evaluated. In addition, floating-point division algorithms and their implementation are evaluated in the point of trade-off. Among the design alternatives for floating-point arithmetic units, the best organization with minimal investment is separate adder/multiplier and radix-16 SRT divider. And split register file permits area saving and instruction issue rate increase. In the processing of whole geometry pipeline stages, 45.5% of execution time improvement is achieved with this configuration. It is a cost-effective design. In addition, execution time and throughput trade-off must be considered for high-end 3D graphics system design.
{"title":"Cost/performance trade-off in floating-point unit design for 3D geometry processor","authors":"C. Jeong, W. Park, Tack-Don Dan, Shin-Dug Kim","doi":"10.1109/APASIC.1999.824039","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824039","url":null,"abstract":"Geometry processing in three dimensional (3D) graphics application is characterized by a large amount of inherent parallelism and floating-point instructions. This processing is accelerated with multiple geometry processors that have fast floating-point unit (FPU). There are many design alternatives in the geometry processor design that are suitable for multiple configurations. With these alternatives, designers have to consider design cost and complexity. In this paper design considerations and trade-off factors are evaluated with floating-point arithmetic unit organization and implementation. First, geometry-processing steps are described and consideration factors are summarized to find design considerations of FPU for geometry processing Then, based on these design considerations, implementation trade-off factors are evaluated. In addition, floating-point division algorithms and their implementation are evaluated in the point of trade-off. Among the design alternatives for floating-point arithmetic units, the best organization with minimal investment is separate adder/multiplier and radix-16 SRT divider. And split register file permits area saving and instruction issue rate increase. In the processing of whole geometry pipeline stages, 45.5% of execution time improvement is achieved with this configuration. It is a cost-effective design. In addition, execution time and throughput trade-off must be considered for high-end 3D graphics system design.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115858017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/APASIC.1999.824112
Jing-Jou Tang, Bin-Da Liu, Jeng Ron Wu
In this paper, we propose a unipolar dynamic driving scheme and a 30-V 16-output row/column driving circuit for polymer stabilized cholesteric texture (PSCT) liquid crystal displays using 2-/spl mu/m HBiMOS process. The proposed chip size is 10 mm/sup 2/. Simulation results show that the total power dissipation is 37.8 mW.
{"title":"A 30-V row/column driver for PSCT LCD using high-voltage BiMOS process","authors":"Jing-Jou Tang, Bin-Da Liu, Jeng Ron Wu","doi":"10.1109/APASIC.1999.824112","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824112","url":null,"abstract":"In this paper, we propose a unipolar dynamic driving scheme and a 30-V 16-output row/column driving circuit for polymer stabilized cholesteric texture (PSCT) liquid crystal displays using 2-/spl mu/m HBiMOS process. The proposed chip size is 10 mm/sup 2/. Simulation results show that the total power dissipation is 37.8 mW.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"4 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124321971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/APASIC.1999.824114
Young-Sik Kim, T. Han, Shin-Dug Kim
This paper proposes a new memory access control scheme called delayed precharge scheme, to improve the performance of on-chip DRAM's by increasing the DRAM page hit ratio for multiple block accesses. This architecture shows higher performance than the hierarchical multi-bank architecture as well as the conventional bank architecture by execution-driven simulation. The proposed scheme could reduce the cache refill time and CPI obtained by the conventional DRAM by 26.9% and 6.2% respectively in typical applications.
{"title":"A memory access system for merged memory with logic LSIs","authors":"Young-Sik Kim, T. Han, Shin-Dug Kim","doi":"10.1109/APASIC.1999.824114","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824114","url":null,"abstract":"This paper proposes a new memory access control scheme called delayed precharge scheme, to improve the performance of on-chip DRAM's by increasing the DRAM page hit ratio for multiple block accesses. This architecture shows higher performance than the hierarchical multi-bank architecture as well as the conventional bank architecture by execution-driven simulation. The proposed scheme could reduce the cache refill time and CPI obtained by the conventional DRAM by 26.9% and 6.2% respectively in typical applications.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122451993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/APASIC.1999.824062
M. Sheu, Sh-Chi Tsai, Ming-Der Shieh
This paper presents a switching-tree coding (STC) algorithm to re-encode the output codevector indexes after vector quantization. Based on the connections in the index neighborhood, we construct three binary trees to allocate the optimal variable-length noiseless code for each index. Simulation results indicate that this algorithm can improve coding efficiency without introducing any extra coding distortion, as compared to conventional memoryless VQ. Besides, according the new algorithm, an efficient VLSI architecture is also derived under the requirements of low cost and high performance. The gate counts of encoder and decoder are about 5000 and 4800 respectively. After Verilog simulation, the clock rate of the whole architecture is 50 MHz by using 0.6 /spl mu/m CMOS IP3M technology.
{"title":"A lossless index coding algorithm and VLSI design for vector quantization","authors":"M. Sheu, Sh-Chi Tsai, Ming-Der Shieh","doi":"10.1109/APASIC.1999.824062","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824062","url":null,"abstract":"This paper presents a switching-tree coding (STC) algorithm to re-encode the output codevector indexes after vector quantization. Based on the connections in the index neighborhood, we construct three binary trees to allocate the optimal variable-length noiseless code for each index. Simulation results indicate that this algorithm can improve coding efficiency without introducing any extra coding distortion, as compared to conventional memoryless VQ. Besides, according the new algorithm, an efficient VLSI architecture is also derived under the requirements of low cost and high performance. The gate counts of encoder and decoder are about 5000 and 4800 respectively. After Verilog simulation, the clock rate of the whole architecture is 50 MHz by using 0.6 /spl mu/m CMOS IP3M technology.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114666179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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