Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824029
Tsung-Sum Lee, Chun-Chieh Liu
A third-order Chebyshev low-pass filter with automatic tuning based on new BiCMOS low-voltage triode transconductors for applications in the very-high-frequency (VHF) range is presented. Simulation results of the filter and the automatic tuning circuitry are described. The complete system operates with supply voltages of /spl plusmn/1.5 V. The filter achieves a 42.8 MHz cutoff frequency. The filter total harmonic distortion (THD) stays lower than 1% for an input signal up to 1.061 V/sub pp/ at 8 MHz frequency. The dynamic range of the filter is 60 dB.
{"title":"Design techniques for low-voltage VHF BiCMOS G/sub m/-C filters with automatic tuning","authors":"Tsung-Sum Lee, Chun-Chieh Liu","doi":"10.1109/APASIC.1999.824029","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824029","url":null,"abstract":"A third-order Chebyshev low-pass filter with automatic tuning based on new BiCMOS low-voltage triode transconductors for applications in the very-high-frequency (VHF) range is presented. Simulation results of the filter and the automatic tuning circuitry are described. The complete system operates with supply voltages of /spl plusmn/1.5 V. The filter achieves a 42.8 MHz cutoff frequency. The filter total harmonic distortion (THD) stays lower than 1% for an input signal up to 1.061 V/sub pp/ at 8 MHz frequency. The dynamic range of the filter is 60 dB.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115585464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824115
Chi-Weon Yoon, Yon-Kyun Im, Seon‐Ho Han, H. Yoo, T. Jung
We propose a Virtual Pipelined Memory (VPM) architecture for fast row-cycle by using a top-down design approach. A pipeline structure in the row path and integration of multiple SRAM buffers enable fast row-cycle. VPM shows higher performance than that of SDRAM by about 40% and that of VCM by about 20%. VPM maintains backward compatibility with a conventional SDRAM interface and consumes low power by adopting partial cell core activation.
{"title":"A VPM (Virtual Pipelined Memory) architecture for a fast row-cycle DRAM","authors":"Chi-Weon Yoon, Yon-Kyun Im, Seon‐Ho Han, H. Yoo, T. Jung","doi":"10.1109/APASIC.1999.824115","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824115","url":null,"abstract":"We propose a Virtual Pipelined Memory (VPM) architecture for fast row-cycle by using a top-down design approach. A pipeline structure in the row path and integration of multiple SRAM buffers enable fast row-cycle. VPM shows higher performance than that of SDRAM by about 40% and that of VCM by about 20%. VPM maintains backward compatibility with a conventional SDRAM interface and consumes low power by adopting partial cell core activation.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"304 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122775325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824083
Doh-Kyung Kim, Ki-Won Kwon, Jong-Chan Choi, Chul-Dong Lee
This paper presents how we use a soft Peripheral Component Interconnect (PCI) Intellectual Property (IP) for converting an Industry Standard Architecture (ISA) bus to a PCI bus in the personal computer (PC) data protection application specific integrated circuit (ASIC) design. To save design time and achieve a more efficient design, we use a verified PCI IP. The PCI IP was a soft IP and designed by Pheonix Technology. The total blocks consist of 3 major blocks: PCI IP block, user interface block, and PC data protection block. We verified the functioning of the PC data protection circuit with a supplied test environment by Pheonix Technology. So we built in a test environment easily. We cooperated with the ASIC foundry and IP vendor for IP integration using PCI IP. The operating frequency is 33 MHz. The size of EEPROM is 64 Kbytes and the size of the data bus is 32 bits. We fabricated the chip in a 0.5 /spl mu/m CMOS technology since the EEPROM was made by 0.5 /spl mu/m CMOS technology.
{"title":"Reusable intellectual property cores in PC data protection ASIC design","authors":"Doh-Kyung Kim, Ki-Won Kwon, Jong-Chan Choi, Chul-Dong Lee","doi":"10.1109/APASIC.1999.824083","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824083","url":null,"abstract":"This paper presents how we use a soft Peripheral Component Interconnect (PCI) Intellectual Property (IP) for converting an Industry Standard Architecture (ISA) bus to a PCI bus in the personal computer (PC) data protection application specific integrated circuit (ASIC) design. To save design time and achieve a more efficient design, we use a verified PCI IP. The PCI IP was a soft IP and designed by Pheonix Technology. The total blocks consist of 3 major blocks: PCI IP block, user interface block, and PC data protection block. We verified the functioning of the PC data protection circuit with a supplied test environment by Pheonix Technology. So we built in a test environment easily. We cooperated with the ASIC foundry and IP vendor for IP integration using PCI IP. The operating frequency is 33 MHz. The size of EEPROM is 64 Kbytes and the size of the data bus is 32 bits. We fabricated the chip in a 0.5 /spl mu/m CMOS technology since the EEPROM was made by 0.5 /spl mu/m CMOS technology.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129639631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824038
R. Lin, A. Botha, K. Kerr, G. Brown
This paper presents a novel parallel inner product processor architecture. The proposed processor has the following features: (1) it can be easily reconfigured for computing inner products of input arrays with four or more types of structures. Typically, each input array may contain 64 8-bit items, or 16 16-bit items, or 4 32-bit items, or 1 64-bit item, with items in unsigned or 2's complement form; (2) it can be pipelined to produce inner products efficiently,; (3) it has a compact VLSI area with very simple reconfigurable components. The processor mainly consists of an array of 8/spl times/8 or 4/spl times/4 small multipliers plus two or three arrays of adders. The total amount of hardware is comparable to a single 64/spl times/64 array multiplier; (4) The whole network is reconfigured through using a few control bits for the desired computations, and the reconfiguration can be done dynamically; (5) The design is highly regular and modular, and most parts of the network are symmetric and repeatable. (6) A set of high performance parallel counter circuits are utilized in the design.
{"title":"An inner product processor design using novel parallel counter circuits","authors":"R. Lin, A. Botha, K. Kerr, G. Brown","doi":"10.1109/APASIC.1999.824038","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824038","url":null,"abstract":"This paper presents a novel parallel inner product processor architecture. The proposed processor has the following features: (1) it can be easily reconfigured for computing inner products of input arrays with four or more types of structures. Typically, each input array may contain 64 8-bit items, or 16 16-bit items, or 4 32-bit items, or 1 64-bit item, with items in unsigned or 2's complement form; (2) it can be pipelined to produce inner products efficiently,; (3) it has a compact VLSI area with very simple reconfigurable components. The processor mainly consists of an array of 8/spl times/8 or 4/spl times/4 small multipliers plus two or three arrays of adders. The total amount of hardware is comparable to a single 64/spl times/64 array multiplier; (4) The whole network is reconfigured through using a few control bits for the desired computations, and the reconfiguration can be done dynamically; (5) The design is highly regular and modular, and most parts of the network are symmetric and repeatable. (6) A set of high performance parallel counter circuits are utilized in the design.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124558075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824104
T. Asakawa, K. Iwasaki
We propose a method for designing a test pattern generator (TPG) to achieve high-fault coverage for stuck-at faults with short application time during BIST. The TPG consists of shift registers and a small amount of ROM containing test vectors generated by an ATPG tool. Experimental results show that our method can drastically reduce the test length required to achieve high-fault coverage with a small amount of hardware overhead in comparison with an LFSR-based method.
{"title":"On using ATPG vectors for BIST TPG","authors":"T. Asakawa, K. Iwasaki","doi":"10.1109/APASIC.1999.824104","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824104","url":null,"abstract":"We propose a method for designing a test pattern generator (TPG) to achieve high-fault coverage for stuck-at faults with short application time during BIST. The TPG consists of shift registers and a small amount of ROM containing test vectors generated by an ATPG tool. Experimental results show that our method can drastically reduce the test length required to achieve high-fault coverage with a small amount of hardware overhead in comparison with an LFSR-based method.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125702290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824093
Do-Wan Kim, D. Jeong
We designed a 32/spl times/32 self-timed multiplier with DCVSL. The multiplier supports both signed and unsigned integer multiplication, and adopts an early completion scheme for fast operation. We proposed a new 4-phase handshake circuit that fits well with DCVSL. We implement the proposed multiplier with 0.6 /spl mu/m CMOS technology, and simulate the circuit with HSPICE. The latency of the multiplier is between 11.7 ns and 98.7 ns. The size of the core multiplier is about 1.8 mm/spl times/1.4 mm.
{"title":"A 32/spl times/32 self-timed multiplier with early completion","authors":"Do-Wan Kim, D. Jeong","doi":"10.1109/APASIC.1999.824093","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824093","url":null,"abstract":"We designed a 32/spl times/32 self-timed multiplier with DCVSL. The multiplier supports both signed and unsigned integer multiplication, and adopts an early completion scheme for fast operation. We proposed a new 4-phase handshake circuit that fits well with DCVSL. We implement the proposed multiplier with 0.6 /spl mu/m CMOS technology, and simulate the circuit with HSPICE. The latency of the multiplier is between 11.7 ns and 98.7 ns. The size of the core multiplier is about 1.8 mm/spl times/1.4 mm.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125753596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824101
P. Lala, A. Singh
This paper proposes a self-checking logic cell that can be used as the building block for on-line testable FPGAs. The proposed cell consists of three 4-to-1 multiplexers, a 2-to-1 multiplexers and a D flip-flop. These multiplexers and the D flip-flop are designed using differential cascode voltage switch logic. Any single transistor fault (stuck-on/off) as well as single stuck-at faults at the inputs of the multiplexers or the D flip-flop can be detected on-line.
{"title":"Logic cell design for on-line testable FPGAs","authors":"P. Lala, A. Singh","doi":"10.1109/APASIC.1999.824101","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824101","url":null,"abstract":"This paper proposes a self-checking logic cell that can be used as the building block for on-line testable FPGAs. The proposed cell consists of three 4-to-1 multiplexers, a 2-to-1 multiplexers and a D flip-flop. These multiplexers and the D flip-flop are designed using differential cascode voltage switch logic. Any single transistor fault (stuck-on/off) as well as single stuck-at faults at the inputs of the multiplexers or the D flip-flop can be detected on-line.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131761488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824102
Y. Kang, Kyung-Hoi Huh, Sungho Kang
In this paper a new scan design for detection of stuck-at faults and delay faults in asynchronous sequential circuits based on the micropipeline approach is proposed. This new scan methodology can gain the high fault coverage of path delay fault as well as stuck-at fault with the small area overhead in the asynchronous micropipeline environments and easily expand the application such as built-in self testing.
{"title":"New scan design of asynchronous sequential circuits","authors":"Y. Kang, Kyung-Hoi Huh, Sungho Kang","doi":"10.1109/APASIC.1999.824102","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824102","url":null,"abstract":"In this paper a new scan design for detection of stuck-at faults and delay faults in asynchronous sequential circuits based on the micropipeline approach is proposed. This new scan methodology can gain the high fault coverage of path delay fault as well as stuck-at fault with the small area overhead in the asynchronous micropipeline environments and easily expand the application such as built-in self testing.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133763762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824031
I. Oh
This paper presents a new driving circuit and method to improve the base driving performance, and to show the validity of the proposed base current driving method by seeing the whole basic operations of the horizontal deflection circuit. Finally, the improved performance results by employing the proposed circuit and base current waveform are given by the experiment results.
{"title":"A new base driving technique of a high voltage BJT for the horizontal deflection output using a CRT","authors":"I. Oh","doi":"10.1109/APASIC.1999.824031","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824031","url":null,"abstract":"This paper presents a new driving circuit and method to improve the base driving performance, and to show the validity of the proposed base current driving method by seeing the whole basic operations of the horizontal deflection circuit. Finally, the improved performance results by employing the proposed circuit and base current waveform are given by the experiment results.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131676483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824010
U. Seng-Pan, R. Neves, R. Martins, J. Franca
This paper proposes an optimum design of a high frequency Switched-Capacitor IIR interpolation filter for Direct Digital Frequency Synthesizer systems. The circuit is formed by the combination of novel double sampling recursive direct-form II and non-recursive polyphase structures embedding mismatch-free analog delay lines with accurate, wideband gain- and offset-compensation achieved by Predictive Correlated-Double Sampling techniques. This filter is designed with optimized speed of the analog components in AMS 0.35 /spl mu/m CMOS technology, occupies about 0.4 mm/sup 2/ active area and consumes about 22 mW at 3.0 V supply.
{"title":"A 120 MHz SC 4th-order elliptic interpolation filter with accurate gain and offset compensation for direct digital frequency synthesizer","authors":"U. Seng-Pan, R. Neves, R. Martins, J. Franca","doi":"10.1109/APASIC.1999.824010","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824010","url":null,"abstract":"This paper proposes an optimum design of a high frequency Switched-Capacitor IIR interpolation filter for Direct Digital Frequency Synthesizer systems. The circuit is formed by the combination of novel double sampling recursive direct-form II and non-recursive polyphase structures embedding mismatch-free analog delay lines with accurate, wideband gain- and offset-compensation achieved by Predictive Correlated-Double Sampling techniques. This filter is designed with optimized speed of the analog components in AMS 0.35 /spl mu/m CMOS technology, occupies about 0.4 mm/sup 2/ active area and consumes about 22 mW at 3.0 V supply.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"8 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115465609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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