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AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)最新文献

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A novel architecture design for multicode CDMA rake receiver 一种新的多码码分多址接收机结构设计
Pub Date : 1999-08-23 DOI: 10.1109/APASIC.1999.824126
Sangyun Hwang, Seongjoo Lee, Jae-Seok Kim, Chae K. Lee, Sunghwan Jun
We propose a new architecture design for the Multicode CDMA (MC-CDMA) rake receiver. It contains one searcher module, three independent fat finger modules, and one combiner for the demodulation of high-rate data. We compare the hardware complexity of the proposed architecture with a conventional CDMA rake receiver in terms of the number of Walsh code channels. The result shows that our proposed architecture has a 12% and 18.6% reduction in gate count when the number of Walsh code channels is 4 and 7, respectively.
提出了一种多码CDMA (MC-CDMA) rake接收机的新架构设计。它包含一个搜索模块,三个独立的胖手指模块和一个用于高速数据解调的合并器。根据沃尔什码信道的数量,我们比较了所提出架构与传统CDMA rake接收机的硬件复杂性。结果表明,当沃尔什码通道数为4和7时,我们提出的架构分别减少了12%和18.6%的门数。
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引用次数: 1
Pattern generation for verification of VHDL behavioral-level design 验证VHDL行为级设计的模式生成
Pub Date : 1999-08-23 DOI: 10.1109/APASIC.1999.824096
Jong-Hyeon Kim, Seung-Kyu Park, Young-ho Seo, Dong-Wook Kim
Design methodology has been changing from schematic-based design to HDL based-design. In HDL based-design, coding errors may exist and it takes much time to be found and corrected in design process. Thus an efficient method to verify the correctness of the coding itself is required. In this paper, we proposed a verification method for VHDL behavioral level design. VHDL coding is converted into CDFG and verification patterns are generated. Generated patterns are applied to VHDL design and the gold-unit. If there is difference in responses from VHDL design and gold-unit, coding error exists in VHDL design, and the proposed method detects and locates the coding error. Simulation result showed that the proposed method could verify the correctness of the design efficiently.
设计方法已经从基于原理图的设计转变为基于HDL的设计。在基于HDL的设计中,可能存在编码错误,并且在设计过程中需要花费大量的时间来发现和纠正。因此,需要一种有效的方法来验证编码本身的正确性。本文提出了一种针对VHDL行为关卡设计的验证方法。将VHDL编码转换为CDFG并生成验证模式。生成的模式应用于VHDL设计和金单元。如果VHDL设计与gold-unit的响应存在差异,则说明VHDL设计存在编码错误,该方法可以检测和定位编码错误。仿真结果表明,该方法能够有效地验证设计的正确性。
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引用次数: 1
The low-area of new arc-tangent look-up table and a low overhead for CATV modem systems 新型切线查表面积小,有线电视调制解调器系统开销低
Pub Date : 1999-08-23 DOI: 10.1109/APASIC.1999.824022
Young-Hoon Ban, Byung-Lok Choj, Jai-Chul Song
Makes possible a removal of the preamble for carrier recovery and symbol-timing recovery by storing a burst in memory with low overhead quaternary phase shift keying (QPSK) demodulation method which also effects frame efficiency improved by processed synchronization performance. In this paper, we propose the new algorithm for arc-tangent look-up table which transforms the input I, Q data by phase. This I, Q data plays an important role in demodulation and realises a demodulator with low-overhead by storing a burst in memory.
通过使用低开销的四元相移键控(QPSK)解调方法在存储器中存储突发,使得除去用于载波恢复和符号定时恢复的序言成为可能,该解调方法还影响通过处理同步性能提高的帧效率。本文提出了对输入I、Q数据进行相位变换的切弧查找表新算法。这种I, Q数据在解调中起着重要的作用,并通过在内存中存储突发来实现低开销的解调器。
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引用次数: 2
IEEE 1284 softcore-implementation issues IEEE 1284软核实现问题
Pub Date : 1999-08-23 DOI: 10.1109/APASIC.1999.824080
Myoung-Han Lee, Sun-Kyu Kim, Myoung-Sun Park, Yl-Seong Bae, P. Chung
In this paper, we present a re-usable softcore for the IEEE 1284 protocol for parallel data transmission. It consists of two parts. One is the firmware to cope with the IEEE-1284 protocol being executed in the processor and the other is the hardware engine to accelerate the basic communication mechanism. Using our evaluation system, it is verified that the designed core is fully compliant with the specification. Additionally, we show the results on the performance comparison between the compatibility and ECP modes of the IEEE-1284 standard.
在本文中,我们提出了一个可重用的软件核,用于并行数据传输的ieee1284协议。它由两部分组成。一个是固件,用于处理处理器中正在执行的IEEE-1284协议;另一个是硬件引擎,用于加速基本通信机制。使用我们的评估系统,验证了设计的核心完全符合规范。此外,我们还展示了IEEE-1284标准的兼容模式和ECP模式的性能比较结果。
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引用次数: 1
A novel FPGA design of a high throughput rate adaptive prediction error filter 一种新型高吞吐率自适应预测误差滤波器的FPGA设计
Pub Date : 1999-08-23 DOI: 10.1109/APASIC.1999.824063
Y. Hwang, Jih-Cheng Han
In this paper we propose a novel adaptive prediction error filter design and implement it as a DSP core on FPGAs. The filter consists of a predictor and a Toeplitz solver. Previous ASIC design approaches often encountered problems such as unbalanced computing loads and extra data redirection circuit overheads. Therefore, we first reformulate the Schur algorithm and then derive an efficient systolic array designs capable of solving a size N Toeplitz matrix in every 2N cycles with each cycle equal to one MAC delay. The predictor design is implemented using the distributed arithmetic (DA) approach. The entire design is described in synthesizable VHDL code and fully parameterized with respect to the matrix size and word length. For the case of solving a tap 50 adaptive prediction error filter, we can achieve a clock rate of 40 MHz and a processing (symbol) rate as high as 60,976 matrix updates per second using four Xilinx 4044XL-3 FPGAs.
本文提出了一种新的自适应预测误差滤波器设计方案,并将其作为DSP核心实现在fpga上。该过滤器由一个预测器和一个Toeplitz解算器组成。以前的ASIC设计方法经常遇到计算负载不平衡和额外的数据重定向电路开销等问题。因此,我们首先重新制定Schur算法,然后推导出一种有效的收缩阵列设计,能够在每2N个周期内求解大小为N的Toeplitz矩阵,每个周期等于一个MAC延迟。预测器设计采用分布式算法(DA)实现。整个设计用可合成的VHDL代码描述,并根据矩阵大小和字长进行了充分的参数化。对于解决分接50自适应预测误差滤波器的情况,我们可以使用四个Xilinx 4044XL-3 fpga实现40 MHz的时钟速率和高达每秒60,976个矩阵更新的处理(符号)速率。
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引用次数: 4
A 0.7-1 Gb/s CMOS clock recovery circuit 一个0.7- 1gb /s的CMOS时钟恢复电路
Pub Date : 1999-08-23 DOI: 10.1109/APASIC.1999.824086
Hui Wang, R. Nottenburg
A 0.7-1 Gb/s clock recovery circuit is designed by ruing a 0.5 /spl mu/m digital CMOS process. It consists of a bang-bang type frequency detector (FD) to acquire frequency lock and a linear phase detector (PD) to acquire phase lock. The FD is able to reset itself upon frequency lock. Measured RMS jitter of the recovered clock is 7.4 ps at 1 GHz and 7 ps at 0.7 GHz. It is able to maintain a BER better than 10/sup -11/ for up to 140 missing transitions. It consumes 200 mW with a 5 V power supply.
利用0.5 /spl mu/m的数字CMOS工艺,设计了一个0.7 ~ 1gb /s的时钟恢复电路。它由一个用于锁频的砰砰式鉴频器(FD)和一个用于锁相的线性鉴相器(PD)组成。FD能够在频率锁定时自行复位。恢复时钟的测量有效值抖动在1ghz时为7.4 ps,在0.7 GHz时为7 ps。它能够维持一个比10/sup -11/更好的误码率高达140个缺失转换。它的功耗为200mw,电源为5v。
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引用次数: 1
Design and analysis of symmetric dual-layer spiral inductors for RF integrated circuits 射频集成电路对称双层螺旋电感的设计与分析
Pub Date : 1999-08-23 DOI: 10.1109/APASIC.1999.824011
Sang-Gug Lee, G. Ihm, W. Song
An area efficient and symmetric dual-layer spiral inductor structure is proposed and evaluated in comparison with the conventional single-layer spiral inductors. Measurements show that, for a given silicon area, the dual-layer inductor provides nearly 4 time the inductance of the single-layer inductor, while the quality factor is up to 2 times higher. For the same amount of inductance the dual-layer inductors show comparable to higher quality factor depends on frequency of operation. This paper demonstrates that, contrary to the common understanding the dual-layer can be more useful for the RF integrated circuits than the conventional single-layered spiral inductors from the aspects of area efficiency and quality factor The proposed dual-layer inductor can also be used as a high-frequency choke.
提出了一种面积高效对称的双层螺旋电感结构,并与传统单层螺旋电感进行了比较。测量表明,对于给定的硅面积,双层电感提供的电感几乎是单层电感的4倍,而质量因子高达2倍。对于相同的电感量,双层电感具有相当高的质量因数,这取决于工作频率。从面积效率和质量因子两个方面论证了双层螺旋电感在射频集成电路中比传统的单层螺旋电感更有用,而且双层电感还可以用作高频扼流圈。
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引用次数: 14
A 3 V 10 b 70 MHz digital-to-analog converter for video applications 用于视频应用的3v 10b70mhz数模转换器
Pub Date : 1999-08-23 DOI: 10.1109/APASIC.1999.824059
Jin Park, Seung-Chul Lee, Seunghoon Lee
This paper describes a 10 b 70 MHz CMOS digital-to-analog converter (DAC) for video applications. The proposed 10 b DAC is composed of a unit decoded matrix for 7 MSB's and a binary weighted array for 3 LSBs, considering linearity, power consumption, routing area, and glitch energy. A new switching scheme for the unit decoded matrix is developed to improve linearity further. Cascode current sources and differential switches with the proposed new deglitching circuit improve dynamic performance. The fabricated and measured prototype DAC in a 0.8 um double-poly double-metal n-well CMOS process typically shows a spurious free dynamic range of 55 dB and a total harmonic distortion of -49 dB at a 3 V supply voltage and a 70 MHz update rate with a 120 mW power consumption. The measured differential and integral nonlinearities are /spl plusmn/0.69 LSB and /spl plusmn/0.79 LSB at a 10 b level, respectively.
本文介绍了一种用于视频应用的10b70mhz CMOS数模转换器(DAC)。考虑到线性度、功耗、路由面积和故障能量,提出的10b DAC由7个MSB的单元解码矩阵和3个lsb的二进制加权阵列组成。为了进一步提高线性度,提出了一种新的单元解码矩阵切换方案。层叠电流源和差动开关采用了新型脱毛刺电路,提高了动态性能。在0.8 um双聚双金属n阱CMOS工艺中制作和测量的原型DAC在3 V电源电压、70 MHz更新速率和120 mW功耗下的无杂散动态范围为55 dB,总谐波失真为-49 dB。在10b水平下,测量到的微分和积分非线性分别为/spl plusmn/0.69 LSB和/spl plusmn/0.79 LSB。
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引用次数: 5
A GHz I-Q quadrature signal generator using cellular oscillator network 一种基于蜂窝振荡器网络的GHz I-Q正交信号发生器
Pub Date : 1999-08-23 DOI: 10.1109/APASIC.1999.824036
Sun-Mo Hwang, G. Moon, Seong-Ho Song
The design of a GHz I-Q and Signal CMOS Generator using a Cellular Oscillator Network architecture is presented and analyzed. With its high speed for settling and easy frequency controllability, this I-Q signal generation method can be used in RF communication systems, where GHz range quadrature signals are needed. Also, a technique is presented for a sleeping mode with a small settling time. This model is simulated and proved with typical 3 V, 0.5 /spl mu/ CMOS N-well process parameters.
提出并分析了一种基于蜂窝振荡器网络结构的GHz I-Q和信号CMOS发生器的设计。该I-Q信号生成方法具有快速沉降和易于频率控制的特点,可用于需要GHz范围正交信号的射频通信系统中。同时,提出了一种短时间睡眠模式的实现方法。该模型采用典型的3 V、0.5 /spl mu/ CMOS n阱工艺参数进行了仿真验证。
{"title":"A GHz I-Q quadrature signal generator using cellular oscillator network","authors":"Sun-Mo Hwang, G. Moon, Seong-Ho Song","doi":"10.1109/APASIC.1999.824036","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824036","url":null,"abstract":"The design of a GHz I-Q and Signal CMOS Generator using a Cellular Oscillator Network architecture is presented and analyzed. With its high speed for settling and easy frequency controllability, this I-Q signal generation method can be used in RF communication systems, where GHz range quadrature signals are needed. Also, a technique is presented for a sleeping mode with a small settling time. This model is simulated and proved with typical 3 V, 0.5 /spl mu/ CMOS N-well process parameters.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124981564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Realization of current-mode multifunction filters using multiple-output current conveyors 用多输出电流输送机实现电流型多功能滤波器
Pub Date : 1999-08-23 DOI: 10.1109/APASIC.1999.824028
M. Higashimura, Y. Fukui
This paper presents novel circuit configuration for realizing current-mode one-input and three-output type biquads using multiple-output current conveyors (MOCCIIs) and grounded passive elements. These circuits realize high-pass, band-pass and low-pass transfer functions simultaneously. By connecting output terminals, we can also realize bandstop and allpass transfer functions. The circuits use grounded capacitors, and have high output impedances which are suitable for current outputs. The cutoff frequency of the filter can be tuned independently of Q by the value of current gain K.
本文提出了利用多输出电流传送带(MOCCIIs)和接地无源元件实现电流型单输入三输出双电路的新颖电路结构。这些电路同时实现高通、带通和低通传递功能。通过连接输出端子,还可以实现带阻和全通传递功能。该电路采用接地电容器,具有适合电流输出的高输出阻抗。滤波器的截止频率可以通过电流增益K的值独立于Q进行调谐。
{"title":"Realization of current-mode multifunction filters using multiple-output current conveyors","authors":"M. Higashimura, Y. Fukui","doi":"10.1109/APASIC.1999.824028","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824028","url":null,"abstract":"This paper presents novel circuit configuration for realizing current-mode one-input and three-output type biquads using multiple-output current conveyors (MOCCIIs) and grounded passive elements. These circuits realize high-pass, band-pass and low-pass transfer functions simultaneously. By connecting output terminals, we can also realize bandstop and allpass transfer functions. The circuits use grounded capacitors, and have high output impedances which are suitable for current outputs. The cutoff frequency of the filter can be tuned independently of Q by the value of current gain K.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117241447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
期刊
AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)
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