Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824066
Naohiko Shimizut, Makoto Naitot
In this paper the authors present a dual issue queued pipelined Java processor TRAJA 3.0. It can decode 162 instructions of the Java Virtual Machine (JVM)'s opcodes and it has a set of proprietary instructions. The pipeline has four instruction buffers and four decode queues to overcome the pipeline stalls on decoding the variable length instructions of the JVM. The processor also executes a restricted set of instruction folding and a restricted set of instruction reorder. In addition it has a caching scheme for the fast execution of the array instructions of the JVM.
{"title":"A dual issue queued pipelined Java processor TRAJA-toward an open source processor project","authors":"Naohiko Shimizut, Makoto Naitot","doi":"10.1109/APASIC.1999.824066","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824066","url":null,"abstract":"In this paper the authors present a dual issue queued pipelined Java processor TRAJA 3.0. It can decode 162 instructions of the Java Virtual Machine (JVM)'s opcodes and it has a set of proprietary instructions. The pipeline has four instruction buffers and four decode queues to overcome the pipeline stalls on decoding the variable length instructions of the JVM. The processor also executes a restricted set of instruction folding and a restricted set of instruction reorder. In addition it has a caching scheme for the fast execution of the array instructions of the JVM.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124997841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824125
K. Nah, T. Ahn, Seung-Beom Baik, Jin-Sub Choi, W. Choo, Dong-Jin Keum, I. Sohn, D. Jung
A 48-pin "minichip" version of the baseband to IF band transceiver chip for CDMA mobile phones, commonly known as the BBA chip, is introduced. It achieves about a thirty three percent reduction in the total pin count relative to the well established 80-pin package version. The paper also presents countermeasures taken against the worsened noise environment brought on by the increased sharing of the power and ground pins among the internal blocks. The minichip is fabricated in a 0.8-/spl mu/m 8-GHz BiCMOS technology and consumes 36 mA from a 3.3 V supply. Its size is 4450/spl times/4450 /spl mu/m/sup 2/. The chip has found application in what are known as watch-phones.
{"title":"A 48-pin \"minichip\" implementation of baseband analog processor for the CDMA mobile phones","authors":"K. Nah, T. Ahn, Seung-Beom Baik, Jin-Sub Choi, W. Choo, Dong-Jin Keum, I. Sohn, D. Jung","doi":"10.1109/APASIC.1999.824125","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824125","url":null,"abstract":"A 48-pin \"minichip\" version of the baseband to IF band transceiver chip for CDMA mobile phones, commonly known as the BBA chip, is introduced. It achieves about a thirty three percent reduction in the total pin count relative to the well established 80-pin package version. The paper also presents countermeasures taken against the worsened noise environment brought on by the increased sharing of the power and ground pins among the internal blocks. The minichip is fabricated in a 0.8-/spl mu/m 8-GHz BiCMOS technology and consumes 36 mA from a 3.3 V supply. Its size is 4450/spl times/4450 /spl mu/m/sup 2/. The chip has found application in what are known as watch-phones.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134102621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824078
K. Byun, Minsoo Hahn, Kyung-Su Kim
In this paper an efficient implementation of a 13 kbps QCELP vocoder ASIC having a speech compression function used in the digital mobile communication is presented The 13 kbps QCELP algorithm has better quality than 8 kbps one, but it requires much more computation. Especially, the complexity load of the pitch and codebook search process for speech synthesis is predominant. We propose an optimized routine for convolution computation by utilizing pipeline structure characteristics of the DSP. Our DSP, specifically designed for vocoder applications, is a 16-bit fixed-point one. We adopt RISC type instruction set, distributed decoding, alternative program fetch, dual bank memory structure, and repeat loop without loss in order to reduce the power consumption and to obtain fast operating capability while keeping the chip size small. The concurrent development of the DSP and the QCELP assembly code enables us to optimize the assembly code more successfully than adopting other general-purpose DSP chips.
{"title":"Implementation of 13 kbps QCELP vocoder ASIC","authors":"K. Byun, Minsoo Hahn, Kyung-Su Kim","doi":"10.1109/APASIC.1999.824078","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824078","url":null,"abstract":"In this paper an efficient implementation of a 13 kbps QCELP vocoder ASIC having a speech compression function used in the digital mobile communication is presented The 13 kbps QCELP algorithm has better quality than 8 kbps one, but it requires much more computation. Especially, the complexity load of the pitch and codebook search process for speech synthesis is predominant. We propose an optimized routine for convolution computation by utilizing pipeline structure characteristics of the DSP. Our DSP, specifically designed for vocoder applications, is a 16-bit fixed-point one. We adopt RISC type instruction set, distributed decoding, alternative program fetch, dual bank memory structure, and repeat loop without loss in order to reduce the power consumption and to obtain fast operating capability while keeping the chip size small. The concurrent development of the DSP and the QCELP assembly code enables us to optimize the assembly code more successfully than adopting other general-purpose DSP chips.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"79 3-4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134289412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824079
Se Ho Park, Dong Hwan Kim, D. Han, Kyu Lee, S. Park, J. Choi
In this paper we propose an implementation method for a single-chip 8192 complex point FFT in terms of sequential data processing. In order to reduce the required chip area for the sequential processing of 8 K complex data, a DRAM-like pipelined commutator architecture is used. The 16-point FFT is a basic building block of the entire FFT chip, and the 8192-point FFT consists of the cascaded blocks with six stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding. As a result the proposed structure brings about the 55% chip size reduction compared with conventional approach.
{"title":"Sequential design of a 8192 complex point FFT in OFDM receiver","authors":"Se Ho Park, Dong Hwan Kim, D. Han, Kyu Lee, S. Park, J. Choi","doi":"10.1109/APASIC.1999.824079","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824079","url":null,"abstract":"In this paper we propose an implementation method for a single-chip 8192 complex point FFT in terms of sequential data processing. In order to reduce the required chip area for the sequential processing of 8 K complex data, a DRAM-like pipelined commutator architecture is used. The 16-point FFT is a basic building block of the entire FFT chip, and the 8192-point FFT consists of the cascaded blocks with six stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding. As a result the proposed structure brings about the 55% chip size reduction compared with conventional approach.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133190926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824123
Seong-Ho Park, G. Lim, Yong-Hee Lee
In this paper rf characteristics of a 0.25 /spl mu/m DRAM embedded CMOS process, focused on the n-MOSFET and the spiral inductor of the critical devices in rf CMOS circuit design, have been investigated. An extremely high cutoff frequency of 44 GHz, high maximum operating frequency of 29 GHz, and a de-embedded minimum noise figure of 1.0 dB have been obtained for a 0.24 /spl mu/m n-MOSFET. As for the spiral inductors, we obtained a peak quality factor of 5.2 at 3.6 nH for a 5-turn inductor and also an inductance of 1.2 to 22.6 nH for inductors with various numbers of turns. These figures of merit seem to be suitable for rf circuits with operating frequency up to 2.5 GHz although the low quality factor of the spiral inductor should be improved.
{"title":"RF characterization of deep-submicron DRAM-embedded CMOS process","authors":"Seong-Ho Park, G. Lim, Yong-Hee Lee","doi":"10.1109/APASIC.1999.824123","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824123","url":null,"abstract":"In this paper rf characteristics of a 0.25 /spl mu/m DRAM embedded CMOS process, focused on the n-MOSFET and the spiral inductor of the critical devices in rf CMOS circuit design, have been investigated. An extremely high cutoff frequency of 44 GHz, high maximum operating frequency of 29 GHz, and a de-embedded minimum noise figure of 1.0 dB have been obtained for a 0.24 /spl mu/m n-MOSFET. As for the spiral inductors, we obtained a peak quality factor of 5.2 at 3.6 nH for a 5-turn inductor and also an inductance of 1.2 to 22.6 nH for inductors with various numbers of turns. These figures of merit seem to be suitable for rf circuits with operating frequency up to 2.5 GHz although the low quality factor of the spiral inductor should be improved.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132882165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824107
Heemin Park, Gyoochan Sim, Jaehoon Jung, H. Jun
This paper describes test ready core design methodology for TeakLite core. Implementation issues and techniques about test access with minimal test pins, scan chain reconfiguration, and UDL test capability are presented. Testability enhancement for development of high quality test vector is also described. As the result, a very high fault coverage of 99.68% has been achieved. We also present the features of test ready TeakLite core.
{"title":"Test ready core design for TeakLite core","authors":"Heemin Park, Gyoochan Sim, Jaehoon Jung, H. Jun","doi":"10.1109/APASIC.1999.824107","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824107","url":null,"abstract":"This paper describes test ready core design methodology for TeakLite core. Implementation issues and techniques about test access with minimal test pins, scan chain reconfiguration, and UDL test capability are presented. Testability enhancement for development of high quality test vector is also described. As the result, a very high fault coverage of 99.68% has been achieved. We also present the features of test ready TeakLite core.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116389957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824113
M.Y. Park, J. Kim, D. Lee, J. Park, K. Cho, H. Cho
We have developed the gate driver IC with 64-channel outputs and the PWM cathode driver IC with 32-channel outputs for driving row/column line of FED panel. The developed gate and the cathode driver ICs having full-complementary high voltage output circuit and CVSL type level shifter are suited for low power consumption, high speed switching as 20 MHz, high output drive voltages ranging from 20 V to 100 V and 20 mA current driving. The high-voltage output stages perform 100 V switching of 50 pF capacitive load with 100 ns of rising/falling time obtained. The LDMOS technology that is completely compatible with 1.2 /spl mu/m analog CMOS process is used to decrease the production cost and increase the packing density of panel driving system. The gate and cathode driver ICs applied 25/spl times/25 FED panels driving board show excellent driving characteristics.
{"title":"A 100 V, 10 mA high-voltage driver ICs for field emission display applications","authors":"M.Y. Park, J. Kim, D. Lee, J. Park, K. Cho, H. Cho","doi":"10.1109/APASIC.1999.824113","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824113","url":null,"abstract":"We have developed the gate driver IC with 64-channel outputs and the PWM cathode driver IC with 32-channel outputs for driving row/column line of FED panel. The developed gate and the cathode driver ICs having full-complementary high voltage output circuit and CVSL type level shifter are suited for low power consumption, high speed switching as 20 MHz, high output drive voltages ranging from 20 V to 100 V and 20 mA current driving. The high-voltage output stages perform 100 V switching of 50 pF capacitive load with 100 ns of rising/falling time obtained. The LDMOS technology that is completely compatible with 1.2 /spl mu/m analog CMOS process is used to decrease the production cost and increase the packing density of panel driving system. The gate and cathode driver ICs applied 25/spl times/25 FED panels driving board show excellent driving characteristics.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115626026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824085
Yeon-kug Moon, K. Yoon
A 3.3 V PLL (Phase Locked loop) is designed for high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage-to-frequency linearity of the VCO (Voltage Controlled Oscillator) with new delay cell. The proposed VCO operates at a wide frequency range of 30 MHz/spl sim/1 GHz with a good linearity. The DC-DC voltage up/down converter is newly designed to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6 /spl mu/m n-well CMOS process. The simulation results show a locking time of 2.6 /spl mu/s at 1 GHz, lock in range of 100 MHz/spl sim/1 GHz, and a power dissipation of 112 mW.
{"title":"A 3.3 V high speed CMOS PLL with a two-stage self-feedback ring oscillator","authors":"Yeon-kug Moon, K. Yoon","doi":"10.1109/APASIC.1999.824085","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824085","url":null,"abstract":"A 3.3 V PLL (Phase Locked loop) is designed for high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage-to-frequency linearity of the VCO (Voltage Controlled Oscillator) with new delay cell. The proposed VCO operates at a wide frequency range of 30 MHz/spl sim/1 GHz with a good linearity. The DC-DC voltage up/down converter is newly designed to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6 /spl mu/m n-well CMOS process. The simulation results show a locking time of 2.6 /spl mu/s at 1 GHz, lock in range of 100 MHz/spl sim/1 GHz, and a power dissipation of 112 mW.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121216111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824149
Sung-Jin Kim, Yong-Goo Lee, Sang-Ki Yun, Hai-Young Lee
Two types of novel high-Q vertical on-chip inductors using wirebonding technology are proposed for low cost and high performance Si-RFIC's. The new inductors show significant improvements of the quality factor and the self-resonant frequency. Their measured maximum quality factors are about 3-times higher than those of the planar spiral inductors (7 for 3.4 nH, 6 for 5 nH) at most. From these experimental results, the bondwire inductors are expected to greatly improve the performance and the production cost of Si-RFIC's.
{"title":"Realization of high-Q inductors using wirebonding technology","authors":"Sung-Jin Kim, Yong-Goo Lee, Sang-Ki Yun, Hai-Young Lee","doi":"10.1109/APASIC.1999.824149","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824149","url":null,"abstract":"Two types of novel high-Q vertical on-chip inductors using wirebonding technology are proposed for low cost and high performance Si-RFIC's. The new inductors show significant improvements of the quality factor and the self-resonant frequency. Their measured maximum quality factors are about 3-times higher than those of the planar spiral inductors (7 for 3.4 nH, 6 for 5 nH) at most. From these experimental results, the bondwire inductors are expected to greatly improve the performance and the production cost of Si-RFIC's.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122208349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824111
J. W. Wee, T. Park, Chong-Ho Lee
This paper suggests new methods for hardware evolution (evolvable hardware, EHW) where the hardware structure is adaptable to the environment. The hardware structure is evolved in real-time by genetic algorithm to obtain a desired function of the digital circuit. In order to operate the EHW efficiently by using genetic algorithm processor (GAP), an encoding technique is employed. Proposed encoding technique shortens the chromosome length and increases the processing speed, as well. Some combinational circuits have been evolved successfully on XC6216 FPGA intrinsically.
{"title":"Adaptive hardware evolution under unpredictable environmental changes","authors":"J. W. Wee, T. Park, Chong-Ho Lee","doi":"10.1109/APASIC.1999.824111","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824111","url":null,"abstract":"This paper suggests new methods for hardware evolution (evolvable hardware, EHW) where the hardware structure is adaptable to the environment. The hardware structure is evolved in real-time by genetic algorithm to obtain a desired function of the digital circuit. In order to operate the EHW efficiently by using genetic algorithm processor (GAP), an encoding technique is employed. Proposed encoding technique shortens the chromosome length and increases the processing speed, as well. Some combinational circuits have been evolved successfully on XC6216 FPGA intrinsically.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121034310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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