Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824117
M. Miyazaki, K. Ishibashi
We have developed a delay-locked loop (DLL) which has a parallel phase-detector for generating a system clock in LSIs. The generated clock is synchronized to an internal clock for various loads in a system. The DLL achieves a settling time of 3 clock-cycles and a maximum skew of 150 ps. The operating frequency is from 66 MHz to 230 MHz with a typical power consumption of 13.5 mW at 100 MHz. In addition, due to the short settling time, the DLL can be powered down to reduce the standby current.
{"title":"A 3-cycle lock time delay-locked loop with a parallel phase detector for low power mobile systems","authors":"M. Miyazaki, K. Ishibashi","doi":"10.1109/APASIC.1999.824117","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824117","url":null,"abstract":"We have developed a delay-locked loop (DLL) which has a parallel phase-detector for generating a system clock in LSIs. The generated clock is synchronized to an internal clock for various loads in a system. The DLL achieves a settling time of 3 clock-cycles and a maximum skew of 150 ps. The operating frequency is from 66 MHz to 230 MHz with a typical power consumption of 13.5 mW at 100 MHz. In addition, due to the short settling time, the DLL can be powered down to reduce the standby current.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128052931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824064
Y. Hung, Bin-Da Liu
A scalable high-precision maximum/minimum circuit is designed. This circuit can be easily configured as maximum or minimum function by an enable signal without modifying the circuit structure and pre-processing input variables. The response time of the circuit is increased linearly with respect to the number of input variables. This circuit has been simulated using 0.5 /spl mu/m CMOS technology by HSPICE. The results show that a cell can be a winner/loser if its input voltage is larger or smaller than those of other cells by 3 mV.
设计了一种可扩展的高精度最大/最小电路。该电路可以通过使能信号轻松配置为最大或最小功能，而无需修改电路结构和预处理输入变量。电路的响应时间随输入变量的数量线性增加。利用HSPICE软件采用0.5 /spl μ m CMOS技术对该电路进行了仿真。结果表明，如果一个电池的输入电压比其他电池的输入电压大或小3 mV，就可以成为赢家或输家。
{"title":"A scalable high-precision CMOS max/min circuit using single comparator","authors":"Y. Hung, Bin-Da Liu","doi":"10.1109/APASIC.1999.824064","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824064","url":null,"abstract":"A scalable high-precision maximum/minimum circuit is designed. This circuit can be easily configured as maximum or minimum function by an enable signal without modifying the circuit structure and pre-processing input variables. The response time of the circuit is increased linearly with respect to the number of input variables. This circuit has been simulated using 0.5 /spl mu/m CMOS technology by HSPICE. The results show that a cell can be a winner/loser if its input voltage is larger or smaller than those of other cells by 3 mV.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131938509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824074
M. H. Chow, P. K. Chan, L. Siek
This paper presents a straightforward way to optimize scaling coefficients used in multistage (MASH) sigma-delta modulators. The scaling coefficients used to counter the effects of overloading are shown to be related to the reference voltage of the 1-bit D/A converter. Finally, an optimized 2-1-1 modulator with an extended dynamic range is proposed. This modulator uses a local feedback loop to extend the dynamic range (DR) to full-scale input level without overloading.
{"title":"Overloading in multistage sigma-delta modulators","authors":"M. H. Chow, P. K. Chan, L. Siek","doi":"10.1109/APASIC.1999.824074","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824074","url":null,"abstract":"This paper presents a straightforward way to optimize scaling coefficients used in multistage (MASH) sigma-delta modulators. The scaling coefficients used to counter the effects of overloading are shown to be related to the reference voltage of the 1-bit D/A converter. Finally, an optimized 2-1-1 modulator with an extended dynamic range is proposed. This modulator uses a local feedback loop to extend the dynamic range (DR) to full-scale input level without overloading.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"33 7-8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131980122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824058
Jungeun Lee, Minkyu Song
In this paper, an 8-bit 100 KSPS 1 mW CMOS A/D converter for digital mobile communication is proposed. The main architecture of the A/D converter is based on a cyclic type, in order to reduce power consumption. This is composed of a proposed Sample and Hold Amplifier (SHA), fully differential gain amplifier and comparator. As the proposed SHA is driven by an offset cancellation clock to reduce offset voltage, the input voltage is held accurately. The proposed fully differential gain amplifier employs a half magnitude of the input capacitance compared to that of the conventional one. Thus both the input capacitance and feedback capacitance have the same value. The A/D converter is fabricated with a 0.6 /spl mu/m single-poly triple-metal n-well CMOS technology and has a power consumption of 980 /spl mu/W at 3 V power supply. Further, the INL and DNL are within /spl plusmn/1 LSB and SNR is about 45 dB.
{"title":"Design of an 8-bit 100 KSPS 1 mW CMOS A/D converter for digital mobile communication","authors":"Jungeun Lee, Minkyu Song","doi":"10.1109/APASIC.1999.824058","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824058","url":null,"abstract":"In this paper, an 8-bit 100 KSPS 1 mW CMOS A/D converter for digital mobile communication is proposed. The main architecture of the A/D converter is based on a cyclic type, in order to reduce power consumption. This is composed of a proposed Sample and Hold Amplifier (SHA), fully differential gain amplifier and comparator. As the proposed SHA is driven by an offset cancellation clock to reduce offset voltage, the input voltage is held accurately. The proposed fully differential gain amplifier employs a half magnitude of the input capacitance compared to that of the conventional one. Thus both the input capacitance and feedback capacitance have the same value. The A/D converter is fabricated with a 0.6 /spl mu/m single-poly triple-metal n-well CMOS technology and has a power consumption of 980 /spl mu/W at 3 V power supply. Further, the INL and DNL are within /spl plusmn/1 LSB and SNR is about 45 dB.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132316559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824081
Jung-Han Lee, Dong-Wook Kim, W. Cho
The authors propose an IEEE 1284 soft IP for system IC implementation. They designed a reduced mode for high-speed and small gate count. The designed IP can be used as a system IC. After simulation the authors verified the designed IP for specific process technology for an actual system IC design process. Finally, they considered which form of IP can be used efficiently for the algorithm level of system IC design.
{"title":"Reduced IEEE 1284 soft IP design for system IC implementation","authors":"Jung-Han Lee, Dong-Wook Kim, W. Cho","doi":"10.1109/APASIC.1999.824081","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824081","url":null,"abstract":"The authors propose an IEEE 1284 soft IP for system IC implementation. They designed a reduced mode for high-speed and small gate count. The designed IP can be used as a system IC. After simulation the authors verified the designed IP for specific process technology for an actual system IC design process. Finally, they considered which form of IP can be used efficiently for the algorithm level of system IC design.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133078381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824091
Jang Jin Hwan, Kim Kyung Ho, Kye Bum Suk
There are some limitations in the ASIC test. The maximum test pattern depth is one of them. A method to reduce the test pattern depth would be very useful. Hence the authors introduce a method to do this and the target ATE is ADVAN.
{"title":"Exceeding test pattern limitation by multi-clock test methodology","authors":"Jang Jin Hwan, Kim Kyung Ho, Kye Bum Suk","doi":"10.1109/APASIC.1999.824091","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824091","url":null,"abstract":"There are some limitations in the ASIC test. The maximum test pattern depth is one of them. A method to reduce the test pattern depth would be very useful. Hence the authors introduce a method to do this and the target ATE is ADVAN.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133818924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824012
Ngai Cheong, R.P. Martins
This paper proposes an interactive architecture compiler for SC multirate circuits, here applied to the design of multistage IIR SC decimators with large decimating factors M. This methodology is implemented based on multi-decimation building blocks such as externally cascaded, internally cascaded or ladder building blocks. A computer-based design is carried out to synthesize and evaluate the performances of the corresponding resulting circuits, in order to achieve the required anti-aliasing amplitude responses, to relax the speed requirements of the operational amplifiers, and also to reduce the capacitance spread and total capacitor area. A design example of a 6th order SC elliptic decimator with M=10 is given to illustrate the above methodology.
{"title":"Synthesis and design of a 6th order SC lowpass decimator combining externally and internally cascaded structures","authors":"Ngai Cheong, R.P. Martins","doi":"10.1109/APASIC.1999.824012","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824012","url":null,"abstract":"This paper proposes an interactive architecture compiler for SC multirate circuits, here applied to the design of multistage IIR SC decimators with large decimating factors M. This methodology is implemented based on multi-decimation building blocks such as externally cascaded, internally cascaded or ladder building blocks. A computer-based design is carried out to synthesize and evaluate the performances of the corresponding resulting circuits, in order to achieve the required anti-aliasing amplitude responses, to relax the speed requirements of the operational amplifiers, and also to reduce the capacitance spread and total capacitor area. A design example of a 6th order SC elliptic decimator with M=10 is given to illustrate the above methodology.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124006554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824069
B.G. Song, S.J. Kim, S. Kwack, M. S. Choi, K. Kwack
This paper presents a new simulation-based analog cell synthesis approach with improved simulation efficiency. For the hierarchical synthesis of analog cell we developed sub-circuit optimizers such as the current mirror and differential input stage. Each sub-circuit optimizer can be used for synthesis of analog cells such as OTA (operational transconductance amplifier), 2-stage op-amp and comparator. To reduce the time spent on the simulation-based synthesis, we propose a two-stage searching scheme and simulation data reuse scheme. With these schemes the synthesis time spent on the OTA was reduced from 301.05 s to 56.52 s, i.e. by 81.1%. Since our synthesis system does not need other additional physical parameters except SPICE parameters, and is independent of the process and its model level, the time spent to port to other process is minimized. We synthesized an OTA and 2-stage op-amp respectively with our approach to show its usefulness.
{"title":"A simulation efficiency improvement method for simulation-based analog cell synthesis","authors":"B.G. Song, S.J. Kim, S. Kwack, M. S. Choi, K. Kwack","doi":"10.1109/APASIC.1999.824069","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824069","url":null,"abstract":"This paper presents a new simulation-based analog cell synthesis approach with improved simulation efficiency. For the hierarchical synthesis of analog cell we developed sub-circuit optimizers such as the current mirror and differential input stage. Each sub-circuit optimizer can be used for synthesis of analog cells such as OTA (operational transconductance amplifier), 2-stage op-amp and comparator. To reduce the time spent on the simulation-based synthesis, we propose a two-stage searching scheme and simulation data reuse scheme. With these schemes the synthesis time spent on the OTA was reduced from 301.05 s to 56.52 s, i.e. by 81.1%. Since our synthesis system does not need other additional physical parameters except SPICE parameters, and is independent of the process and its model level, the time spent to port to other process is minimized. We synthesized an OTA and 2-stage op-amp respectively with our approach to show its usefulness.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127460152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824097
C. Chitu, W. Hofmann
A switched capacitor analog memory circuit for capturing fast signals from Cherenkov telescopes is described. A four channel version of the memory with 128 cells in each channel has been integrated in a 0.8 /spl mu/m complementary metal oxide semiconductor (CMOS) process with poly-to-poly capacitors. The sampling frequency generated on chip is 500 MHz and the readout frequency is 100 kHz. The measured rms cell pedestal variation in a channel after baseline subtraction is less than 10 mV across the full input signal range. The cell-to-cell gain matching is better than 1% rms, and the nonlinearity is less than 1.3% for a 1.5 V input range. The dynamic range of the memory exceeds 8 bits for a 1.5 V input voltage range.
{"title":"High speed analog memory integrated circuit for Cherenkov telescopes","authors":"C. Chitu, W. Hofmann","doi":"10.1109/APASIC.1999.824097","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824097","url":null,"abstract":"A switched capacitor analog memory circuit for capturing fast signals from Cherenkov telescopes is described. A four channel version of the memory with 128 cells in each channel has been integrated in a 0.8 /spl mu/m complementary metal oxide semiconductor (CMOS) process with poly-to-poly capacitors. The sampling frequency generated on chip is 500 MHz and the readout frequency is 100 kHz. The measured rms cell pedestal variation in a channel after baseline subtraction is less than 10 mV across the full input signal range. The cell-to-cell gain matching is better than 1% rms, and the nonlinearity is less than 1.3% for a 1.5 V input range. The dynamic range of the memory exceeds 8 bits for a 1.5 V input voltage range.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130784778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824116
J. Wee, Phil-Jung Kim, H. Cho, J. Oh, Chang-Hyuk Lee, Jae-Seok Park, Hong-Bae Yoon, C.S. Choi, Kyoung‐Soo Lee, Jae-Young Cha, Jong-woo Kim, J. Doh, Joo-Sun Choi
The optimum routing methodology for high-performance and fast-layout time DRAM design in the era beyond 0.2 /spl mu/m technology is investigated. The key attributes of the methodology are that it does pitch-based interconnect design (/spl lambda/-rule) and then analyzes the signal integrity through hierarchical interconnect modeling. The final goal of this work is to make the CAD tool for designing the IP-based logic blocks with interconnect net modeling instead of feature-based interconnect parasitic modeling.
{"title":"An effective routing methodology in the era of 0.2 /spl mu/m and beyond technologies for reducing the DRAM design cost","authors":"J. Wee, Phil-Jung Kim, H. Cho, J. Oh, Chang-Hyuk Lee, Jae-Seok Park, Hong-Bae Yoon, C.S. Choi, Kyoung‐Soo Lee, Jae-Young Cha, Jong-woo Kim, J. Doh, Joo-Sun Choi","doi":"10.1109/APASIC.1999.824116","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824116","url":null,"abstract":"The optimum routing methodology for high-performance and fast-layout time DRAM design in the era beyond 0.2 /spl mu/m technology is investigated. The key attributes of the methodology are that it does pitch-based interconnect design (/spl lambda/-rule) and then analyzes the signal integrity through hierarchical interconnect modeling. The final goal of this work is to make the CAD tool for designing the IP-based logic blocks with interconnect net modeling instead of feature-based interconnect parasitic modeling.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121151172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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