Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824072
Myung-Ryul Choi, Jin-Sung Park
Simple analog nonlinear circuits are proposed for implementing neural networks using standard CMOS technology. Three analog nonlinear circuits are proposed: a nonlinear difference circuit, a nonlinear synapse circuit and a nonlinear multiplier (which is composed of the proposed nonlinear difference circuit and the proposed nonlinear synapse circuit.) The proposed multiplier takes less silicon area than the conventional linear multipliers do. The proposed nonlinear circuits are fully simulated using HPSICE. The proposed nonlinear circuits are applied for implementation of multi-layered feedforward circuits and MEBP (modified error backpropagation) learning circuitry. The implemented neural networks have been simulated using HSPICE circuit simulator and produce an output voltage, which is uniquely determined by any pair of learning input patterns. The proposed nonlinear circuits are very suitable for future implementation of the large-scale neural networks with learning.
{"title":"Simple analog nonlinear circuits for neural networks","authors":"Myung-Ryul Choi, Jin-Sung Park","doi":"10.1109/APASIC.1999.824072","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824072","url":null,"abstract":"Simple analog nonlinear circuits are proposed for implementing neural networks using standard CMOS technology. Three analog nonlinear circuits are proposed: a nonlinear difference circuit, a nonlinear synapse circuit and a nonlinear multiplier (which is composed of the proposed nonlinear difference circuit and the proposed nonlinear synapse circuit.) The proposed multiplier takes less silicon area than the conventional linear multipliers do. The proposed nonlinear circuits are fully simulated using HPSICE. The proposed nonlinear circuits are applied for implementation of multi-layered feedforward circuits and MEBP (modified error backpropagation) learning circuitry. The implemented neural networks have been simulated using HSPICE circuit simulator and produce an output voltage, which is uniquely determined by any pair of learning input patterns. The proposed nonlinear circuits are very suitable for future implementation of the large-scale neural networks with learning.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115874553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
IP design of a complete, reconfigurable baseline JPEG encoder is presented in this paper. It features completely JFIF (JPEG File Interchange Format) compatible bit-stream output and a user-defined quantization table that can be re-configured at the run time and the compiling time. Thus, various hardware configurations can be easily achieved. Besides, modularized design is practiced such that smooth data flow in this pipelined architecture can be easily achieved by utilizing a central controller. This technique improves system performance greatly.
{"title":"IP design of a reconfigurable baseline JPEG coding","authors":"Hao-Chieh Chang, Li-Lin Chen, Chung-Jr Lian, Yung-Chi Chang, Liang-Gee Chen","doi":"10.1109/APASIC.1999.824048","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824048","url":null,"abstract":"IP design of a complete, reconfigurable baseline JPEG encoder is presented in this paper. It features completely JFIF (JPEG File Interchange Format) compatible bit-stream output and a user-defined quantization table that can be re-configured at the run time and the compiling time. Thus, various hardware configurations can be easily achieved. Besides, modularized design is practiced such that smooth data flow in this pipelined architecture can be easily achieved by utilizing a central controller. This technique improves system performance greatly.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129636994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824025
H. Jang, S. Kim, Young-hoon Chang
Low power in digital signal processor design has been a critical design constraint since portable battery operated devices prevailed. Most of the power dissipation of a processor is in the clock network and the on-chip memory. By optimizing the critical path of the processor we could reduce the power of clock network. We propose an energy-efficient instruction set architecture to reduce the power consumption of the program memory access. We applied it to a digital hearing aid, and reduced the program memory size by approximately 75%.
{"title":"A digital signal processor for low power","authors":"H. Jang, S. Kim, Young-hoon Chang","doi":"10.1109/APASIC.1999.824025","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824025","url":null,"abstract":"Low power in digital signal processor design has been a critical design constraint since portable battery operated devices prevailed. Most of the power dissipation of a processor is in the clock network and the on-chip memory. By optimizing the critical path of the processor we could reduce the power of clock network. We propose an energy-efficient instruction set architecture to reduce the power consumption of the program memory access. We applied it to a digital hearing aid, and reduced the program memory size by approximately 75%.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133798405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824067
Sang-Won Lee, Y. Song, Soo-Won Kim, H. Oh, Woo-Jang Hahn
A microarchitecture of a processor named RAPTOR is described. RAPTOR is a single chip multiprocessor developed for exploiting thread-level parallelism. RAPTOR includes four identical processors, a graphics coprocessor, and an external cache controller. Each processor has a 16 KB primary cache and implements SPARC version 9 instruction set architecture. The external cache controller provides direct connection to a large external second level cache. RAPTOR is designed as a building block of multiprocessor systems such as symmetric multiprocessor machines.
{"title":"RAPTOR: a single chip multiprocessor","authors":"Sang-Won Lee, Y. Song, Soo-Won Kim, H. Oh, Woo-Jang Hahn","doi":"10.1109/APASIC.1999.824067","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824067","url":null,"abstract":"A microarchitecture of a processor named RAPTOR is described. RAPTOR is a single chip multiprocessor developed for exploiting thread-level parallelism. RAPTOR includes four identical processors, a graphics coprocessor, and an external cache controller. Each processor has a 16 KB primary cache and implements SPARC version 9 instruction set architecture. The external cache controller provides direct connection to a large external second level cache. RAPTOR is designed as a building block of multiprocessor systems such as symmetric multiprocessor machines.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115650558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824118
B. Ko, Dong-Bin Cheon, Seong-Wook Kim, Jin-Su Ko, Jeong-Keun Kim, Byeong-ha Park
This paper presents a quantitative analysis on the cross modulation between transmitter CDMA leakage signal and single tone jammer signal, and some design guidelines for overcoming it in receiver design. The analysis shows that duplexer isolation and LNA IIP3 are responsible for the cross modulation. It also shows that LNA IIP3 required for meeting J-STD-018 PCS specification is about 4-5 dBm with duplexer isolation of 50 dB.
{"title":"A nightmare for CDMA RF receiver: the cross modulation","authors":"B. Ko, Dong-Bin Cheon, Seong-Wook Kim, Jin-Su Ko, Jeong-Keun Kim, Byeong-ha Park","doi":"10.1109/APASIC.1999.824118","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824118","url":null,"abstract":"This paper presents a quantitative analysis on the cross modulation between transmitter CDMA leakage signal and single tone jammer signal, and some design guidelines for overcoming it in receiver design. The analysis shows that duplexer isolation and LNA IIP3 are responsible for the cross modulation. It also shows that LNA IIP3 required for meeting J-STD-018 PCS specification is about 4-5 dBm with duplexer isolation of 50 dB.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127692806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824054
Kuo-Hsing Cheng, Ven-Chieh Hsieh
A new 3-input XOR gate based upon the pass transistor design methodology for low-voltage, low-voltage high-speed applications is proposed. Five existing circuits are compared with the new proposed gate. It is shown that the proposed new circuit has at least 50% improvement in power-delay product than that of the CPL structure and the CMOS structure. Moreover, the proposed new circuit can also be operated as low as 1 V. Thus, the proposed new circuit is suitable for low-power, low-voltage and high-speed applications.
{"title":"High efficient 3-input XOR for low-voltage low-power high-speed applications","authors":"Kuo-Hsing Cheng, Ven-Chieh Hsieh","doi":"10.1109/APASIC.1999.824054","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824054","url":null,"abstract":"A new 3-input XOR gate based upon the pass transistor design methodology for low-voltage, low-voltage high-speed applications is proposed. Five existing circuits are compared with the new proposed gate. It is shown that the proposed new circuit has at least 50% improvement in power-delay product than that of the CPL structure and the CMOS structure. Moreover, the proposed new circuit can also be operated as low as 1 V. Thus, the proposed new circuit is suitable for low-power, low-voltage and high-speed applications.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129028432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824049
Hyunjune Yoo, Ecksang Ko, S. Ong, M. Sunwoo
This paper presents a fixed-point multimedia DSP (MDSP) chip and instruction set for portable multimedia and its chip implementation. MDSP employs parallel processing techniques, such as SIMD, vector processing, and DSP schemes. MDSP can handle 8-, 16-, 32- or 40-bit data and can perform four MAC operations in parallel. In addition, MDSP can complete various vector operations in a cycle. With these features, MDSP can handle both 2D video signal processing and 1D signal processing. The second version of the MDSP chip with 73,095 gates, has been fabricated and is running at 30 MHz.
{"title":"A multimedia DSP chip for portable applications","authors":"Hyunjune Yoo, Ecksang Ko, S. Ong, M. Sunwoo","doi":"10.1109/APASIC.1999.824049","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824049","url":null,"abstract":"This paper presents a fixed-point multimedia DSP (MDSP) chip and instruction set for portable multimedia and its chip implementation. MDSP employs parallel processing techniques, such as SIMD, vector processing, and DSP schemes. MDSP can handle 8-, 16-, 32- or 40-bit data and can perform four MAC operations in parallel. In addition, MDSP can complete various vector operations in a cycle. With these features, MDSP can handle both 2D video signal processing and 1D signal processing. The second version of the MDSP chip with 73,095 gates, has been fabricated and is running at 30 MHz.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127555727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824023
S. Lee, Chan Kim, Jae-Guen Kim
As the various types of application services are increased in the ATM (asynchronous transfer mode) network, it becomes a very important requirement for ATM network equipment to provide for higher transfer rate and to detect the network failure or the service degradation. In order to meet these requirements we developed a monolithic single chip device which can handle VPI/VCI address translation, routing, UPC (usage parameter control), QOS (quality of service) buffering, ABR (available bit rate) processing and OAM (operation and management) processing for 65,536 VCs (virtual circuits) in real time. This paper describes architectural design and implementation of a 622 Mbps ATM layer ASIC (application specific integrated circuit). This ASIC is applicable to develop the network equipment in B-ISDN. This supports both NNI (network-network interface) and UNI (user-network interface).
{"title":"Architectural design and implementation of full ATM layer functions for the cost effective access network","authors":"S. Lee, Chan Kim, Jae-Guen Kim","doi":"10.1109/APASIC.1999.824023","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824023","url":null,"abstract":"As the various types of application services are increased in the ATM (asynchronous transfer mode) network, it becomes a very important requirement for ATM network equipment to provide for higher transfer rate and to detect the network failure or the service degradation. In order to meet these requirements we developed a monolithic single chip device which can handle VPI/VCI address translation, routing, UPC (usage parameter control), QOS (quality of service) buffering, ABR (available bit rate) processing and OAM (operation and management) processing for 65,536 VCs (virtual circuits) in real time. This paper describes architectural design and implementation of a 622 Mbps ATM layer ASIC (application specific integrated circuit). This ASIC is applicable to develop the network equipment in B-ISDN. This supports both NNI (network-network interface) and UNI (user-network interface).","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128674875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824056
Hyung Hoon Kim, K. Yoon
An 12 bit 20 MS/s current-mode folding and interpolation analog to digital converter (ADC) with multiplied folding amplifiers is proposed in this paper. A current-mode multiplied folding amplifier is employed not only to reduce the number of reference current sources, but also to decrease the power dissipation within the ADC. The proposed ADC is implemented by a 0.65 /spl mu/m n-well CMOS single poly/double metal process. The simulation result shows a differential nonlinearity (DNL) of /spl plusmn/0.5 LSB, an integral nonlinearity (INL) of /spl plusmn/1.0 LSB, the power dissipation of 280 mW with a power supply of 5 V.
{"title":"A 12 bit current-mode folding/interpolation CMOS A/D converter with 2 step architecture","authors":"Hyung Hoon Kim, K. Yoon","doi":"10.1109/APASIC.1999.824056","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824056","url":null,"abstract":"An 12 bit 20 MS/s current-mode folding and interpolation analog to digital converter (ADC) with multiplied folding amplifiers is proposed in this paper. A current-mode multiplied folding amplifier is employed not only to reduce the number of reference current sources, but also to decrease the power dissipation within the ADC. The proposed ADC is implemented by a 0.65 /spl mu/m n-well CMOS single poly/double metal process. The simulation result shows a differential nonlinearity (DNL) of /spl plusmn/0.5 LSB, an integral nonlinearity (INL) of /spl plusmn/1.0 LSB, the power dissipation of 280 mW with a power supply of 5 V.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116875945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824087
Sung-Dae Lee, Sang-Kyu Kim, W. Lee
In this paper we introduce an on-chip automatic tuning circuit using a proposed voltage-controlled oscillator. The prepared on-chip automatic tuning circuit is designed in a 0.65 /spl mu/m 3.3 V CMOS process for tuning of the passive component variation. This tuning circuit could reduce the large differences between code values and real output values, however, the dual slope tuning circuit cannot reduce them. Also it also does not generate signal modulation because the tuning codes are fixed in the normal operation The proposed on-chip automatic tuning circuit could increase the accuracy of the passive component and reduce the complexity of the tuning circuit. Since the proposed on-chip automatic tuning circuit operates at several hundreds MHz speed, it can be applied to real time operation especially a calibration circuit for a high speed A/D converter. It may be able to compensate for the variation of passive components within a maximum range of /spl plusmn/1.0% at /spl plusmn/56% RC time constant variation of the detecting integrator.
本文介绍了一种基于压控振荡器的片上自动调谐电路。所制备的片上自动调谐电路在0.65 /spl mu/m 3.3 V CMOS工艺下设计，用于无源元件变化的调谐。该调谐电路可以减小编码值与实际输出值之间的较大差异，而双斜率调谐电路不能减小编码值与实际输出值之间的较大差异。由于正常工作时调谐码是固定的，因此不会产生信号调制。本文提出的片上自动调谐电路可以提高无源器件的精度，降低调谐电路的复杂性。由于所提出的片上自动调谐电路的工作速度可达数百MHz，因此可以应用于实时操作，特别是高速a /D转换器的校准电路。在检测积分器的/spl plusmn/56% RC时间常数变化时，可以在/spl plusmn/1.0%的最大范围内补偿无源分量的变化。
{"title":"An on-chip automatic tuning circuit with VCO for multi-bit A/D-D/A calibration","authors":"Sung-Dae Lee, Sang-Kyu Kim, W. Lee","doi":"10.1109/APASIC.1999.824087","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824087","url":null,"abstract":"In this paper we introduce an on-chip automatic tuning circuit using a proposed voltage-controlled oscillator. The prepared on-chip automatic tuning circuit is designed in a 0.65 /spl mu/m 3.3 V CMOS process for tuning of the passive component variation. This tuning circuit could reduce the large differences between code values and real output values, however, the dual slope tuning circuit cannot reduce them. Also it also does not generate signal modulation because the tuning codes are fixed in the normal operation The proposed on-chip automatic tuning circuit could increase the accuracy of the passive component and reduce the complexity of the tuning circuit. Since the proposed on-chip automatic tuning circuit operates at several hundreds MHz speed, it can be applied to real time operation especially a calibration circuit for a high speed A/D converter. It may be able to compensate for the variation of passive components within a maximum range of /spl plusmn/1.0% at /spl plusmn/56% RC time constant variation of the detecting integrator.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125520157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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