Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824034
J. Ryu, S. C. Kim, J.D. Cho, H.W. Park, Y. Chang
This paper presents a new algorithm for a lower power Add-Compare-Select (ACS) architecture and glitch minimization for the Viterbi decoder which can reduce the complexity of the computation using HSPICE. Our experimental results show an average 7% reduction in power with the same latency at a cost of 3% increase in area compared with the ACS unit introduced by Tsui et al. (1999).
{"title":"A new lower power Viterbi decoder architecture with glitch reduction","authors":"J. Ryu, S. C. Kim, J.D. Cho, H.W. Park, Y. Chang","doi":"10.1109/APASIC.1999.824034","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824034","url":null,"abstract":"This paper presents a new algorithm for a lower power Add-Compare-Select (ACS) architecture and glitch minimization for the Viterbi decoder which can reduce the complexity of the computation using HSPICE. Our experimental results show an average 7% reduction in power with the same latency at a cost of 3% increase in area compared with the ACS unit introduced by Tsui et al. (1999).","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131193526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824059
Jin Park, Seung-Chul Lee, Seunghoon Lee
This paper describes a 10 b 70 MHz CMOS digital-to-analog converter (DAC) for video applications. The proposed 10 b DAC is composed of a unit decoded matrix for 7 MSB's and a binary weighted array for 3 LSBs, considering linearity, power consumption, routing area, and glitch energy. A new switching scheme for the unit decoded matrix is developed to improve linearity further. Cascode current sources and differential switches with the proposed new deglitching circuit improve dynamic performance. The fabricated and measured prototype DAC in a 0.8 um double-poly double-metal n-well CMOS process typically shows a spurious free dynamic range of 55 dB and a total harmonic distortion of -49 dB at a 3 V supply voltage and a 70 MHz update rate with a 120 mW power consumption. The measured differential and integral nonlinearities are /spl plusmn/0.69 LSB and /spl plusmn/0.79 LSB at a 10 b level, respectively.
{"title":"A 3 V 10 b 70 MHz digital-to-analog converter for video applications","authors":"Jin Park, Seung-Chul Lee, Seunghoon Lee","doi":"10.1109/APASIC.1999.824059","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824059","url":null,"abstract":"This paper describes a 10 b 70 MHz CMOS digital-to-analog converter (DAC) for video applications. The proposed 10 b DAC is composed of a unit decoded matrix for 7 MSB's and a binary weighted array for 3 LSBs, considering linearity, power consumption, routing area, and glitch energy. A new switching scheme for the unit decoded matrix is developed to improve linearity further. Cascode current sources and differential switches with the proposed new deglitching circuit improve dynamic performance. The fabricated and measured prototype DAC in a 0.8 um double-poly double-metal n-well CMOS process typically shows a spurious free dynamic range of 55 dB and a total harmonic distortion of -49 dB at a 3 V supply voltage and a 70 MHz update rate with a 120 mW power consumption. The measured differential and integral nonlinearities are /spl plusmn/0.69 LSB and /spl plusmn/0.79 LSB at a 10 b level, respectively.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124323275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824036
Sun-Mo Hwang, G. Moon, Seong-Ho Song
The design of a GHz I-Q and Signal CMOS Generator using a Cellular Oscillator Network architecture is presented and analyzed. With its high speed for settling and easy frequency controllability, this I-Q signal generation method can be used in RF communication systems, where GHz range quadrature signals are needed. Also, a technique is presented for a sleeping mode with a small settling time. This model is simulated and proved with typical 3 V, 0.5 /spl mu/ CMOS N-well process parameters.
{"title":"A GHz I-Q quadrature signal generator using cellular oscillator network","authors":"Sun-Mo Hwang, G. Moon, Seong-Ho Song","doi":"10.1109/APASIC.1999.824036","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824036","url":null,"abstract":"The design of a GHz I-Q and Signal CMOS Generator using a Cellular Oscillator Network architecture is presented and analyzed. With its high speed for settling and easy frequency controllability, this I-Q signal generation method can be used in RF communication systems, where GHz range quadrature signals are needed. Also, a technique is presented for a sleeping mode with a small settling time. This model is simulated and proved with typical 3 V, 0.5 /spl mu/ CMOS N-well process parameters.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124981564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824052
Beom-Seon Ryu, Hyoung Sok Oh, Kie Hak Shim, K. Lee, Taewon Cho
A low power 16-b ALU has been designed at the transistor level. The designed ALU performs 16 instructions and has a two-stage pipelined architecture. For low power consumption we propose a new ALU architecture which has efficient propagation (P) and generation (G) block schemes of ELM adder. The adder of the proposed ALU is disabled while the logic operation is performed and vice versa. Outputs of each P block are separated to the dual output bus to reduce switching capacitance during the ALU operation. The proposed ALU was simulated with O.6/spl mu/m single-poly triple-metal CMOS process. As a result of post-layout simulations, addition time of the core is about 5ns with 3. 3 V supply voltage and the average power consumption of the core was 54 mW at 200 MHz.
{"title":"Multi-level approaches to low power 16-bit ALU design","authors":"Beom-Seon Ryu, Hyoung Sok Oh, Kie Hak Shim, K. Lee, Taewon Cho","doi":"10.1109/APASIC.1999.824052","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824052","url":null,"abstract":"A low power 16-b ALU has been designed at the transistor level. The designed ALU performs 16 instructions and has a two-stage pipelined architecture. For low power consumption we propose a new ALU architecture which has efficient propagation (P) and generation (G) block schemes of ELM adder. The adder of the proposed ALU is disabled while the logic operation is performed and vice versa. Outputs of each P block are separated to the dual output bus to reduce switching capacitance during the ALU operation. The proposed ALU was simulated with O.6/spl mu/m single-poly triple-metal CMOS process. As a result of post-layout simulations, addition time of the core is about 5ns with 3. 3 V supply voltage and the average power consumption of the core was 54 mW at 200 MHz.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"423 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123387195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824037
W.-K. Hong, Seungyup Lee, Shin-Dug Kim
The cache structures in the existing VLIW systems are largely classified into the unpacked cache and the full packed cache. The degree of memory utilization in the unpacked cache is very low because instructions are loaded in the form of the unfolded instruction. On the contrary, the full packed cache loads instructions in the form of the folded instruction in order to enhance the degree of memory utilization. But the fetch time gets longer because the lengths of instructions are different. This paper proposes a new instruction format and a cache structure to eliminate NOPs. The experimental results show that the best performance can be achieved in the memory system composed of the partial packed cache as the first level cache and the full packed cache as the second level cache.
{"title":"A semi-folded instruction format for VLIW architecture","authors":"W.-K. Hong, Seungyup Lee, Shin-Dug Kim","doi":"10.1109/APASIC.1999.824037","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824037","url":null,"abstract":"The cache structures in the existing VLIW systems are largely classified into the unpacked cache and the full packed cache. The degree of memory utilization in the unpacked cache is very low because instructions are loaded in the form of the unfolded instruction. On the contrary, the full packed cache loads instructions in the form of the folded instruction in order to enhance the degree of memory utilization. But the fetch time gets longer because the lengths of instructions are different. This paper proposes a new instruction format and a cache structure to eliminate NOPs. The experimental results show that the best performance can be achieved in the memory system composed of the partial packed cache as the first level cache and the full packed cache as the second level cache.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125247623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824122
Ki-Whan Song, K. Kyung, Changhyun Kim
This paper describes a methodology to analyze a long periodic channel. The work was performed for the RAMBUS system. The analysis is focused on DRAM loading effects on electrical signal integrity. We suggest some proper windows of DRAM input impedance for 800 MHz signaling. Without additional constraints to /spl Delta/Lin (pin-to-pin Lin differences), the skew amounts to 45 ps, which can be lowered to 22 ps by the control of /spl Delta/Lin within 1.5 nH.
{"title":"Optimum windows of DRAM input impedance (Lin,Cin,Rin) on data bus for 800 MHz signaling","authors":"Ki-Whan Song, K. Kyung, Changhyun Kim","doi":"10.1109/APASIC.1999.824122","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824122","url":null,"abstract":"This paper describes a methodology to analyze a long periodic channel. The work was performed for the RAMBUS system. The analysis is focused on DRAM loading effects on electrical signal integrity. We suggest some proper windows of DRAM input impedance for 800 MHz signaling. Without additional constraints to /spl Delta/Lin (pin-to-pin Lin differences), the skew amounts to 45 ps, which can be lowered to 22 ps by the control of /spl Delta/Lin within 1.5 nH.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"353 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125637793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824014
Seong-Jo Na, M.M.-O. Lee, Ting-Hong Chung, Seung-Min Lee, J.H. Kim
Multimedia service with audio and video have become most desirable as the ADSL technology ideally converted from 1.5 Mbps full duplex HDSL technology via two twist-pair into 6.144 Mbps transmission technology via single twist-pair. This results in an interactive transmission service of T1 & E1 class data using the subscriber line without repeaters. The ADSL transceiver chipset is configured by DMT (Discrete Multi Tone modulation) scheme and RISC-based DSP core structure. Our ADSL chip is to be used in VOD, interactive interact service and/or teleconferencing system, etc. The operating frequency and dissipated power of the chip are 40 MHz and 5 W at 5 V.
{"title":"Design and implementation for 125 mW/MIPS ultra-high speed low power asymmetric digital subscriber line transceiver chip","authors":"Seong-Jo Na, M.M.-O. Lee, Ting-Hong Chung, Seung-Min Lee, J.H. Kim","doi":"10.1109/APASIC.1999.824014","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824014","url":null,"abstract":"Multimedia service with audio and video have become most desirable as the ADSL technology ideally converted from 1.5 Mbps full duplex HDSL technology via two twist-pair into 6.144 Mbps transmission technology via single twist-pair. This results in an interactive transmission service of T1 & E1 class data using the subscriber line without repeaters. The ADSL transceiver chipset is configured by DMT (Discrete Multi Tone modulation) scheme and RISC-based DSP core structure. Our ADSL chip is to be used in VOD, interactive interact service and/or teleconferencing system, etc. The operating frequency and dissipated power of the chip are 40 MHz and 5 W at 5 V.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128889482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824100
Yeo-San Song, Jin-Ku Kang
This paper shows a DLL (delay locked loop) which has a mixed-mode tuning capability. The proposed architecture is based on a dual loop which is controlled by peripheral circuits such as FSM (finite state machine) and two phase detectors whose roles are coarse error detection and fine error detection respectively. The main DLL is composed of eight differential delay buffers and generates eight clocks evenly spaced by 45/spl deg/. The second loop is to produce the retimed clock through coarse timing and fine timing using digital and analog phase control. The circuit has the unlimited phase control range due to the dial loop structure. The circuit operates at 500 MHz under 3.3 V supply according to SPICE simulation on the extracted layout. The circuit will be fabricated in 0.6-/spl mu/m CMOS.
本文介绍了一种具有混合模式调优能力的延迟锁环。该结构基于一个由有限状态机(FSM)等外围电路控制的双环和两个相位检测器，其作用分别是粗误差检测和细误差检测。主DLL由8个差分延迟缓冲器组成，产生8个均匀间隔为45/spl度/的时钟。第二个回路是利用数字和模拟相位控制，通过粗定时和精定时产生重定时时钟。由于采用了拨环结构，该电路具有无限的相位控制范围。根据提取的布局上的SPICE仿真，该电路在3.3 V电源下工作在500 MHz。该电路将在0.6-/spl μ m CMOS中制造。
{"title":"A delay locked loop circuit with mixed-mode tuning","authors":"Yeo-San Song, Jin-Ku Kang","doi":"10.1109/APASIC.1999.824100","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824100","url":null,"abstract":"This paper shows a DLL (delay locked loop) which has a mixed-mode tuning capability. The proposed architecture is based on a dual loop which is controlled by peripheral circuits such as FSM (finite state machine) and two phase detectors whose roles are coarse error detection and fine error detection respectively. The main DLL is composed of eight differential delay buffers and generates eight clocks evenly spaced by 45/spl deg/. The second loop is to produce the retimed clock through coarse timing and fine timing using digital and analog phase control. The circuit has the unlimited phase control range due to the dial loop structure. The circuit operates at 500 MHz under 3.3 V supply according to SPICE simulation on the extracted layout. The circuit will be fabricated in 0.6-/spl mu/m CMOS.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129013178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824030
B.G. Song, O. Kwon, I. Chang, H.J. Song, K. Kwack
This paper describes a 1.8 V self-biased complementary folded cascode(SB-CFC) amplifier. We propose a new self biasing scheme for the folded cascode amplifier which eliminates 6 external bias voltages and related biasing circuits. The required minimum power supply voltage is reduced to 1.8 V and the output voltage swings are increased. With our new self-biasing scheme the area and power overhead, susceptibility of the bias lines to noise and crosstalk, and design time are reduced.
{"title":"A 1.8 V self-biased complementary folded cascode amplifier","authors":"B.G. Song, O. Kwon, I. Chang, H.J. Song, K. Kwack","doi":"10.1109/APASIC.1999.824030","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824030","url":null,"abstract":"This paper describes a 1.8 V self-biased complementary folded cascode(SB-CFC) amplifier. We propose a new self biasing scheme for the folded cascode amplifier which eliminates 6 external bias voltages and related biasing circuits. The required minimum power supply voltage is reduced to 1.8 V and the output voltage swings are increased. With our new self-biasing scheme the area and power overhead, susceptibility of the bias lines to noise and crosstalk, and design time are reduced.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127700701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824060
Hee-Cheol Choi, Jaejin Park, Seung-Bin You, Hojin Park, Geun-Soon Kang, Jae-Whui Kim
A calibration-free 3 V 12-bit 20 MSPS pipelined analog-to-digital (A/D) converter was implemented using 0.35 /spl mu/m CMOS technology. The proposed hybrid capacitor switching technique of two feedback capacitors is applied to improve the linearity which is limited by component mismatch depending on the process. Since the proposed technique can be implemented by simple circuits compared with previous self-calibration techniques, it allows smaller area and lower power consumption and it is applicable to general pipelined architectures. Other technique proposed to improve the linearity is a capacitor array layout scheme which is insensitive to the parasitic effect of capacitor top plates. The A/D converter occupies a die area of 2.57 mm/sup 2/ (1260 /spl mu/m/spl times/2040 /spl mu/m) excluding pad ring and dissipates 135 mW at a 20 MHz clock rate with a 3 V single supply. Typical differential nonlinearity (DNL) and integral nonlinearity (INL) are /spl plusmn/0.72 LSB and/spl plusmn/1.22 LSB, respectively.
{"title":"A calibration-free 3.0 V 12-bit 20 MSPS A/D converter","authors":"Hee-Cheol Choi, Jaejin Park, Seung-Bin You, Hojin Park, Geun-Soon Kang, Jae-Whui Kim","doi":"10.1109/APASIC.1999.824060","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824060","url":null,"abstract":"A calibration-free 3 V 12-bit 20 MSPS pipelined analog-to-digital (A/D) converter was implemented using 0.35 /spl mu/m CMOS technology. The proposed hybrid capacitor switching technique of two feedback capacitors is applied to improve the linearity which is limited by component mismatch depending on the process. Since the proposed technique can be implemented by simple circuits compared with previous self-calibration techniques, it allows smaller area and lower power consumption and it is applicable to general pipelined architectures. Other technique proposed to improve the linearity is a capacitor array layout scheme which is insensitive to the parasitic effect of capacitor top plates. The A/D converter occupies a die area of 2.57 mm/sup 2/ (1260 /spl mu/m/spl times/2040 /spl mu/m) excluding pad ring and dissipates 135 mW at a 20 MHz clock rate with a 3 V single supply. Typical differential nonlinearity (DNL) and integral nonlinearity (INL) are /spl plusmn/0.72 LSB and/spl plusmn/1.22 LSB, respectively.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126970937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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