Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824120
S. Yen, Chorng-Kuang Wang
This paper presents a 2 V DS-CDMA programmable digital matched filter with a differential and pipelined structure. A differential PN (Pseudo-Noise) code scheme is adopted to reduce the number of multiplication and summations (M&S). The PDDMF (Pipelined Digital Differential Matched Filter) not only saves hardware and power, but also improves the operation speed, which makes PDDMF more suitable for personal communication at high speed and low power requirements than the conventional approach. The PDDMF, implemented in a 0.6 /spl mu/m CMOS technology, is clocked at 2.5 MHz and consumes 1.6 mW from a single 2 V power supply.
{"title":"A 2 V CMOS programmable pipelined digital differential matched filter for DS-CDMA system","authors":"S. Yen, Chorng-Kuang Wang","doi":"10.1109/APASIC.1999.824120","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824120","url":null,"abstract":"This paper presents a 2 V DS-CDMA programmable digital matched filter with a differential and pipelined structure. A differential PN (Pseudo-Noise) code scheme is adopted to reduce the number of multiplication and summations (M&S). The PDDMF (Pipelined Digital Differential Matched Filter) not only saves hardware and power, but also improves the operation speed, which makes PDDMF more suitable for personal communication at high speed and low power requirements than the conventional approach. The PDDMF, implemented in a 0.6 /spl mu/m CMOS technology, is clocked at 2.5 MHz and consumes 1.6 mW from a single 2 V power supply.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131169312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824034
J. Ryu, S. C. Kim, J.D. Cho, H.W. Park, Y. Chang
This paper presents a new algorithm for a lower power Add-Compare-Select (ACS) architecture and glitch minimization for the Viterbi decoder which can reduce the complexity of the computation using HSPICE. Our experimental results show an average 7% reduction in power with the same latency at a cost of 3% increase in area compared with the ACS unit introduced by Tsui et al. (1999).
{"title":"A new lower power Viterbi decoder architecture with glitch reduction","authors":"J. Ryu, S. C. Kim, J.D. Cho, H.W. Park, Y. Chang","doi":"10.1109/APASIC.1999.824034","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824034","url":null,"abstract":"This paper presents a new algorithm for a lower power Add-Compare-Select (ACS) architecture and glitch minimization for the Viterbi decoder which can reduce the complexity of the computation using HSPICE. Our experimental results show an average 7% reduction in power with the same latency at a cost of 3% increase in area compared with the ACS unit introduced by Tsui et al. (1999).","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131193526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824050
Seung-Min Lee, Jin-H. Chung, Hyung-Seok Yoon, M.M.-O. Lee
In this paper a study has been presented on high speed (HS) and 79 mW low power (LP) 16/spl times/16 MAC performance of XOR-based circuits using transmission gate logic (TG) implemented on 0.6 um CMOS DLP/DLM technology. It is shown that our proposed MAC results in better performance than other published MACs due to no DC leakage currents for low power and bypassing unnecessary switching activities with latches before and after the multiplier for high speed.
本文研究了在0.6 um CMOS DLP/DLM技术上采用传输门逻辑(TG)实现的基于xor电路的高速(HS)和79 mW低功耗(LP) 16/spl倍/16 MAC性能。结果表明，我们提出的MAC比其他已发表的MAC具有更好的性能，因为它在低功率下没有直流漏电流，并且在高速乘法器前后通过锁存器绕过不必要的开关活动。
{"title":"66 M/70 mW HS and ultra-low power 16/spl times/16 MAC design using TG for web-based multimedia system","authors":"Seung-Min Lee, Jin-H. Chung, Hyung-Seok Yoon, M.M.-O. Lee","doi":"10.1109/APASIC.1999.824050","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824050","url":null,"abstract":"In this paper a study has been presented on high speed (HS) and 79 mW low power (LP) 16/spl times/16 MAC performance of XOR-based circuits using transmission gate logic (TG) implemented on 0.6 um CMOS DLP/DLM technology. It is shown that our proposed MAC results in better performance than other published MACs due to no DC leakage currents for low power and bypassing unnecessary switching activities with latches before and after the multiplier for high speed.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"272 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122769734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824052
Beom-Seon Ryu, Hyoung Sok Oh, Kie Hak Shim, K. Lee, Taewon Cho
A low power 16-b ALU has been designed at the transistor level. The designed ALU performs 16 instructions and has a two-stage pipelined architecture. For low power consumption we propose a new ALU architecture which has efficient propagation (P) and generation (G) block schemes of ELM adder. The adder of the proposed ALU is disabled while the logic operation is performed and vice versa. Outputs of each P block are separated to the dual output bus to reduce switching capacitance during the ALU operation. The proposed ALU was simulated with O.6/spl mu/m single-poly triple-metal CMOS process. As a result of post-layout simulations, addition time of the core is about 5ns with 3. 3 V supply voltage and the average power consumption of the core was 54 mW at 200 MHz.
{"title":"Multi-level approaches to low power 16-bit ALU design","authors":"Beom-Seon Ryu, Hyoung Sok Oh, Kie Hak Shim, K. Lee, Taewon Cho","doi":"10.1109/APASIC.1999.824052","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824052","url":null,"abstract":"A low power 16-b ALU has been designed at the transistor level. The designed ALU performs 16 instructions and has a two-stage pipelined architecture. For low power consumption we propose a new ALU architecture which has efficient propagation (P) and generation (G) block schemes of ELM adder. The adder of the proposed ALU is disabled while the logic operation is performed and vice versa. Outputs of each P block are separated to the dual output bus to reduce switching capacitance during the ALU operation. The proposed ALU was simulated with O.6/spl mu/m single-poly triple-metal CMOS process. As a result of post-layout simulations, addition time of the core is about 5ns with 3. 3 V supply voltage and the average power consumption of the core was 54 mW at 200 MHz.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"423 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123387195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824072
Myung-Ryul Choi, Jin-Sung Park
Simple analog nonlinear circuits are proposed for implementing neural networks using standard CMOS technology. Three analog nonlinear circuits are proposed: a nonlinear difference circuit, a nonlinear synapse circuit and a nonlinear multiplier (which is composed of the proposed nonlinear difference circuit and the proposed nonlinear synapse circuit.) The proposed multiplier takes less silicon area than the conventional linear multipliers do. The proposed nonlinear circuits are fully simulated using HPSICE. The proposed nonlinear circuits are applied for implementation of multi-layered feedforward circuits and MEBP (modified error backpropagation) learning circuitry. The implemented neural networks have been simulated using HSPICE circuit simulator and produce an output voltage, which is uniquely determined by any pair of learning input patterns. The proposed nonlinear circuits are very suitable for future implementation of the large-scale neural networks with learning.
{"title":"Simple analog nonlinear circuits for neural networks","authors":"Myung-Ryul Choi, Jin-Sung Park","doi":"10.1109/APASIC.1999.824072","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824072","url":null,"abstract":"Simple analog nonlinear circuits are proposed for implementing neural networks using standard CMOS technology. Three analog nonlinear circuits are proposed: a nonlinear difference circuit, a nonlinear synapse circuit and a nonlinear multiplier (which is composed of the proposed nonlinear difference circuit and the proposed nonlinear synapse circuit.) The proposed multiplier takes less silicon area than the conventional linear multipliers do. The proposed nonlinear circuits are fully simulated using HPSICE. The proposed nonlinear circuits are applied for implementation of multi-layered feedforward circuits and MEBP (modified error backpropagation) learning circuitry. The implemented neural networks have been simulated using HSPICE circuit simulator and produce an output voltage, which is uniquely determined by any pair of learning input patterns. The proposed nonlinear circuits are very suitable for future implementation of the large-scale neural networks with learning.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115874553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824037
W.-K. Hong, Seungyup Lee, Shin-Dug Kim
The cache structures in the existing VLIW systems are largely classified into the unpacked cache and the full packed cache. The degree of memory utilization in the unpacked cache is very low because instructions are loaded in the form of the unfolded instruction. On the contrary, the full packed cache loads instructions in the form of the folded instruction in order to enhance the degree of memory utilization. But the fetch time gets longer because the lengths of instructions are different. This paper proposes a new instruction format and a cache structure to eliminate NOPs. The experimental results show that the best performance can be achieved in the memory system composed of the partial packed cache as the first level cache and the full packed cache as the second level cache.
{"title":"A semi-folded instruction format for VLIW architecture","authors":"W.-K. Hong, Seungyup Lee, Shin-Dug Kim","doi":"10.1109/APASIC.1999.824037","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824037","url":null,"abstract":"The cache structures in the existing VLIW systems are largely classified into the unpacked cache and the full packed cache. The degree of memory utilization in the unpacked cache is very low because instructions are loaded in the form of the unfolded instruction. On the contrary, the full packed cache loads instructions in the form of the folded instruction in order to enhance the degree of memory utilization. But the fetch time gets longer because the lengths of instructions are different. This paper proposes a new instruction format and a cache structure to eliminate NOPs. The experimental results show that the best performance can be achieved in the memory system composed of the partial packed cache as the first level cache and the full packed cache as the second level cache.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125247623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
IP design of a complete, reconfigurable baseline JPEG encoder is presented in this paper. It features completely JFIF (JPEG File Interchange Format) compatible bit-stream output and a user-defined quantization table that can be re-configured at the run time and the compiling time. Thus, various hardware configurations can be easily achieved. Besides, modularized design is practiced such that smooth data flow in this pipelined architecture can be easily achieved by utilizing a central controller. This technique improves system performance greatly.
{"title":"IP design of a reconfigurable baseline JPEG coding","authors":"Hao-Chieh Chang, Li-Lin Chen, Chung-Jr Lian, Yung-Chi Chang, Liang-Gee Chen","doi":"10.1109/APASIC.1999.824048","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824048","url":null,"abstract":"IP design of a complete, reconfigurable baseline JPEG encoder is presented in this paper. It features completely JFIF (JPEG File Interchange Format) compatible bit-stream output and a user-defined quantization table that can be re-configured at the run time and the compiling time. Thus, various hardware configurations can be easily achieved. Besides, modularized design is practiced such that smooth data flow in this pipelined architecture can be easily achieved by utilizing a central controller. This technique improves system performance greatly.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129636994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824060
Hee-Cheol Choi, Jaejin Park, Seung-Bin You, Hojin Park, Geun-Soon Kang, Jae-Whui Kim
A calibration-free 3 V 12-bit 20 MSPS pipelined analog-to-digital (A/D) converter was implemented using 0.35 /spl mu/m CMOS technology. The proposed hybrid capacitor switching technique of two feedback capacitors is applied to improve the linearity which is limited by component mismatch depending on the process. Since the proposed technique can be implemented by simple circuits compared with previous self-calibration techniques, it allows smaller area and lower power consumption and it is applicable to general pipelined architectures. Other technique proposed to improve the linearity is a capacitor array layout scheme which is insensitive to the parasitic effect of capacitor top plates. The A/D converter occupies a die area of 2.57 mm/sup 2/ (1260 /spl mu/m/spl times/2040 /spl mu/m) excluding pad ring and dissipates 135 mW at a 20 MHz clock rate with a 3 V single supply. Typical differential nonlinearity (DNL) and integral nonlinearity (INL) are /spl plusmn/0.72 LSB and/spl plusmn/1.22 LSB, respectively.
{"title":"A calibration-free 3.0 V 12-bit 20 MSPS A/D converter","authors":"Hee-Cheol Choi, Jaejin Park, Seung-Bin You, Hojin Park, Geun-Soon Kang, Jae-Whui Kim","doi":"10.1109/APASIC.1999.824060","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824060","url":null,"abstract":"A calibration-free 3 V 12-bit 20 MSPS pipelined analog-to-digital (A/D) converter was implemented using 0.35 /spl mu/m CMOS technology. The proposed hybrid capacitor switching technique of two feedback capacitors is applied to improve the linearity which is limited by component mismatch depending on the process. Since the proposed technique can be implemented by simple circuits compared with previous self-calibration techniques, it allows smaller area and lower power consumption and it is applicable to general pipelined architectures. Other technique proposed to improve the linearity is a capacitor array layout scheme which is insensitive to the parasitic effect of capacitor top plates. The A/D converter occupies a die area of 2.57 mm/sup 2/ (1260 /spl mu/m/spl times/2040 /spl mu/m) excluding pad ring and dissipates 135 mW at a 20 MHz clock rate with a 3 V single supply. Typical differential nonlinearity (DNL) and integral nonlinearity (INL) are /spl plusmn/0.72 LSB and/spl plusmn/1.22 LSB, respectively.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126970937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824014
Seong-Jo Na, M.M.-O. Lee, Ting-Hong Chung, Seung-Min Lee, J.H. Kim
Multimedia service with audio and video have become most desirable as the ADSL technology ideally converted from 1.5 Mbps full duplex HDSL technology via two twist-pair into 6.144 Mbps transmission technology via single twist-pair. This results in an interactive transmission service of T1 & E1 class data using the subscriber line without repeaters. The ADSL transceiver chipset is configured by DMT (Discrete Multi Tone modulation) scheme and RISC-based DSP core structure. Our ADSL chip is to be used in VOD, interactive interact service and/or teleconferencing system, etc. The operating frequency and dissipated power of the chip are 40 MHz and 5 W at 5 V.
{"title":"Design and implementation for 125 mW/MIPS ultra-high speed low power asymmetric digital subscriber line transceiver chip","authors":"Seong-Jo Na, M.M.-O. Lee, Ting-Hong Chung, Seung-Min Lee, J.H. Kim","doi":"10.1109/APASIC.1999.824014","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824014","url":null,"abstract":"Multimedia service with audio and video have become most desirable as the ADSL technology ideally converted from 1.5 Mbps full duplex HDSL technology via two twist-pair into 6.144 Mbps transmission technology via single twist-pair. This results in an interactive transmission service of T1 & E1 class data using the subscriber line without repeaters. The ADSL transceiver chipset is configured by DMT (Discrete Multi Tone modulation) scheme and RISC-based DSP core structure. Our ADSL chip is to be used in VOD, interactive interact service and/or teleconferencing system, etc. The operating frequency and dissipated power of the chip are 40 MHz and 5 W at 5 V.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128889482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824030
B.G. Song, O. Kwon, I. Chang, H.J. Song, K. Kwack
This paper describes a 1.8 V self-biased complementary folded cascode(SB-CFC) amplifier. We propose a new self biasing scheme for the folded cascode amplifier which eliminates 6 external bias voltages and related biasing circuits. The required minimum power supply voltage is reduced to 1.8 V and the output voltage swings are increased. With our new self-biasing scheme the area and power overhead, susceptibility of the bias lines to noise and crosstalk, and design time are reduced.
{"title":"A 1.8 V self-biased complementary folded cascode amplifier","authors":"B.G. Song, O. Kwon, I. Chang, H.J. Song, K. Kwack","doi":"10.1109/APASIC.1999.824030","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824030","url":null,"abstract":"This paper describes a 1.8 V self-biased complementary folded cascode(SB-CFC) amplifier. We propose a new self biasing scheme for the folded cascode amplifier which eliminates 6 external bias voltages and related biasing circuits. The required minimum power supply voltage is reduced to 1.8 V and the output voltage swings are increased. With our new self-biasing scheme the area and power overhead, susceptibility of the bias lines to noise and crosstalk, and design time are reduced.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127700701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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