Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962972
D. Choi, D. Nozu, K. Hasebe, T. Shibata, K. Nakao, M. Izuha, H. Akahori, T. Aoyama, K. Eguchi, K. Hieda, T. Arikado, K. Okumura
The gas cleaning of the hot-wall batch type Ru CVD reactor by oxygen was investigated. The cleaning mechanism is considered as follows. Below 800/spl deg/C, Ru film is oxidized and forms RuO/sub 2/ which is not volatile. But above 800/spl deg/C, RuO/sub 2/ film, which is formed at first, is oxidized again to form RuO/sub 4/. Since RuO/sub 4/ is volatile, it evaporates easily. High temperature, low pressure and high oxygen flow rate were required to obtain fast Ru etching rate. With these optimum cleaning conditions by design of experiments (DOE), 30-nm-thick Ru film was removed completely in 20 minutes. We could accomplish this in situ oxygen gas cleaning effectively in short time by using hot-wall batch type Ru CVD equipment, which has high heating and cooling rate characteristics.
{"title":"Cleaning technique of hot-wall batch type Ru CVD equipment by oxygen gas","authors":"D. Choi, D. Nozu, K. Hasebe, T. Shibata, K. Nakao, M. Izuha, H. Akahori, T. Aoyama, K. Eguchi, K. Hieda, T. Arikado, K. Okumura","doi":"10.1109/ISSM.2001.962972","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962972","url":null,"abstract":"The gas cleaning of the hot-wall batch type Ru CVD reactor by oxygen was investigated. The cleaning mechanism is considered as follows. Below 800/spl deg/C, Ru film is oxidized and forms RuO/sub 2/ which is not volatile. But above 800/spl deg/C, RuO/sub 2/ film, which is formed at first, is oxidized again to form RuO/sub 4/. Since RuO/sub 4/ is volatile, it evaporates easily. High temperature, low pressure and high oxygen flow rate were required to obtain fast Ru etching rate. With these optimum cleaning conditions by design of experiments (DOE), 30-nm-thick Ru film was removed completely in 20 minutes. We could accomplish this in situ oxygen gas cleaning effectively in short time by using hot-wall batch type Ru CVD equipment, which has high heating and cooling rate characteristics.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123227644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962917
D. Collins, V. Lakshman, L. Collins
We present a FAB Simulator (FS) and Capacity Planner (CP) that permits the operational planner to introduce new product into an existing production mix with confidence as to the customer delivery dates and FAB Capacity This paper describes the implementation of these two dynamic tools in a semiconductor FAB in Arizona. These tools assist the operational planner with the planning of the daily production mix. This FAB produces 100's of different bipolar devices using 36 process flows. The key to success in calculating present and future production goals is real time operational level tracking. Real time tracked data includes data gathered from the Manufacturing Execution System (MES) for each product's work-in-process (WIP), process flow routing, and data gathered from the equipment utilization and emergency maintenance databases. This key information is fed through a GUI linked to the CP which in turn controls the stochastic dynamic simulation model of the FS. These links provide the operational planner with dynamic production data in real time and simulated time for decision-making. The CP and FS are running in parallel and are linked directly with the FAB's MES maintaining current production data.
{"title":"Dynamic simulator for WIP analysis in semiconductor manufacturing","authors":"D. Collins, V. Lakshman, L. Collins","doi":"10.1109/ISSM.2001.962917","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962917","url":null,"abstract":"We present a FAB Simulator (FS) and Capacity Planner (CP) that permits the operational planner to introduce new product into an existing production mix with confidence as to the customer delivery dates and FAB Capacity This paper describes the implementation of these two dynamic tools in a semiconductor FAB in Arizona. These tools assist the operational planner with the planning of the daily production mix. This FAB produces 100's of different bipolar devices using 36 process flows. The key to success in calculating present and future production goals is real time operational level tracking. Real time tracked data includes data gathered from the Manufacturing Execution System (MES) for each product's work-in-process (WIP), process flow routing, and data gathered from the equipment utilization and emergency maintenance databases. This key information is fed through a GUI linked to the CP which in turn controls the stochastic dynamic simulation model of the FS. These links provide the operational planner with dynamic production data in real time and simulated time for decision-making. The CP and FS are running in parallel and are linked directly with the FAB's MES maintaining current production data.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129380047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962908
C.-S. Wu, Y. Chou, J.-Z. Lin
The tool portfolio of a plant refers to the makeup, in quantity and type, of processing machines in the plant. Portfolio planning is a multi-criteria decision-making task involving trade-offs between investment cost, throughput, cycle time and risk. In this paper, an economic decision model is first presented for optimal configuration of portfolio and to determine optimal factory loading. If plants are closely located or have a twin-fab design, portfolio planning at multiple plants can be integrated to enhance the overall effectiveness of portfolios. A novel methodology for arbitrating capacity backup between multiple plants is described in the second part. Finally, robust configuration of portfolio in a dynamic demand environment is addressed. Industry data have been utilized to run through the developed methodologies.
{"title":"Optimization and economic analysis for tool portfolio planning in semiconductor manufacturing","authors":"C.-S. Wu, Y. Chou, J.-Z. Lin","doi":"10.1109/ISSM.2001.962908","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962908","url":null,"abstract":"The tool portfolio of a plant refers to the makeup, in quantity and type, of processing machines in the plant. Portfolio planning is a multi-criteria decision-making task involving trade-offs between investment cost, throughput, cycle time and risk. In this paper, an economic decision model is first presented for optimal configuration of portfolio and to determine optimal factory loading. If plants are closely located or have a twin-fab design, portfolio planning at multiple plants can be integrated to enhance the overall effectiveness of portfolios. A novel methodology for arbitrating capacity backup between multiple plants is described in the second part. Finally, robust configuration of portfolio in a dynamic demand environment is addressed. Industry data have been utilized to run through the developed methodologies.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127183779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963002
C. Frum, Z. Sui, Hongching Shan
In this paper, we present an in-situ interferometric technique to control the trench depth for etching various type of patterned dielectric films, including silicon oxide, low-k black diamond, and low k SILK materials. We present the data on etching oxide trench wafers with various pattern density on Si substrate, black diamond film on Si, and SILK on Si, using Applied Materials' MERIE dielectric etch chambers. A good correlation between predicted etch depth using interferometric signals and SEM depth data is presented. In addition, the issues of integrating this sensor into a dielectric etch chamber are addressed.
{"title":"Interferometric techniques for dielectric trench etch applications","authors":"C. Frum, Z. Sui, Hongching Shan","doi":"10.1109/ISSM.2001.963002","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963002","url":null,"abstract":"In this paper, we present an in-situ interferometric technique to control the trench depth for etching various type of patterned dielectric films, including silicon oxide, low-k black diamond, and low k SILK materials. We present the data on etching oxide trench wafers with various pattern density on Si substrate, black diamond film on Si, and SILK on Si, using Applied Materials' MERIE dielectric etch chambers. A good correlation between predicted etch depth using interferometric signals and SEM depth data is presented. In addition, the issues of integrating this sensor into a dielectric etch chamber are addressed.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"2162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127468354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962949
K. Macwilliams, J. Huang, M. Schulberg, P. van Cleemput
A primary challenge in building integrated circuits with geometries of 0.13 /spl mu/m and smaller is the development of materials with low dielectric constants. The properties of the low k films must be compatible with subsequent processing for integration. The present work describes the influence of the starting materials (precursors) and of the deposition process on the electrical and mechanical properties of the low k film.
{"title":"Low k material optimization","authors":"K. Macwilliams, J. Huang, M. Schulberg, P. van Cleemput","doi":"10.1109/ISSM.2001.962949","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962949","url":null,"abstract":"A primary challenge in building integrated circuits with geometries of 0.13 /spl mu/m and smaller is the development of materials with low dielectric constants. The properties of the low k films must be compatible with subsequent processing for integration. The present work describes the influence of the starting materials (precursors) and of the deposition process on the electrical and mechanical properties of the low k film.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128917646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962978
T. Onishi, K. Nagaseki, M. Shimada, H. Miyajima, R. Nakata, M. Yamaguchi, J. Murase, H. Hata
Recently IC makers have requested single wafer processes because the number of wafers in 1 lot is small and the size of the wafers are larger. Usually spin on low-k material is used by the furnace (FNC) for long time thermal cure process. A new electron beam (EB) cure equipment and process are developed to improve the mechanical strength of low-k dielectric, to reduce the time of cure process and to reduce thermal budget. By EB curing, JSR LKD (low k dielectric) material (k = 2.9) becomes 1.6 times stronger than conventional film. EB cure also shows considerable merit over FNC in cure time and power consumption for small batch size processing. For single wafer processing, the cure time is reduced from 30 minutes to 2 minutes. The power consumption is less than half of the FNC case for 25 wafer processing. Electric charge up damage is measured and proved not much of a drawback for devices.
{"title":"Advanced EB-cure process and equipment for low-k dielectric","authors":"T. Onishi, K. Nagaseki, M. Shimada, H. Miyajima, R. Nakata, M. Yamaguchi, J. Murase, H. Hata","doi":"10.1109/ISSM.2001.962978","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962978","url":null,"abstract":"Recently IC makers have requested single wafer processes because the number of wafers in 1 lot is small and the size of the wafers are larger. Usually spin on low-k material is used by the furnace (FNC) for long time thermal cure process. A new electron beam (EB) cure equipment and process are developed to improve the mechanical strength of low-k dielectric, to reduce the time of cure process and to reduce thermal budget. By EB curing, JSR LKD (low k dielectric) material (k = 2.9) becomes 1.6 times stronger than conventional film. EB cure also shows considerable merit over FNC in cure time and power consumption for small batch size processing. For single wafer processing, the cure time is reduced from 30 minutes to 2 minutes. The power consumption is less than half of the FNC case for 25 wafer processing. Electric charge up damage is measured and proved not much of a drawback for devices.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121702592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963023
Y. Kanechika, T. Kawaguchi, M. Nagase, T. Jimbo, M. Yamasaki, M. Hirayama, Y. Shirai, T. Ohmi
Clean room air contains many kinds of contaminants such as moisture and organic compounds. The device performance is influenced by them, therefore, Si wafers should not be exposed to clean room air. We have developed the next generation Si wafer transfer/stock system using out-gas free advanced resin and CDA (Clean Dry Air). The advanced resin has various advantageous properties for a Si wafer transfer box and stocker. For example, (1) out-gas free, (2) light weight, (3) high transparency, (4) high strength, etc. Using the advanced resin, we have developed a new Si wafer transfer pod, called BORP (Bottom Opening Removal Pod).
{"title":"Development of the next generation Si wafer transfer/stock system","authors":"Y. Kanechika, T. Kawaguchi, M. Nagase, T. Jimbo, M. Yamasaki, M. Hirayama, Y. Shirai, T. Ohmi","doi":"10.1109/ISSM.2001.963023","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963023","url":null,"abstract":"Clean room air contains many kinds of contaminants such as moisture and organic compounds. The device performance is influenced by them, therefore, Si wafers should not be exposed to clean room air. We have developed the next generation Si wafer transfer/stock system using out-gas free advanced resin and CDA (Clean Dry Air). The advanced resin has various advantageous properties for a Si wafer transfer box and stocker. For example, (1) out-gas free, (2) light weight, (3) high transparency, (4) high strength, etc. Using the advanced resin, we have developed a new Si wafer transfer pod, called BORP (Bottom Opening Removal Pod).","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127812456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963027
T. Croft, H. Toeante, T. Baker
Knowing the current labor needs of your fab is an awareness; knowing the labor needs of your fab in the future is a science and an art. Keeping accurate and up-to-date labor modeling is vital to the health of a manufacturing organization, especially in a highly cost-competitive environment. AMD's Fab 25 recognizes the need to understand the labor components in our cost structure and the necessity to control this delicate element. Using both an analytical and research approach to a difficult problem, we successfully built a labor model for Fab 25.
{"title":"Labor modeling in a dynamic environment","authors":"T. Croft, H. Toeante, T. Baker","doi":"10.1109/ISSM.2001.963027","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963027","url":null,"abstract":"Knowing the current labor needs of your fab is an awareness; knowing the labor needs of your fab in the future is a science and an art. Keeping accurate and up-to-date labor modeling is vital to the health of a manufacturing organization, especially in a highly cost-competitive environment. AMD's Fab 25 recognizes the need to understand the labor components in our cost structure and the necessity to control this delicate element. Using both an analytical and research approach to a difficult problem, we successfully built a labor model for Fab 25.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127750145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962968
A. Skumanich, E. Ryabova
A methodology is outlined to establish the prioritization of defects under conditions of low sampling statistics based on the deliberate introduction of defects at specific process points. Probe results from electrical test structures are correlated with optical defect inspection data to determine the kill rates of various defects. The methodology generalizes from a standard approach that typically relies on a high statistical sampling plan with significant wafer area coverage. In this case, the probed area coverage is reduced to 1-3% of the wafer surface but still provides defect impact prioritization for targeted defect reduction and optimized inspection strategies.
{"title":"Methodology for yield analysis based on targeted defect impact studies","authors":"A. Skumanich, E. Ryabova","doi":"10.1109/ISSM.2001.962968","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962968","url":null,"abstract":"A methodology is outlined to establish the prioritization of defects under conditions of low sampling statistics based on the deliberate introduction of defects at specific process points. Probe results from electrical test structures are correlated with optical defect inspection data to determine the kill rates of various defects. The methodology generalizes from a standard approach that typically relies on a high statistical sampling plan with significant wafer area coverage. In this case, the probed area coverage is reduced to 1-3% of the wafer surface but still provides defect impact prioritization for targeted defect reduction and optimized inspection strategies.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128390942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962963
A. Strojwas, Zhengrong Zhu, D. Ciplickas, Xiaolei Li
This paper presents the latest development of Metropole-3D, a three-dimensional vector simulator that is designed to rigorously simulate the photolithography process in VLSI manufacturing. The development work includes implementation of an efficient and stable solution of Maxwell's equation, a rigorous model for post-exposure bake (PEB) and a fast marching module which simulates the development of photoresist. The integration of these features into a rigorous overall simulation approach enables Metropole-3D to meet the demands of simulating DUV and even more advanced lithography process. Simulation of Focus-Exposure Matrix (FEM) conditions shows good matching to experiments in both dense and isolated lines. Process variation analysis using Metropole-3D is demonstrated in a study of undercut and other effects as function of defocus, dose, or other parameters. Finally, line end printability analysis is shown, as an example use of Metropole-3D to study manufacturability of advanced optical proximity correction (OPC).
{"title":"Layout manufacturability analysis using rigorous 3-d topography simulation","authors":"A. Strojwas, Zhengrong Zhu, D. Ciplickas, Xiaolei Li","doi":"10.1109/ISSM.2001.962963","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962963","url":null,"abstract":"This paper presents the latest development of Metropole-3D, a three-dimensional vector simulator that is designed to rigorously simulate the photolithography process in VLSI manufacturing. The development work includes implementation of an efficient and stable solution of Maxwell's equation, a rigorous model for post-exposure bake (PEB) and a fast marching module which simulates the development of photoresist. The integration of these features into a rigorous overall simulation approach enables Metropole-3D to meet the demands of simulating DUV and even more advanced lithography process. Simulation of Focus-Exposure Matrix (FEM) conditions shows good matching to experiments in both dense and isolated lines. Process variation analysis using Metropole-3D is demonstrated in a study of undercut and other effects as function of defocus, dose, or other parameters. Finally, line end printability analysis is shown, as an example use of Metropole-3D to study manufacturability of advanced optical proximity correction (OPC).","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132987374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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