Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963011
T. Nakao, S. Katsui, M. Kamimura, A. Yamamoto, Y. Tsunashima, Y. Mikata
To satisfy both the quick turn around time and the process compatibility with the current product line at LPCVD process, the mini-batch furnace is one of the reasonable options. For the high tool utility and the capital scalability at small manufacturing line, the minibatch furnaces are required short time and high frequency tool cleaning for the low machine down time and process commonality for different kind of films LPCVD. In this paper, the short time and high frequency tool cleaning is proposed not only for productivity but also for particle controls.
{"title":"Gas cleaning technique for batch furnace at Agile-fab concept manufacturing","authors":"T. Nakao, S. Katsui, M. Kamimura, A. Yamamoto, Y. Tsunashima, Y. Mikata","doi":"10.1109/ISSM.2001.963011","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963011","url":null,"abstract":"To satisfy both the quick turn around time and the process compatibility with the current product line at LPCVD process, the mini-batch furnace is one of the reasonable options. For the high tool utility and the capital scalability at small manufacturing line, the minibatch furnaces are required short time and high frequency tool cleaning for the low machine down time and process commonality for different kind of films LPCVD. In this paper, the short time and high frequency tool cleaning is proposed not only for productivity but also for particle controls.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123176593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962926
M. Johnston
A novel approach to reconciling global optimizing scheduling with real-time dispatching is presented. High speed scheduling is accomplished by two simultaneous cooperating scheduling processes, one of which generates longer term schedules while the other is focused with higher resolution on the nearer term. Real-time dispatching is based on the most recently generated near term schedule, carefully reconciled with events that could affect its current validity on the shopfloor. Results are presented which show a fivefold performance speedup in schedule generation time, as well as significant schedule quality improvements over pure dispatching approaches.
{"title":"Reconciling high-speed scheduling with dispatching in wafer fabs","authors":"M. Johnston","doi":"10.1109/ISSM.2001.962926","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962926","url":null,"abstract":"A novel approach to reconciling global optimizing scheduling with real-time dispatching is presented. High speed scheduling is accomplished by two simultaneous cooperating scheduling processes, one of which generates longer term schedules while the other is focused with higher resolution on the nearer term. Real-time dispatching is based on the most recently generated near term schedule, carefully reconciled with events that could affect its current validity on the shopfloor. Results are presented which show a fivefold performance speedup in schedule generation time, as well as significant schedule quality improvements over pure dispatching approaches.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133958642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962933
Z. Wu, C. Spanoc
Plasma etching signals arising from three different sources are collected and analyzed, including optical emission spectroscopy (OES), RF power fundamental and harmonic information, and machine signals such as power, chamber pressure, temperature, gas flow rate, etc. CF/sub 2/ OES lines 275 nm and 321 nm are found to be better than any other signals for poly-etch endpoint detection. In addition, excellent statistical models for wafer state prediction are obtained by linear stepwise regression on all available signals. Finally a data exploration system, based on syntactic analysis, is developed for efficiently browsing the data archive, allowing users to examine the data both qualitatively and quantitatively.
{"title":"Towards a complete plasma diagnostic system","authors":"Z. Wu, C. Spanoc","doi":"10.1109/ISSM.2001.962933","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962933","url":null,"abstract":"Plasma etching signals arising from three different sources are collected and analyzed, including optical emission spectroscopy (OES), RF power fundamental and harmonic information, and machine signals such as power, chamber pressure, temperature, gas flow rate, etc. CF/sub 2/ OES lines 275 nm and 321 nm are found to be better than any other signals for poly-etch endpoint detection. In addition, excellent statistical models for wafer state prediction are obtained by linear stepwise regression on all available signals. Finally a data exploration system, based on syntactic analysis, is developed for efficiently browsing the data archive, allowing users to examine the data both qualitatively and quantitatively.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129332237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962911
M. Inaba, T. Aizono, K. Sonobe, H. Fukube, T. Iizumi, J. Arima, Y. Usami
Hitachi's CD-SEM achieves the highest tool availability in the industry. However, efforts to further our performance are continuously underway. The proposed on-line diagnostics system can allow senior technical staff to monitor and investigate tool status by connecting the equipment supplier and the device manufacturer sites through the Internet. The advanced security system ensures confidentiality by firewalls, digital certification, and advanced encryption algorithms to protect device manufacturer data from unauthorized access. Service support software, called DDS (defective part diagnosis support system), will analyze the status of mechanical, evacuation, and optical systems. Its advanced overlay function on a timing chart identifies failed components in the tool and allows on-site or remote personnel to predict potential failures prior to their occurrence. Examples of application shows that the proposed system is expected to reduce repair time, improve availability and lower cost of ownership.
{"title":"The development of security system and visual service support software for on-line diagnostics","authors":"M. Inaba, T. Aizono, K. Sonobe, H. Fukube, T. Iizumi, J. Arima, Y. Usami","doi":"10.1109/ISSM.2001.962911","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962911","url":null,"abstract":"Hitachi's CD-SEM achieves the highest tool availability in the industry. However, efforts to further our performance are continuously underway. The proposed on-line diagnostics system can allow senior technical staff to monitor and investigate tool status by connecting the equipment supplier and the device manufacturer sites through the Internet. The advanced security system ensures confidentiality by firewalls, digital certification, and advanced encryption algorithms to protect device manufacturer data from unauthorized access. Service support software, called DDS (defective part diagnosis support system), will analyze the status of mechanical, evacuation, and optical systems. Its advanced overlay function on a timing chart identifies failed components in the tool and allows on-site or remote personnel to predict potential failures prior to their occurrence. Examples of application shows that the proposed system is expected to reduce repair time, improve availability and lower cost of ownership.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128897506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963025
H. Seita, A. Fujii, T. Suzuki, S. Kimoto, O. Shippou, K. Fujiwara, K. Tokunaga
Evaluates both mechanical and process characteristics of FOUPs (front opening unifed pods) and improves performance through feedback to suppliers. Issues of FOUPs are as follows.: dimensions; FOUP/LP interoperability; particle contamination; organic contamination; and drying defectiveness We have developed 3-dimensional FOUP measuring equipment with Nikon Instech Co. (Nexiv450N) and measured critical dimensions like wafer teeth height, Y52, and latch key hole position. With the Nexiv450N we could take the dimensions of each FOUP to their nominal values. It's important to align the dimension of the FOUP to realize FOUP/load port interoperability.
{"title":"Improvement of 300mm FOUP mini-environment","authors":"H. Seita, A. Fujii, T. Suzuki, S. Kimoto, O. Shippou, K. Fujiwara, K. Tokunaga","doi":"10.1109/ISSM.2001.963025","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963025","url":null,"abstract":"Evaluates both mechanical and process characteristics of FOUPs (front opening unifed pods) and improves performance through feedback to suppliers. Issues of FOUPs are as follows.: dimensions; FOUP/LP interoperability; particle contamination; organic contamination; and drying defectiveness We have developed 3-dimensional FOUP measuring equipment with Nikon Instech Co. (Nexiv450N) and measured critical dimensions like wafer teeth height, Y52, and latch key hole position. With the Nexiv450N we could take the dimensions of each FOUP to their nominal values. It's important to align the dimension of the FOUP to realize FOUP/load port interoperability.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133745837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962999
Sang-mun Chon, S. Choi, Yong-Wan Kim, Kye-Weon Kim, Kyu-hong Lim, Sun-Yong Choi, C. Jun
We have developed an automated contact inspection system using an in-line CD SEM and applied it to monitor contact etching processes. As the design rule shrinks, monitoring of the contact etching, which cannot be detected by the conventional optical inspection systems, are becoming one of the most critical issues in semiconductor processing. Though there are e-beam based inspection systems or manual inspection sequence with in-line SEM (Scanning Electron Microscope), monitoring small and electrical defects has a few fundamental limitations. E-beam inspection systems have low throughput and a high price as a mass production tool. In the case of the manual inspection system, the inspection result depends on the operator and it is difficult to quantify the defect data. We have developed an automated contact inspection system to overcome these limitations. The system is composed of a data processing system and an in-line SEM. The automated in-line SEM inspects and stores the images of specified points on the wafer. The data processing system receives and manipulates the images to indicate the etching problem. It was shown that the scanning electron image of the contact is related to failures such as insufficient etching or residuals inside the contact.
{"title":"Development of automated contact inspection system using in-line CD SEM","authors":"Sang-mun Chon, S. Choi, Yong-Wan Kim, Kye-Weon Kim, Kyu-hong Lim, Sun-Yong Choi, C. Jun","doi":"10.1109/ISSM.2001.962999","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962999","url":null,"abstract":"We have developed an automated contact inspection system using an in-line CD SEM and applied it to monitor contact etching processes. As the design rule shrinks, monitoring of the contact etching, which cannot be detected by the conventional optical inspection systems, are becoming one of the most critical issues in semiconductor processing. Though there are e-beam based inspection systems or manual inspection sequence with in-line SEM (Scanning Electron Microscope), monitoring small and electrical defects has a few fundamental limitations. E-beam inspection systems have low throughput and a high price as a mass production tool. In the case of the manual inspection system, the inspection result depends on the operator and it is difficult to quantify the defect data. We have developed an automated contact inspection system to overcome these limitations. The system is composed of a data processing system and an in-line SEM. The automated in-line SEM inspects and stores the images of specified points on the wafer. The data processing system receives and manipulates the images to indicate the etching problem. It was shown that the scanning electron image of the contact is related to failures such as insufficient etching or residuals inside the contact.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130577142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963010
A. Tanzawa, T. Igarashi, S. Matsuzaki, T. Suzuki, K. Tokushige
Chemical mechanical polishing (CMP) has been available to semiconductor manufacturing but it is still difficult to control the CMP process precisely. This means that it is hard to control CMP according to the process model. Without model based process control, one can't achieve major success. This report describes the development of a data logging network system for CMP process. This system helps engineers building up the proper process control model. This system consists of the following equipment, CMP to which several analog/digital I/O devices were attached, the equipment of film thickness measurement and of scratch measurement, the particle measurement facility, and the infrared thermometer apparatus. All of these compose a local area network.
{"title":"Development of data logging system for chemical mechanical polishing and its application for process control","authors":"A. Tanzawa, T. Igarashi, S. Matsuzaki, T. Suzuki, K. Tokushige","doi":"10.1109/ISSM.2001.963010","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963010","url":null,"abstract":"Chemical mechanical polishing (CMP) has been available to semiconductor manufacturing but it is still difficult to control the CMP process precisely. This means that it is hard to control CMP according to the process model. Without model based process control, one can't achieve major success. This report describes the development of a data logging network system for CMP process. This system helps engineers building up the proper process control model. This system consists of the following equipment, CMP to which several analog/digital I/O devices were attached, the equipment of film thickness measurement and of scratch measurement, the particle measurement facility, and the infrared thermometer apparatus. All of these compose a local area network.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131448618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962916
I. Peterson, M. Stoller, D. Gudmundsson, R. Nurani, S. Ashkenaz, L. Breaux
The latest technology advances and new processes in the lithography area coupled with the increasing market pressures have placed greater demands on defect management. Thinner resists, new resist chemistries and tighter process windows along with shorter product life cycles and the need for faster return on investment create the necessity to focus more attention to defectivity. Fabs must detect, identify and resolve defects in the lithography area before committing product wafers in order to be competitive. At present, the application of available advanced defect management technology in the lithography area has lagged compared to other areas in the semiconductor fab. Optimizing the defect management strategy with the large range of possible defect mechanisms and related yield impact that can occur within the lithography area is a relatively complicated task. With the variety of available defect inspection technologies, the capital and labor support costs associated with defect metrology and the ability to correct problems by rework, there is a need to approach the problem of defect management in, a systematic, manner to measure the cost effectiveness of the defect management strategy. In this paper the Sample Planner cost model was applied to the full range of available defect inspection technologies and sampling strategies based on the commonly known defect mechanisms that occur in the lithography area. From this a recommended optimum sampling and monitoring strategy was obtained.
{"title":"Comprehensive cost-effective photo defect monitoring strategy","authors":"I. Peterson, M. Stoller, D. Gudmundsson, R. Nurani, S. Ashkenaz, L. Breaux","doi":"10.1109/ISSM.2001.962916","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962916","url":null,"abstract":"The latest technology advances and new processes in the lithography area coupled with the increasing market pressures have placed greater demands on defect management. Thinner resists, new resist chemistries and tighter process windows along with shorter product life cycles and the need for faster return on investment create the necessity to focus more attention to defectivity. Fabs must detect, identify and resolve defects in the lithography area before committing product wafers in order to be competitive. At present, the application of available advanced defect management technology in the lithography area has lagged compared to other areas in the semiconductor fab. Optimizing the defect management strategy with the large range of possible defect mechanisms and related yield impact that can occur within the lithography area is a relatively complicated task. With the variety of available defect inspection technologies, the capital and labor support costs associated with defect metrology and the ability to correct problems by rework, there is a need to approach the problem of defect management in, a systematic, manner to measure the cost effectiveness of the defect management strategy. In this paper the Sample Planner cost model was applied to the full range of available defect inspection technologies and sampling strategies based on the commonly known defect mechanisms that occur in the lithography area. From this a recommended optimum sampling and monitoring strategy was obtained.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129761927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962967
S. Doan, Boon Ang
The effective use of SRAM bitmap, end-of-line failure analyses, in-line electron beam defect inspections and focused ion beam (FIB) to identify and resolve an integration-related metal voiding issue is demonstrated in this paper. Because the voiding mechanism was due to a post-metal, multi-layer process interaction, conventional in-line optical defect inspections failed to provide useful information. Electron beam defect inspections and FIB, on the other hand, provided a fast and accurate in-line assessment of the problem, thus enabling a timely resolution of this yield issue.
{"title":"A non-traditional approach to resolving multi-layer process-induced metal voiding","authors":"S. Doan, Boon Ang","doi":"10.1109/ISSM.2001.962967","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962967","url":null,"abstract":"The effective use of SRAM bitmap, end-of-line failure analyses, in-line electron beam defect inspections and focused ion beam (FIB) to identify and resolve an integration-related metal voiding issue is demonstrated in this paper. Because the voiding mechanism was due to a post-metal, multi-layer process interaction, conventional in-line optical defect inspections failed to provide useful information. Electron beam defect inspections and FIB, on the other hand, provided a fast and accurate in-line assessment of the problem, thus enabling a timely resolution of this yield issue.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"208 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132391976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962995
M. Kobayashi, T. Makita, S. Matsui, M. Koyama, N. Fujii, I. Hatono, K. Ueda
Floor layout to realize short accumulated distance of product and high throughput is required. Currently, however, it is very difficult and takes a very long time to optimize floor planning in a wafer process, because of complex process flow. In this paper we propose a new method of floor planning based on self-organization to solve these problems. We verify the validity of applying this method to semiconductor manufacturing. Self-organization method can generate a floor layout plan autonomously. In particular, potential field modeling method can describe simulation models in a simple way, because it controls all entities in the same method. The results of simulation indicate that the proposed method can provide the layout plan with short accumulated distance of product without requiring considerable labor and time.
{"title":"Floor layout planning method based on self-organization","authors":"M. Kobayashi, T. Makita, S. Matsui, M. Koyama, N. Fujii, I. Hatono, K. Ueda","doi":"10.1109/ISSM.2001.962995","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962995","url":null,"abstract":"Floor layout to realize short accumulated distance of product and high throughput is required. Currently, however, it is very difficult and takes a very long time to optimize floor planning in a wafer process, because of complex process flow. In this paper we propose a new method of floor planning based on self-organization to solve these problems. We verify the validity of applying this method to semiconductor manufacturing. Self-organization method can generate a floor layout plan autonomously. In particular, potential field modeling method can describe simulation models in a simple way, because it controls all entities in the same method. The results of simulation indicate that the proposed method can provide the layout plan with short accumulated distance of product without requiring considerable labor and time.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"32 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128596919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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