Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434268
M. M. Tabrizi, N. Masoumi
The class E switched mode power amplifier consists of a load network and a single transistor that is operated as a switch at the carrier frequency of the output signal. Main three parts of the power amplifier that specify its total efficiency are: the Q factor of output band-pass filter, the transistor on-state resistance, and the driver stage. In this paper, we design and optimize three common structures of power amplifiers using a random search algorithm. Optimized designs are simulated with HSPICE in 0.25 /spl mu/m CMOS technology at the carrier frequency of 5.2 GHz. The maximum efficiency for each structure is calculated, and then its bottle-neck is determined. We also achieve the total efficiency of 92.3% for the power amplifier.
E类开关模式功率放大器由负载网络和单个晶体管组成，该晶体管在输出信号的载波频率上作为开关工作。决定功率放大器总效率的主要有三个部分:输出带通滤波器的Q因子、晶体管导通电阻和驱动级。本文采用随机搜索算法对三种常见的功率放大器结构进行了设计和优化。在载波频率为5.2 GHz的0.25 /spl μ m CMOS技术下，利用HSPICE对优化设计进行了仿真。计算每种结构的最大效率，然后确定其瓶颈。我们还实现了功率放大器的总效率为92.3%。
{"title":"High efficiency class-E switched mode power amplifier design and optimization with random search algorithm","authors":"M. M. Tabrizi, N. Masoumi","doi":"10.1109/ICM.2004.1434268","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434268","url":null,"abstract":"The class E switched mode power amplifier consists of a load network and a single transistor that is operated as a switch at the carrier frequency of the output signal. Main three parts of the power amplifier that specify its total efficiency are: the Q factor of output band-pass filter, the transistor on-state resistance, and the driver stage. In this paper, we design and optimize three common structures of power amplifiers using a random search algorithm. Optimized designs are simulated with HSPICE in 0.25 /spl mu/m CMOS technology at the carrier frequency of 5.2 GHz. The maximum efficiency for each structure is calculated, and then its bottle-neck is determined. We also achieve the total efficiency of 92.3% for the power amplifier.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128909655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434236
T. W. Kwan, M. Shams
This paper introduces and compares two topologies for the C-element in MCML and two topologies for double-edge-triggered flip-flop in MCML. Based on the simulation results, an asynchronous MCML C-element dissipates four times less power than conventional static CMOS C-element at the same throughout of 1.9 GHz. Also, MCML double-edge-triggered flip-flop runs up to three times faster than the conventional static CMOS counterpart at the same power level. All the circuits are implemented in a standard 0.18 /spl mu/m CMOS technology.
{"title":"Design of asynchronous circuit primitives using MOS current-mode logic (MCML)","authors":"T. W. Kwan, M. Shams","doi":"10.1109/ICM.2004.1434236","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434236","url":null,"abstract":"This paper introduces and compares two topologies for the C-element in MCML and two topologies for double-edge-triggered flip-flop in MCML. Based on the simulation results, an asynchronous MCML C-element dissipates four times less power than conventional static CMOS C-element at the same throughout of 1.9 GHz. Also, MCML double-edge-triggered flip-flop runs up to three times faster than the conventional static CMOS counterpart at the same power level. All the circuits are implemented in a standard 0.18 /spl mu/m CMOS technology.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"434 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116988633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434216
M. Ghannam, I. Adly, H. Tilmans, W. De Raedt, R. Mertens
In this work a digitally controlled dc-dc voltage converter circuit aimed at providing on-chip high voltage for MEMS switch actuation is developed. The chip including an analog voltage converter and a digital controller is fabricated in a 0.7 /spl mu/m CMOS high voltage/low voltage technology and occupies 11.84 mm/sup 2/ Si area. A maximum voltage of 32 V is attained in the realized prototype but higher levels are possible with modified converter designs. Multilevel driving voltage waveforms are demonstrated with successful configuration of the voltage level and time of selected intervals.
本文设计了一种数字控制的dc-dc电压转换电路，旨在为MEMS开关驱动提供片上高压。该芯片包括模拟电压转换器和数字控制器，采用0.7 /spl μ m CMOS高/低压工艺制作，占地11.84 mm/sup 2/ Si。在实现的原型中获得了32 V的最大电压，但通过修改转换器设计可以达到更高的电压。演示了多电平驱动电压波形，并成功配置了所选间隔的电压电平和时间。
{"title":"CMOS-integrated digitally controlled DC-DC voltage converter with voltage and time configurations for on-chip high voltage MEMS switch actuation","authors":"M. Ghannam, I. Adly, H. Tilmans, W. De Raedt, R. Mertens","doi":"10.1109/ICM.2004.1434216","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434216","url":null,"abstract":"In this work a digitally controlled dc-dc voltage converter circuit aimed at providing on-chip high voltage for MEMS switch actuation is developed. The chip including an analog voltage converter and a digital controller is fabricated in a 0.7 /spl mu/m CMOS high voltage/low voltage technology and occupies 11.84 mm/sup 2/ Si area. A maximum voltage of 32 V is attained in the realized prototype but higher levels are possible with modified converter designs. Multilevel driving voltage waveforms are demonstrated with successful configuration of the voltage level and time of selected intervals.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130922593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434261
N. Ismail, N. Malbert, N. Labat, A. Touboul, J. Muraro
On-state breakdown loci of three technologies (power PHEMT, PHEMT and MESFET) have been measured using gate-current extraction techniques. We present a precise understanding of the correlation between the on-state breakdown voltage (BV on-state) locus and the reverse Igs-Vgs characteristics. From the comparison of Igs-Vgs characteristics, this study has allowed establishing a methodology to compare BV-on state of the devices under test. We have found that for technologies with impact ionization occurring at pinch off, such as the PHEMT technology with a high leakage gate current, the on-state breakdown locus presents a pronounced "exponential" shape. On the contrary, a technology with high impact ionization component in the gate current, such as the PPHEMT technology, presents a shape of the on-state breakdown locus rather "hyperbolic". We assess that technologies with impact ionization occurring at pinch off such as the PHEMT and PPHEMT present a more "hyperbolic" shape of the on-state breakdown locus than technologies with impact ionization occurring in open channel regime such as the MESFET.
{"title":"Methodology to compare on-state breakdown loci of GaAs FET's","authors":"N. Ismail, N. Malbert, N. Labat, A. Touboul, J. Muraro","doi":"10.1109/ICM.2004.1434261","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434261","url":null,"abstract":"On-state breakdown loci of three technologies (power PHEMT, PHEMT and MESFET) have been measured using gate-current extraction techniques. We present a precise understanding of the correlation between the on-state breakdown voltage (BV on-state) locus and the reverse Igs-Vgs characteristics. From the comparison of Igs-Vgs characteristics, this study has allowed establishing a methodology to compare BV-on state of the devices under test. We have found that for technologies with impact ionization occurring at pinch off, such as the PHEMT technology with a high leakage gate current, the on-state breakdown locus presents a pronounced \"exponential\" shape. On the contrary, a technology with high impact ionization component in the gate current, such as the PPHEMT technology, presents a shape of the on-state breakdown locus rather \"hyperbolic\". We assess that technologies with impact ionization occurring at pinch off such as the PHEMT and PPHEMT present a more \"hyperbolic\" shape of the on-state breakdown locus than technologies with impact ionization occurring in open channel regime such as the MESFET.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131088820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434753
O. Malik, V. Grimalsky, J. De la Hidalga-W, W. Calleja-A
A CMOS optical detector with a metal-insulator-silicon (MIS) structure is considered. A two-level voltage bias provides a transient between two quasi-equilibrium inversion modes. The simple readout procedure provides the reading of the integrated information with a significant current gain, which is about 10/sup 4/ for high external loads (>10 K/spl Omega/). In this paper, the case of small loads is considered (/spl sim/100 /spl Omega/). Simulations show that the resistance of the silicon base changes drastically due to a double injection of carriers in the base. The current gain obtained experimentally reaches the value of 10/sup 6/ at low loads. Dependencies of integration and readout currents on time allow also a determination of the generation and recombination lifetimes of minority carriers.
{"title":"Signal gain optimization in metal-insulator-silicon optical detector","authors":"O. Malik, V. Grimalsky, J. De la Hidalga-W, W. Calleja-A","doi":"10.1109/ICM.2004.1434753","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434753","url":null,"abstract":"A CMOS optical detector with a metal-insulator-silicon (MIS) structure is considered. A two-level voltage bias provides a transient between two quasi-equilibrium inversion modes. The simple readout procedure provides the reading of the integrated information with a significant current gain, which is about 10/sup 4/ for high external loads (>10 K/spl Omega/). In this paper, the case of small loads is considered (/spl sim/100 /spl Omega/). Simulations show that the resistance of the silicon base changes drastically due to a double injection of carriers in the base. The current gain obtained experimentally reaches the value of 10/sup 6/ at low loads. Dependencies of integration and readout currents on time allow also a determination of the generation and recombination lifetimes of minority carriers.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"96 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131219822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434585
T. Hollstein, H. Zimmer, M. Glesner
In this paper, we present a new paradigm and methodology for the network-on-chip (NoC) based design of complex hardware/software systems. While classical industrial design platforms represent dedicated fixed architectures for specific applications, flexible NoC architectures open new degrees of system reconfigurability. After giving an overview on required demands for NoC hyper-platforms, we describe the realisation of these prerequisites within the HiNoC platform. We introduce a new dynamic hardware/software co-design methodology for pre- and post-manufacturing design. Finally, we summarize the concept combined with an outlook on further investigations.
{"title":"Dynamic hardware/software co-design based on a communication-centric hyper-platform","authors":"T. Hollstein, H. Zimmer, M. Glesner","doi":"10.1109/ICM.2004.1434585","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434585","url":null,"abstract":"In this paper, we present a new paradigm and methodology for the network-on-chip (NoC) based design of complex hardware/software systems. While classical industrial design platforms represent dedicated fixed architectures for specific applications, flexible NoC architectures open new degrees of system reconfigurability. After giving an overview on required demands for NoC hyper-platforms, we describe the realisation of these prerequisites within the HiNoC platform. We introduce a new dynamic hardware/software co-design methodology for pre- and post-manufacturing design. Finally, we summarize the concept combined with an outlook on further investigations.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131121388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434196
N. M. Madani, B. Tavassoli, A. Behnam, A. Afzali-Kusha
Super cut-off method as a well-known technique to reduce leakage power is investigated for its operational characteristics in the sub 100 nm technology nodes. Specially, the effect of the gate leakage in power consumption is considered and a design routine for optimizing the circuit in this regard is proposed. A right design methodology can improve the power and the circuit performance efficiently.
{"title":"Study of super cut-off CMOS technique in presence of the gate leakage current","authors":"N. M. Madani, B. Tavassoli, A. Behnam, A. Afzali-Kusha","doi":"10.1109/ICM.2004.1434196","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434196","url":null,"abstract":"Super cut-off method as a well-known technique to reduce leakage power is investigated for its operational characteristics in the sub 100 nm technology nodes. Specially, the effect of the gate leakage in power consumption is considered and a design routine for optimizing the circuit in this regard is proposed. A right design methodology can improve the power and the circuit performance efficiently.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121553974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434755
N. Sghaier, N. Yacoubi, J. Bluet, A. Souifi, G. Guillot, C. Gaquière, J. De Jaeger
In this paper, we present static measurements and defect analysis performed on AlGaN/GaN/Si or Al/sub 2/O/sub 3/ HEMTs. I/sub d/-V/sub ds/-T, I/sub d/-V/sub gs/-T and I/sub g/-V/sub gs/-T characteristics show anomalies (leakage current, degradation in saturation current, Kink effect, distortions on I/sub d/-V/sub d/ characteristics in saturation region,... etc). These anomalies on output characteristics changes when we vary measurement conditions (temperature, polarisation, stress...). Deep defects analysis performed by capacitance transient spectroscopy (C-DLTS), frequency dispersion of the output conductance (G/sub ds/(f)) and random telegraph signal (RTS) prove the presence of deep defects with activations energies ranging from 0.05 eV to 1.8 eV. The presence of G-R centers acting like traps at the interface GaN/AlGaN is confirmed by I/sub g/-V/sub gs/ and RTS measurements. The localization and the identification of these defects are presented. Finally, the correlation between the anomalies observed on output characteristics and defects is discussed and a little comparison between Al/sub 2/O/sub 3/ and Si HEMTs is presented.
{"title":"Current instabilities and deep level investigation on AlGaN/GaN HEMT's on silicon and sapphire substrates","authors":"N. Sghaier, N. Yacoubi, J. Bluet, A. Souifi, G. Guillot, C. Gaquière, J. De Jaeger","doi":"10.1109/ICM.2004.1434755","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434755","url":null,"abstract":"In this paper, we present static measurements and defect analysis performed on AlGaN/GaN/Si or Al/sub 2/O/sub 3/ HEMTs. I/sub d/-V/sub ds/-T, I/sub d/-V/sub gs/-T and I/sub g/-V/sub gs/-T characteristics show anomalies (leakage current, degradation in saturation current, Kink effect, distortions on I/sub d/-V/sub d/ characteristics in saturation region,... etc). These anomalies on output characteristics changes when we vary measurement conditions (temperature, polarisation, stress...). Deep defects analysis performed by capacitance transient spectroscopy (C-DLTS), frequency dispersion of the output conductance (G/sub ds/(f)) and random telegraph signal (RTS) prove the presence of deep defects with activations energies ranging from 0.05 eV to 1.8 eV. The presence of G-R centers acting like traps at the interface GaN/AlGaN is confirmed by I/sub g/-V/sub gs/ and RTS measurements. The localization and the identification of these defects are presented. Finally, the correlation between the anomalies observed on output characteristics and defects is discussed and a little comparison between Al/sub 2/O/sub 3/ and Si HEMTs is presented.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126258639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434249
N. M. Madani, N. Masoumi
Dynamic power management (DPM) is a technique to reduce power consumption of electronic systems by selectively shutting down idle components. DPM encompasses a set of techniques that achieves energy-efficient computation by selectively turning off system components when they are idle. In this paper, we survey several approaches to system-level dynamic power management and advantages and disadvantages of them. We used continuous-time Markov decision process to manage our systems and show how to modify buffer size of the system queue (SQ) and a technique by changing system provider (SP) parameters to reduce power consumption of the system.
{"title":"A new optimization method for CTMDP system-level power management techniques","authors":"N. M. Madani, N. Masoumi","doi":"10.1109/ICM.2004.1434249","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434249","url":null,"abstract":"Dynamic power management (DPM) is a technique to reduce power consumption of electronic systems by selectively shutting down idle components. DPM encompasses a set of techniques that achieves energy-efficient computation by selectively turning off system components when they are idle. In this paper, we survey several approaches to system-level dynamic power management and advantages and disadvantages of them. We used continuous-time Markov decision process to manage our systems and show how to modify buffer size of the system queue (SQ) and a technique by changing system provider (SP) parameters to reduce power consumption of the system.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114487822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-06DOI: 10.1109/ICM.2004.1434768
A. Ben Atitallah, P. Kadionik, F. Ghozzi, P. Nouel, N. Masmoudi, P. Marchegay
In this paper, we present the installation of a hardware platform for video acquisition and restitution in real-time using a mixed software/hardware environment. The hardware platform is based on the Altera STRATIX development board. Besides, it is completed with a camera interface for acquisition and a VGA interface for restitution. The core of the system incorporates an IP module (intellectual property) of Altera Nios processor in the Quartus II development tool of Altera. During this study, we have used video sequences, which are acquired, processed and visualized while respecting temporal constraints.
{"title":"Hardware platform design for real-time video applications","authors":"A. Ben Atitallah, P. Kadionik, F. Ghozzi, P. Nouel, N. Masmoudi, P. Marchegay","doi":"10.1109/ICM.2004.1434768","DOIUrl":"https://doi.org/10.1109/ICM.2004.1434768","url":null,"abstract":"In this paper, we present the installation of a hardware platform for video acquisition and restitution in real-time using a mixed software/hardware environment. The hardware platform is based on the Altera STRATIX development board. Besides, it is completed with a camera interface for acquisition and a VGA interface for restitution. The core of the system incorporates an IP module (intellectual property) of Altera Nios processor in the Quartus II development tool of Altera. During this study, we have used video sequences, which are acquired, processed and visualized while respecting temporal constraints.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115994813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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