Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654375
R. Metasch, M. Roellig, U. Naumann, Felix Wiesenhütter, R. Kaufmann
The development team has set itself the task of creating a new type of testing system for faster and more cost-effective reliability and service life evaluation. This system additionally measure in-situ the mechanical deformation and shear forces in the electronic joints during the action of temperature change loads. The system approach begins with a new type of temperature unit, which allows very fast and homogeneous heating of the test specimen and measuring chamber. The selection of suitable sensors for high-resolution, long-term stable measurement under the influence of temperature changes is a further sub-area of system development. The developments are accompanied by virtual system design and numerical calculations. First development results for the evaluation of concrete implementation concepts are presented. The focus will be on concepts for load introduction via a frame construction, through heating, force/displacement sensors and material selection based on thermal-mechanical measurements.
{"title":"Novel Concept of an In-situ Test System for the Thermal-Mechanical Fatigue Measurement for Reliability Evaluation of Electronic Solder Joints","authors":"R. Metasch, M. Roellig, U. Naumann, Felix Wiesenhütter, R. Kaufmann","doi":"10.1109/EPTC.2018.8654375","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654375","url":null,"abstract":"The development team has set itself the task of creating a new type of testing system for faster and more cost-effective reliability and service life evaluation. This system additionally measure in-situ the mechanical deformation and shear forces in the electronic joints during the action of temperature change loads. The system approach begins with a new type of temperature unit, which allows very fast and homogeneous heating of the test specimen and measuring chamber. The selection of suitable sensors for high-resolution, long-term stable measurement under the influence of temperature changes is a further sub-area of system development. The developments are accompanied by virtual system design and numerical calculations. First development results for the evaluation of concrete implementation concepts are presented. The focus will be on concepts for load introduction via a frame construction, through heating, force/displacement sensors and material selection based on thermal-mechanical measurements.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132909292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654441
S. Jeong, Seung-Boo Jung, Jeong-Won Yoon
Recently, research and development of power electronics, such as inverter systems and power modules, in electric vehicles (EV) and hybrid electric vehicles (HEV) are increasing. In the power electronic systems, the chip junction temperature is extremely high during operation. Therefore, the new bonding materials and methods are needed for operation at high temperatures for power electronic packaging. Some good candidates for high temperature die-attach applications include high-temperature solders such as Au-Sn, Ag sinter pastes, and transient liquid phase (TLP) bonding materials. Among them, a TLP bonding technology utilizes cheap metals such as Cu, Ni, and Sn. This process is also similar to the conventional soldering process and is reliable when subjected to high temperatures over long durations. TLP bonding is a die-attach technology wherein an intermetallic compound (IMC) is formed via a diffusion reaction by incorporating a low melting point metal between metals with high melting points. This paper presents the growth rate of forming Cu-Sn IMCs in the composite preform that is used as a die-attach material for a TLP bonding. To overcome the drawbacks of the TLP bonding such as a long bonding time, the composite preform was fabricated, and the feasibility for high-temperature power electronics applications was evaluated in this study. The composite preform is composed of a Cu core layer with a high-melting temperature and a low-melting temperature Sn coating at both sides of the Cu core layer. During aging treatment, the Cu-Sn IMC layer was rapidly formed by consuming the both low-melting point Sn layers. The IMC formation by the reaction between Cu and Sn is very important because it affects the thermal, electrical and mechanical reliability for electronic packaging technologies. After isothermal aging treatments at $150^{circ}mathrm{C}$ for various times, the thicknesses of Sn, Cu, and Cu-Sn IMC layers in the composite preform were investigated using field-emission scanning electron microscope (FE-SEM, INSPECT F, FEI, USA) equipped with an energy dispersive X-ray spectroscope (EDX) and focused ion beam (FIB, NOVA-600, FEI, USA).
{"title":"A Study of the Growth Rate of Cu-Sn Intermetallic Compounds for Transient Liquid Phase Bonding during Isothermal Aging","authors":"S. Jeong, Seung-Boo Jung, Jeong-Won Yoon","doi":"10.1109/EPTC.2018.8654441","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654441","url":null,"abstract":"Recently, research and development of power electronics, such as inverter systems and power modules, in electric vehicles (EV) and hybrid electric vehicles (HEV) are increasing. In the power electronic systems, the chip junction temperature is extremely high during operation. Therefore, the new bonding materials and methods are needed for operation at high temperatures for power electronic packaging. Some good candidates for high temperature die-attach applications include high-temperature solders such as Au-Sn, Ag sinter pastes, and transient liquid phase (TLP) bonding materials. Among them, a TLP bonding technology utilizes cheap metals such as Cu, Ni, and Sn. This process is also similar to the conventional soldering process and is reliable when subjected to high temperatures over long durations. TLP bonding is a die-attach technology wherein an intermetallic compound (IMC) is formed via a diffusion reaction by incorporating a low melting point metal between metals with high melting points. This paper presents the growth rate of forming Cu-Sn IMCs in the composite preform that is used as a die-attach material for a TLP bonding. To overcome the drawbacks of the TLP bonding such as a long bonding time, the composite preform was fabricated, and the feasibility for high-temperature power electronics applications was evaluated in this study. The composite preform is composed of a Cu core layer with a high-melting temperature and a low-melting temperature Sn coating at both sides of the Cu core layer. During aging treatment, the Cu-Sn IMC layer was rapidly formed by consuming the both low-melting point Sn layers. The IMC formation by the reaction between Cu and Sn is very important because it affects the thermal, electrical and mechanical reliability for electronic packaging technologies. After isothermal aging treatments at $150^{circ}mathrm{C}$ for various times, the thicknesses of Sn, Cu, and Cu-Sn IMC layers in the composite preform were investigated using field-emission scanning electron microscope (FE-SEM, INSPECT F, FEI, USA) equipped with an energy dispersive X-ray spectroscope (EDX) and focused ion beam (FIB, NOVA-600, FEI, USA).","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128891538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654320
P. Liu, H. Feng, K. Ranjith, T. Wong, K. Toh
Condensation of FC72 in the presence of air has been numerically investigated. The influence of concentration of inlet non-condensable gas on the condensation heat transfer has been examined. It is found that when air is introduced at the inlet, condensation heat transfer deteriorates, more so in the case of condensation under natural convection. The diffusion layer, in which the gradient of non-condensable gas concentration is very high, can clearly ne observed adjacent to the interface. The formation of the diffusion layer provides a driving force for the vapor to reach the interface for continuous condensation. However, it is the presence of this layer that causes a very low vapor partial pressure near the interface, which dramatically decreases the condensation temperature at the interface. This will cause a much smaller temperature difference across the condensate film, which will eventually result in a poorer condensation rate compared with the pure vapor case. It is concluded that effective disturbance or even breakdown of this diffusion layer is the key to enhance condensation heat transfer if the presence of air in the system is inevitable.
{"title":"Numerical Investigation on the Condensation Heat Transfer of FC72 in the Presence of Air","authors":"P. Liu, H. Feng, K. Ranjith, T. Wong, K. Toh","doi":"10.1109/EPTC.2018.8654320","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654320","url":null,"abstract":"Condensation of FC72 in the presence of air has been numerically investigated. The influence of concentration of inlet non-condensable gas on the condensation heat transfer has been examined. It is found that when air is introduced at the inlet, condensation heat transfer deteriorates, more so in the case of condensation under natural convection. The diffusion layer, in which the gradient of non-condensable gas concentration is very high, can clearly ne observed adjacent to the interface. The formation of the diffusion layer provides a driving force for the vapor to reach the interface for continuous condensation. However, it is the presence of this layer that causes a very low vapor partial pressure near the interface, which dramatically decreases the condensation temperature at the interface. This will cause a much smaller temperature difference across the condensate film, which will eventually result in a poorer condensation rate compared with the pure vapor case. It is concluded that effective disturbance or even breakdown of this diffusion layer is the key to enhance condensation heat transfer if the presence of air in the system is inevitable.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124434682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654386
Ruiqi Lim, Weiguo Chen, D. Choong, M. R. Damalerio, Ming-Yuan Cheng
Renal denervation procedure had been emerging as a potential treatment for resistant hypertension condition. It is a minimally invasive procedure where radiofrequency (RF) energy is supplied to ablate and deactivate the renal artery nerve. The deactivation of the renal nerve helps to reduce and control the patient’s blood pressure level. In order to achieve multiple ablation sites per ablation cycle, multiple discrete RF electrodes and temperature sensors components are required for integration with ablation catheter. This is a tedious and time consuming process. To address this issue, this paper proposed a three dimensional roll-up polymer-silicon structure with an overall thickness of 110um for easy of assembly. This roll-up structure with a ‘belt’ slot feature will be used for assembling of MEMS based sensor chip into a single component. Bench-top mechanical testing to simulate the activation and de-activation of the catheter had been performed. The roll-up structure was able to achieve a smooth activation of 5° to 62° with a maximum length of 8mm (diameter) for 10 repeated cycles.
{"title":"Development of Three Dimensional Roll-up Polymer-Si Structure for Nerve Ablation Catheter","authors":"Ruiqi Lim, Weiguo Chen, D. Choong, M. R. Damalerio, Ming-Yuan Cheng","doi":"10.1109/EPTC.2018.8654386","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654386","url":null,"abstract":"Renal denervation procedure had been emerging as a potential treatment for resistant hypertension condition. It is a minimally invasive procedure where radiofrequency (RF) energy is supplied to ablate and deactivate the renal artery nerve. The deactivation of the renal nerve helps to reduce and control the patient’s blood pressure level. In order to achieve multiple ablation sites per ablation cycle, multiple discrete RF electrodes and temperature sensors components are required for integration with ablation catheter. This is a tedious and time consuming process. To address this issue, this paper proposed a three dimensional roll-up polymer-silicon structure with an overall thickness of 110um for easy of assembly. This roll-up structure with a ‘belt’ slot feature will be used for assembling of MEMS based sensor chip into a single component. Bench-top mechanical testing to simulate the activation and de-activation of the catheter had been performed. The roll-up structure was able to achieve a smooth activation of 5° to 62° with a maximum length of 8mm (diameter) for 10 repeated cycles.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115041526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654336
Yixin Xu, F. Zhu, Miaocao Wang, Xiaojiang Liu, Sheng Liu
The molecular dynamics model of wurtzite crystal structure GaN in nano-grinding was established using the Tersoff multi-body potential. The complete structure defect-free GaN model and the defect-containing GaN model were set for comparison. The MD model used hemispherical diamond abrasive grains as the grinding tool, and the micro-regular ensemble (NVE) was used in the grinding process. Additionally, the GaN grinding simulation results under different loading conditions (changing grinding speed, depth) were analyzed to study the changes of internal crystal structure and the evolution of crystal defects. The results show that there is a transition from wurtzite to zinc-blende in GaN during the grinding. Moreover, defects and grinding force increase as the depth of grinding increases. The grinding speed has no obvious influence on the grinding force. When the grinding distance reaches 15 nm, the grinding force decreases slightly with the increase of the speed.
{"title":"Molecular Dynamics Simulation of GaN Nano-grinding","authors":"Yixin Xu, F. Zhu, Miaocao Wang, Xiaojiang Liu, Sheng Liu","doi":"10.1109/EPTC.2018.8654336","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654336","url":null,"abstract":"The molecular dynamics model of wurtzite crystal structure GaN in nano-grinding was established using the Tersoff multi-body potential. The complete structure defect-free GaN model and the defect-containing GaN model were set for comparison. The MD model used hemispherical diamond abrasive grains as the grinding tool, and the micro-regular ensemble (NVE) was used in the grinding process. Additionally, the GaN grinding simulation results under different loading conditions (changing grinding speed, depth) were analyzed to study the changes of internal crystal structure and the evolution of crystal defects. The results show that there is a transition from wurtzite to zinc-blende in GaN during the grinding. Moreover, defects and grinding force increase as the depth of grinding increases. The grinding speed has no obvious influence on the grinding force. When the grinding distance reaches 15 nm, the grinding force decreases slightly with the increase of the speed.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115079620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654330
Mike Tsai, Ryan Chiu, Eric He, J. Chen, R. Chen, Jensen Tsai, Yu-Po Wang
In the near future, the next potential fast and large growing opportunity market will be the Internet of Things (IoT) and fifth generation (5G) connectivity application, due to the electronics industry is moved maturely on the mobile computing market for now. To meet the new application requirements & challenges, high-gain antennas have been proposed for wireless connectivity applications such as IoT and 5G product for high data transmission and low power consumption requirements. Differemt frequency transmission required to integrate an antenna in SiP module so that product designer can develop the products as compact as possible for specific application. This advanced technology will provide the integration solution for small form factor, high electrical performance, multi-function and low cost were the most popular requirements, the System in Package (SiP) is a combination of heterogeneous idea with semiconductor devices and passive components within one small package as system function module.In this paper, SPIL provided an alternative 3D small form factor SiP methodology will use surface mount technology (SMT) and 3D structure of stacking die on passives with antenna integration were designed to shrink the package size, the calculation of package size can be shrunk around 25% area and package size reduced from 16 x 12mm to 12 ×12mm. This new solution could be integrated an antenna inside SiP module as antenna in package (AiP) technology to get small form factor and additional major benefites to address cost, performance, and time-to-market.The characterization analysis will utilize typical reliability testing (Temperature Cycle Test, High Temperature Storage Test, unbias HAST) results as a verification for stacking die on passives integrated 3D antenna of SiP feasibility structure. Finally, this paper will find out the suitable 3D stacking die on passives of SiP structure and antenna integration solution for future IoT and 5G Connectivity devices application.
{"title":"Innovative Packaging Solutions of 3D System in Package with Antenna Integration for IoT and 5G Application","authors":"Mike Tsai, Ryan Chiu, Eric He, J. Chen, R. Chen, Jensen Tsai, Yu-Po Wang","doi":"10.1109/EPTC.2018.8654330","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654330","url":null,"abstract":"In the near future, the next potential fast and large growing opportunity market will be the Internet of Things (IoT) and fifth generation (5G) connectivity application, due to the electronics industry is moved maturely on the mobile computing market for now. To meet the new application requirements & challenges, high-gain antennas have been proposed for wireless connectivity applications such as IoT and 5G product for high data transmission and low power consumption requirements. Differemt frequency transmission required to integrate an antenna in SiP module so that product designer can develop the products as compact as possible for specific application. This advanced technology will provide the integration solution for small form factor, high electrical performance, multi-function and low cost were the most popular requirements, the System in Package (SiP) is a combination of heterogeneous idea with semiconductor devices and passive components within one small package as system function module.In this paper, SPIL provided an alternative 3D small form factor SiP methodology will use surface mount technology (SMT) and 3D structure of stacking die on passives with antenna integration were designed to shrink the package size, the calculation of package size can be shrunk around 25% area and package size reduced from 16 x 12mm to 12 ×12mm. This new solution could be integrated an antenna inside SiP module as antenna in package (AiP) technology to get small form factor and additional major benefites to address cost, performance, and time-to-market.The characterization analysis will utilize typical reliability testing (Temperature Cycle Test, High Temperature Storage Test, unbias HAST) results as a verification for stacking die on passives integrated 3D antenna of SiP feasibility structure. Finally, this paper will find out the suitable 3D stacking die on passives of SiP structure and antenna integration solution for future IoT and 5G Connectivity devices application.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123403771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/eptc.2018.8654266
J. Daviot
The acceleration of advanced development globally to meet current and future system requirements has placed considerable stress on manufacturing methods in the semiconductor industry. For BEOL and FBEOL residue removal, photoresist stripping, and metal etching, new classes of specialty chemical processes are required to address these considerable challengesAdvances have been made in specific areas of compatibility, selectivity, safety, full dissolution of photoresists (P/N), and reductions in overall CoO to enable this wave of next generation integration. This presentation will discuss new technology in highly selective wet metal etchants, full dissolution PR stripping of thick resists, and advanced surface cleaning for high k
{"title":"Resolving Stripping, Etching, and Cleaning Challenges for Shrinking Dimensions from BEOL to Advanced Packaging","authors":"J. Daviot","doi":"10.1109/eptc.2018.8654266","DOIUrl":"https://doi.org/10.1109/eptc.2018.8654266","url":null,"abstract":"The acceleration of advanced development globally to meet current and future system requirements has placed considerable stress on manufacturing methods in the semiconductor industry. For BEOL and FBEOL residue removal, photoresist stripping, and metal etching, new classes of specialty chemical processes are required to address these considerable challengesAdvances have been made in specific areas of compatibility, selectivity, safety, full dissolution of photoresists (P/N), and reductions in overall CoO to enable this wave of next generation integration. This presentation will discuss new technology in highly selective wet metal etchants, full dissolution PR stripping of thick resists, and advanced surface cleaning for high k","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129551412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654342
Chien-Yu Lien, Yao-Chen Chuang, Yuan Yao, Edward Charn, Eric Chen
As the electronic devices getting lighter and smaller, a coreless substrate technology, called Embedded Trace Substrate (ETS) is developed to meet the market requirement. However, this design causes severe warpage due to the large difference in CTE (coefficient of thermal expansion) of buildup material and Cu plate. Recently, finite element analysis (FEA) is a popular and effective method used for substrate warpage prediction and mechanical studies. Manufacturers apply FEA simulation for substrate design improvements and provide substrate warpage that satisfying the customer’s specification. Nevertheless, the computational resources needed for high-fidelity simulation are extremely expensive and time-consuming. Hence the simulation study becomes a long and arduous task if it has to be performed many times, e.g., sensitivity analysis and warpage optimization.In this paper, we propose a new method for FEA modeling of mechanical behaviors of the substrate and present an optimization strategy for substrate warpage control. In the first step, the Gerber files of each layer of the substrate are converted into high-resolution bitmap images, and the copper area of each image is divided and scanned by a pre-sized block window. After that, the effective material properties for each block are calculated with a volume average micromechanics approach, and then all blocks are stacked-up to build a block-based analysis model for FEA simulation. As compared with conventional trace mapping simulation, the proposed method significantly decreases the demands of the computing resource. Besides, we gained accurate warpage prediction results as validated by a real substrate experiment. Finally, we presented an optimization strategy that manipulates the thickness of each layer for substrate warpage optimization in pre-processing steps of packaging. In conclusion, the results show that the methodology for substrate simulation in this paper is practical, effective, and costless.
{"title":"Block-Based Finite Element Modeling, Simulation, and Optimization of the Warpage of Embedded Trace Substrate","authors":"Chien-Yu Lien, Yao-Chen Chuang, Yuan Yao, Edward Charn, Eric Chen","doi":"10.1109/EPTC.2018.8654342","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654342","url":null,"abstract":"As the electronic devices getting lighter and smaller, a coreless substrate technology, called Embedded Trace Substrate (ETS) is developed to meet the market requirement. However, this design causes severe warpage due to the large difference in CTE (coefficient of thermal expansion) of buildup material and Cu plate. Recently, finite element analysis (FEA) is a popular and effective method used for substrate warpage prediction and mechanical studies. Manufacturers apply FEA simulation for substrate design improvements and provide substrate warpage that satisfying the customer’s specification. Nevertheless, the computational resources needed for high-fidelity simulation are extremely expensive and time-consuming. Hence the simulation study becomes a long and arduous task if it has to be performed many times, e.g., sensitivity analysis and warpage optimization.In this paper, we propose a new method for FEA modeling of mechanical behaviors of the substrate and present an optimization strategy for substrate warpage control. In the first step, the Gerber files of each layer of the substrate are converted into high-resolution bitmap images, and the copper area of each image is divided and scanned by a pre-sized block window. After that, the effective material properties for each block are calculated with a volume average micromechanics approach, and then all blocks are stacked-up to build a block-based analysis model for FEA simulation. As compared with conventional trace mapping simulation, the proposed method significantly decreases the demands of the computing resource. Besides, we gained accurate warpage prediction results as validated by a real substrate experiment. Finally, we presented an optimization strategy that manipulates the thickness of each layer for substrate warpage optimization in pre-processing steps of packaging. In conclusion, the results show that the methodology for substrate simulation in this paper is practical, effective, and costless.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132396132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654444
A. Ferro, M. Özkök, H. Huebner, T. Fujiwara
The Semi Additive Process (SAP) has gained more attraction over the past years because it enables very fine lines and spaces for the production of IC-Substrates. When operating with lines and spaces (L/S) of $10/10 mu mathrm {m}$ and less the copper thickness variation is one of the critical parameters which has to be controlled within a tight range in order to avoid reliability problems in assembly or during the lifetime as described in several papers [1], [2]. The key process parameter here is called the copper thickness within-unit distribution (WUD) or copper thickness within-panel-distribution (WPD). Another important parameter is the current density used for the copper plating process. Higher current density operating range of an electrolyte results in in better productivity. But both parameters are usually influencing each other. The existing POR might operate at a current density at 1.5 A/dm2 but increasing the current density in order to improve the productivity means the copper thickness variation within the panel will increase. This is not beneficial for the quality of the product, as the market is looking for a tight control of the copper thickness variation on a IC substrate.Already in 2013 a SAP Electrolyte was introduced to the market which is established meanwhile as a POR at IC-substrate manufacturers. Now in 2017 an upgraded electrolyte was developed in order to overcome this conflict of productivity and copper thickness variation. The novel SAP Copper electrolyte was optimized in its formulation so that higher current densities may be applied while still keeping very good copper thickness within unit distribution (WUD) results. Continuity of innovation and invention as expected by Moore’s Law are needed to reduce cost and increase capability. Challenges like within-unit distribution become a critical factor for the subsequent processing steps.The technical paper will contain results of copper thickness and the copper thickness variation (WUD), microsection pictures, DOE Results, dimple results, filling performance and further data. The novel electrolyte shows capabilities to operate at > 3A/dm2 which brings almost an improvement of the productivity by a factor of 2! The new electrolyte also brings further improvement regarding the Cu thickness variation as tighter tolerances may be realized. This is important for the later process steps during package manufacturing. Other Parameters of the new electrolyte will be shown as well like ductility and copper crystal structures of the new electrolyte.
半增材工艺(SAP)在过去几年中获得了更多的吸引力，因为它可以为ic基板的生产提供非常精细的线条和空间。当线和间距(L/S)为$10/10 mu mathm {m}$及以下时，铜的厚度变化是必须控制在严格范围内的关键参数之一，以避免在组装或使用寿命期间出现可靠性问题，如几篇论文[1]，[2]所述。这里的关键工艺参数称为单元内铜厚度分布(WUD)或板内铜厚度分布(WPD)。另一个重要的参数是镀铜过程中使用的电流密度。电解液的电流密度越高，生产效率越高。但这两个参数通常是相互影响的。现有的POR可以在1.5 a /dm2的电流密度下工作，但是为了提高生产率而增加电流密度意味着面板内的铜厚度变化将会增加。这不利于产品质量，因为市场正在寻找对IC基板上铜厚度变化的严格控制。早在2013年，SAP电解液就被引入市场，同时在ic衬底制造商中建立了POR。现在在2017年，一种升级的电解质被开发出来，以克服生产率和铜厚度变化的冲突。该新型SAP铜电解液在配方上进行了优化，可以在施加更高的电流密度的同时，在单位分布(WUD)结果内仍然保持非常好的铜厚度。正如摩尔定律所期望的那样，创新和发明的连续性需要降低成本和提高能力。单元内分布等挑战成为后续处理步骤的关键因素。技术论文将包含铜厚度和铜厚度变化(WUD)的结果、显微切片图片、DOE结果、韧窝结果、填充性能和其他数据。新型电解质显示出在> 3A/dm2下工作的能力，这几乎使生产率提高了2倍!新的电解液也带来了进一步的改善关于铜的厚度变化，更严格的公差可以实现。这对于包装制造过程中的后期工艺步骤非常重要。新电解质的其他参数，如延展性和铜晶体结构也将被显示出来。
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Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654448
J. Tao, C. Choong, Tao Sun, H. Cai, Navab Singh, Y. Gu
Hybrid laser integration with optical MEMS chips and silicon photonic (SiP) circuits are important for many miniature devices, such as micro-sensor, optical transmitter module. Here, we demonstrated a flexible approach for hybrid integrating laser chip onto silicon device by use of flip-chip bonding method to build a MEMS tunable laser and a miniature silicon optical bench (SiOB) for SiP devices. The maximum coupling efficiency is up to 76.5% and 81.5% for these two devices, respectively. It provides a low cost, miniature, and reliable solution for large-scale deployments Place abstract here: usually a single paragraph summarizing the problem, approach, and results that are in the paper.
{"title":"A Hybrid Laser Integration Approach for Miniature Photonic Sensors","authors":"J. Tao, C. Choong, Tao Sun, H. Cai, Navab Singh, Y. Gu","doi":"10.1109/EPTC.2018.8654448","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654448","url":null,"abstract":"Hybrid laser integration with optical MEMS chips and silicon photonic (SiP) circuits are important for many miniature devices, such as micro-sensor, optical transmitter module. Here, we demonstrated a flexible approach for hybrid integrating laser chip onto silicon device by use of flip-chip bonding method to build a MEMS tunable laser and a miniature silicon optical bench (SiOB) for SiP devices. The maximum coupling efficiency is up to 76.5% and 81.5% for these two devices, respectively. It provides a low cost, miniature, and reliable solution for large-scale deployments Place abstract here: usually a single paragraph summarizing the problem, approach, and results that are in the paper.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120947666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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