2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"An Evaluation of the Electrical Stability of Copper Filled Isotropic Conductive Adhesives in High Moisture Environments","authors":"Shanda Wang, D. Hutt, D. Whalley, G. Critchlow","doi":"10.1109/EPTC.2018.8654274","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654274","url":null,"abstract":"Isotropic Conductive Adhesives (ICAs) consisting of SAM (Self-Assembled Monolayer) coated copper (Cu) powder dispersed in a two-part epoxy adhesive (hereafter referred to as Cu-ICAs) were prepared, stencil printed as tracks on to glass substrates and cured. These test samples were stored within four different environments: a room temperature ambient environment; deionized water at room temperature; $85^{circ}mathrm{C}$ and 85% relative humidity (RH); and $85^{circ}mathrm{C}$ and 1% RH. Samples of a commercial silver (Ag) filled ICA (Ag-ICA), also based on a two-part epoxy resin system, were prepared for comparison. Changes in the electrical conductivity of the stored ICA samples were evaluated using four point probe resistance measurements made by contacting either the top surface (for both ICAs) or lower surface (Cu-ICAs only) of the tracks. The as-prepared Cu-ICAs and Ag-ICAs displayed similar electrical conductivity and showed good electrical stability during long-term storage in ambient conditions. During storage in deionised water the conductivity of the commercial Ag-ICA samples was also stable, whereas the conductivity of the Cu-ICAs measured through the lower surface contact decreased by around 25% after 280 days. Dry high temperature storage $(85^{circ}mathrm{C}$ with 1% RH) accelerated the electrical aging of the Cu-ICAs and the addition of 85% RH considerably accelerated the degradation rate. It was typically seen that there was an apparent greater decline in the conductivity of the specimens when measured through the exposed top surface of the tracks compared to the enclosed lower surface and this was linked to morphological changes seen in the structure of the Cu particles at the sample surface.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131474183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Mechanics of Copper Wire Bond Failure due to Thermal Fatigue","authors":"S. Manoharan, N. M. Li, C. Patel, Stevan Hunter, P. McCluskey","doi":"10.1109/EPTC.2018.8654436","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654436","url":null,"abstract":"Thermal stresses occur on wire Bonds due to mismatch of coefficient of thermal expansion (CTE) between wire and mold compound in addition to the global deformation of the package. This leads to different failure modes (different location of crack in wire bond) based on material and geometrical characteristics of package, ultimately leading to an open circuit. Such failures have been observed and reported widely in literature in the ball bond interface, ball neck region, mid span of wire and at stitch bond; however, little is known about the kind of damage that occurs at these critical regions due to material and geometrical differences in package and wire. Furthermore, different phases of m inter metallic compounds (IMCs) and its thickness that form at the wire bond-bond pad interface alters stress conditions on the wire bond. First part of this study presents a review of existing models to obtain stress in wire Bonds and results of finite element stress analyses from literature. Second part of the work focuses on studying three factors, namely, package type, mold compound material and interfacial changes in wire bond, for understanding types of deformations and stresses that develop on the wire bond. This analysis is aimed at providing vital information about package and materials to aid in optimizing design for extended reliability of wire Bonds.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128040227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study of polysilsesquioxane dielectric for the use of multi-structured redistribution layers in fan-out wafer level packaging applications","authors":"Changmin Song, Sungdong Kim, S. Kim","doi":"10.1109/EPTC.2018.8654290","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654290","url":null,"abstract":"Integrated circuit (IC) technologies have been significantly changed due to the strong demands of high performance, multifunction, low power, small size, and low cost. Furthermore, IC technology paradigms have been shifted to one-chip integration, 3D integration, and multi-function integration. However, since the scaling-down of IC devices has been reached to their physical limitations, several innovative packaging technologies such as 3D packaging, embedded packaging, and fan-out wafer level packaging (FOWLP) are actively studied for high I/O devices. In this study polysilsesquioxane (PSSQ) dielectric materials were investigated for the use of multi-structured redistribution layers in FOWLP applications. Organic-inorganic hybrid dielectric is expected to improve mechanical reliability and thermal stability. In addition, PSSQ has an excellent advantage of simultaneous curing and patterning through UV exposure. A PSSQ solution was spin-coated on 6-inch Si wafer followed by pre-baking and UV exposure. Then the pattern capability of PSSQ dielectric was evaluated by a scanning electron microscope, and the good pattern capability of $2 mu mathrm{m}$ lines was obtained. The dielectric constant of cured PSSQ was ranged from 2.0 to 2.4, and the dielectric loss was ranged from 0.0001 to 0.005. It has been demonstrated that PSSQ can be cured by UV exposure alone without a high temperature curing process.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128139526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Solution for Short Tail Issue on Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) Bond Finger with 0.7mil Gold Wire","authors":"L. Wai, Lim Teck Guan","doi":"10.1109/EPTC.2018.8654319","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654319","url":null,"abstract":"Gold wire bonding process was evaluated with ENEPIG bondfingers which consist of 5umNi/0.2umPd/0.2umAu layers on the Cu traces. Total of 295 wires with wire length range from 2.4 to 3.8mm were bonded for each package. Massive short tail issues were encountered at initial set-up, which resulted in the discontinuity of the wire bonding process. Damage on the bonding surface was observed after the short tail happened which triggered by missing ball alarm. Capillary design with chamfer angle (CA) of 90 Degree and bottle neck height (BNH) of 180um was used and the result shows that short tail was reduced. To achieve short tail free, different ø0.7mil wire types were evaluated. Type A wire (99% Au) is having short tail in most of the runs and low wire pull reading in some cases. Type B (99% Au) and Type C (99.9% Au) wire have good wire pull results and do not have short tail issues. In this study, the key finding is that the wire type is very important for achieving short tail free bonding and right selection of wire provides a wider bonding parameter window. The best few runs had achieved wedge pull strength of $gt 1.5$ gf. from this stud, it is observed that capillary with larger CA and smaller BNH has less short tail issues. From the study, type B and type C do not have short tail issues. Type B wire also has better response to pre-contact and pre-base scrub. Wire type A, (99% Au) has better wire sweep resistance compare to type B and type C. In overall, wire type B has best results in term of bonding continuity and wedge pull results.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133629338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Solder Resist Crack Resistance Process Characterization in BGA Package for Automotive Grade Reliability","authors":"K. Muniandy, C. Jin, J. Peter","doi":"10.1109/EPTC.2018.8654301","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654301","url":null,"abstract":"The numbers of electronic devices are increasing year on year basis in our cars. New additions such as Autonomous Self Driving, ADAS and e-mobility: electrification of cars will include charging and thereby extend further in future our expected requirements for IC’s. These factors have changed the overall requirement demanding more stringent conditions and higher density packages. The requirement for these semiconductor devices are also increasing. Automotive Industry Standards AEC- Q100 requires Grade 0, which indicates that these devices to be exposed to higher temperatures such as $175^{circ}C$, higher than the regular $150^{circ}C$ and for a longer duration. One of the packages that are used under the hood which is submitted to this severe environment, is the Ball Grid Array (BGA) package. The standard BGA package when submitted to these stringent reliability requirements due to the automotive Grade 0 starts to exhibit defects. The major concern seen are the cracks that are propagating through the solder resist level and in some cases propagating even further reaching to the copper traces and causing an open failure. These cracks in the solder resist are evident after the parts were stressed with extended duration at temperature cycling (TC) and also seen during power temperature cycle (PTC). In regards to PTC, more complex considerations are required to ensure proper stress is applied with respect to the device power activation. The cross section of the failed unit showed that the die attach material had resin rich area at the edges. Further failure analysis was carried out on the reject samples and it was found that the crack signature is matching to the peripheral area of the die edge location. Simulation was performed to identify the stress gradient within the region and the results showed that the die attach fillet edge has the highest stress point. Various designs of experiments were carried out to determine or rather establish a process window with the existing bill of material. The initial experiments were conducted by optimizing the fillet height, bond line thickness, epoxy coverage and also the optimization of the epoxy cure profile. Following that the experiments included different candidates of die attach epoxy. These candidates were selected based on their suitable material properties e.g. Tg and CTE. Phase 2 included the different candidates of Solder resist material. In the next step, new solder resist candidates were also evaluated to determine the overall bill of material robustness in regards to the stress and its performance on the cracks. The results are summarized in detail in this paper. In summary the combination of the given bill of materials are limited to existing boundary conditions and further stressing the units at extended stress or accelerated stress levels would certainly push the BGA package to its limits. Further measures must address the concept and design levels to eradicate these defects.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134034882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High Aspect Ratio~10 TSV Via-last-from-back Process Development and Integration","authors":"Xiangy-Yu Wang, Hongyu Li","doi":"10.1109/EPTC.2018.8654305","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654305","url":null,"abstract":"As Moore’s law appears to come to the end when the transistor size approaches to its physical scaling limits, peoples begin to look for the new technology to break through the barrier beyond Moore’s law. TSV is one potential option as it could further increase integration density vertically. In this study, a high aspect ratio 10$mu mathrm{m} times100 mu$m TSV from the wafer back side is demonstrated and some of the critical process will be discussed.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115889009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Challenges and Approaches of 2.5D high density Flip chip interconnect on through mold interposer","authors":"S. Lim, S. Chong, W. Seit, T. Chai","doi":"10.1109/EPTC.2018.8654411","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654411","url":null,"abstract":"The continuous requirements of package miniaturization in the demand of mobile application market have shown the increase in demand of many FOWLP packaging [1]. The applications of FOWLP has many advantages including shorter interconnection, lower heat resistance, better electrical efficiency and smaller package form factor [2].The work presented in this paper describes the reconfigured wafer approach in fan-out wafer level technology that allows multiple dies with high solder interconnect to package using the molded interposer for FOWLP technology. In this work, we presented some of the work done prior to the flip chip bonding process and the different approaches to resolve some of the process issues encountered in the assembly process for 3 test dies with high I/Os onto a fan-out mold interposer. The 1st test die is the 15x15mm ASIC die with 21472 I/Os and the remaining 2 dies are the 7x7mm HBM dies with 4942 I/Os. Both the ASIC and HBM dies have a minimum bump pitch at 55 μ m. The 12 inch through molded interposer wafer is singulated into individual interposer prior to the flip chip attachment process.The package warpage remains the main concern in the through mold interposer assembly. To minimize interposer warpage, a metal stiffener was attached to the molded interposer. Results shows the attachment of the metal stiffener helps to reduce the package warpage. In addition, a thinner die thickness of 150 μ m helps to reduce the overall molded interposer package‘s warpage after assembly compared to a die thickness of 500 μ m. Cross-section analysis was done to inspect the solderjoint shape at 150 μ m and 500 μ m die thickness. Further optimized thermocompression bonding process and capillary underfill process helps to ensure good solderjoint interconnection and no underfill voids for a robust Fine pitch interconnect Fan-out WLP assembly.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116099245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Innovative Approach of efficient High Humidity and High Temperature Reverse Bias Testing as significant Qualification Method for Power Electronic Modules","authors":"M. Mueller, J. Franke","doi":"10.1109/EPTC.2018.8654395","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654395","url":null,"abstract":"The field of today’s power electronics is exposed to continuously increasing requirements. Key issues such as energy efficiency, cost savings and reliability with a simultaneous increase of power represent the new challenges. By innovative wideband gap semiconductor technologies, copper wire bonding, and silver sintered or diffusion soldered layers for die-attach higher temperature limits and current densities can still be realized. In the course of this power modules must be protected against fatigue. In particular these high stresses affect the reliability of modules and therefore the life time.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124816973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of SiC Chip Based Power Package for High Power and High Performance Application","authors":"G. Tang, L. Wai, T. Lim, Zhaohui Chen, Yong Liang Ye, R. Singh, L. Bu, B. L. Lau, T. Chai, Kazunori Yamamoto, Xiaowu Zhang","doi":"10.1109/EPTC.2018.8654429","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654429","url":null,"abstract":"In this paper, a SiC device based power package with double side cooling capability is designed and developed for high power, high performance application. The developed power package mainly consists of high power rated SiC chips, customized metal clips forming the electrical interconnections, and active metal brazing (AMB) substrates with specially designed cavities. the customized interconnects and the use of paralleled high-power SiC devices in the developed package enable its usage for high power applications. High temperature sustainability is obtained by utilizing the high temperature endurable materials for the interconnections and encapsulation. High thermal performance is realized by shortening the heat transfer path from the SiC chips to liquid cooling heat sink and implementing the double side liquid cooling scheme. In addition, by embedding the chip inside the AMB substrate and replacing the wire-bond interconnections with the flatted copper clip interconnections, the developed power package is with low profile. Significant improvement (> 50%) of the thermal performance has been achieved for the developed power package as compared with the thermal performance of the conventional wire bonded power package. Very low loop inductance along the electric current flow path has been obtained (i.e., 2.7nH at 1Mhz of frequency). High temperature endurable package materials (e.g., die attach and encapsulation material) have been evaluated. The developed power package has been fabricated and passed the specified reliability assessments, i.e., unbiased Highly Accelerated Stress Test (HAST), temperature cycling (TC) test (40 ~200 °C), High temperature storage (HTS) test at 250 °C and power cycling (PC) test ($Delta$ T= 150 °C).","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"603 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123149643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Simulation Approach to Predict Warpage based on Resin Curing Behavior during Substrate Manufacturing Process","authors":"Masaharu Furuyama, Hideaki Nagaoka, T. Akahoshi, D. Mizutani, S. Sakuyama, M. Nagatake, Nobutaka Itoh","doi":"10.1109/EPTC.2018.8654387","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654387","url":null,"abstract":"Progress in the high-density mounting of electronic equipment warrants a manufacturing technique for suppressing the warpage of the circuit board and an analysis technique for predicting warpage. In this study, we developed a technique to accurately predict the difference in circuit board warpage caused by variations in manufacturing process by simulating resin curing behavior. As a result, the manufacturing process was optimized to reduce mounting failure caused by substrate warpage.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"600 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123150548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}