Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654424
Y. Shang, M. Shinohara, Rahul Babu Radhamony, J. Kiljan, Alan Wu
In the prevailing era of Internet of Things (IoT), the conventional failure analysis methodologies are more and more challenged by largely increased I/O density and data throughput with complex chip structures developed such as 3D IC and 2.5D packaging technology. Recently, impulse-based time-domain reflectometry (TDR) has gradually become a popular method to quickly localize a failure point in 2.5D/3D chip package with high resolution. However, it is still a big challenge to apply such TDR analysis for the defect characterization inside the die. In this work, a recursive modeling technique is proposed to enable the TDR analysis inside the die to the frontend-of-line (FEOL) interface.
{"title":"High-resolution Time-domain Reflectometry Analysis in Back-end-of-line (BEOL) by Recursive Circuit Modelling","authors":"Y. Shang, M. Shinohara, Rahul Babu Radhamony, J. Kiljan, Alan Wu","doi":"10.1109/EPTC.2018.8654424","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654424","url":null,"abstract":"In the prevailing era of Internet of Things (IoT), the conventional failure analysis methodologies are more and more challenged by largely increased I/O density and data throughput with complex chip structures developed such as 3D IC and 2.5D packaging technology. Recently, impulse-based time-domain reflectometry (TDR) has gradually become a popular method to quickly localize a failure point in 2.5D/3D chip package with high resolution. However, it is still a big challenge to apply such TDR analysis for the defect characterization inside the die. In this work, a recursive modeling technique is proposed to enable the TDR analysis inside the die to the frontend-of-line (FEOL) interface.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123867052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654447
Haoran Chen, Yong Han, G. Tang, Xiaowu Zhang
Liquid cooling system for IT device shows potential of energy efficiency, which is very attractive to data center owner. To exploit the capability of the liquid cooling system, proper controller should be designed. This paper presents the design of model and controller for the liquid cooling system. First, the mathematical models for each individual component are derived from physical laws. Model parameters are determined by the performance curve. Based on the working point selection program and control parameter optimization process, the proportional-integration controller with feedforward path (PI-FF) is designed. Target tracking task and disturbance rejection task are used to evaluate the performance of the PI-FF controller. The results and simulations not only validate the capability of proposed control method, but also in-depth revealed the key physical bottleneck that prevent improving the response of the controller. This result suggests that heat transfer process from junction to the coolant should be as shot as possible, and therefore direct bonding the micro cooler to the chip could be the most efficient way to reduce their interface thickness.
{"title":"Modeling and Control of Hybrid Si-Based Micro-Fluid Cooling System for Data Center Application","authors":"Haoran Chen, Yong Han, G. Tang, Xiaowu Zhang","doi":"10.1109/EPTC.2018.8654447","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654447","url":null,"abstract":"Liquid cooling system for IT device shows potential of energy efficiency, which is very attractive to data center owner. To exploit the capability of the liquid cooling system, proper controller should be designed. This paper presents the design of model and controller for the liquid cooling system. First, the mathematical models for each individual component are derived from physical laws. Model parameters are determined by the performance curve. Based on the working point selection program and control parameter optimization process, the proportional-integration controller with feedforward path (PI-FF) is designed. Target tracking task and disturbance rejection task are used to evaluate the performance of the PI-FF controller. The results and simulations not only validate the capability of proposed control method, but also in-depth revealed the key physical bottleneck that prevent improving the response of the controller. This result suggests that heat transfer process from junction to the coolant should be as shot as possible, and therefore direct bonding the micro cooler to the chip could be the most efficient way to reduce their interface thickness.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123060310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654373
Lau Boon Long, C. Zhaohui, Simon Lim Siak Boon, Sharon Lim Pei Siang
This paper is presenting the fabrication of wafer substrate level chip-scale packaging process on MEMS. The key processes are to develop the over-mold wafer level chip-scale packaging solution for MEMS which using metal deposited silicon pillar and Cu/Pd vertical wire as through-mold interconnection (TMI). Wafer level RDL process to route the contact point to UBM bumping pads which going to bond with PCB. The key challenges and process steps are discussed here: Wafer level epoxy molding materials selection; several approaches on molding process optimization; silicon to epoxy molded layers density and thickness ratio control and post mold curing conditions settings were studied to minimize the wafer warpage at <1.5 mm which was induced from CTE mismatch between silicon and epoxy materials. After backgrinding process to reveal the silicon pillar or Cu/Pd vertical wire contact surfaces; subsequent RDL processes are following by physical vapour deposition (PVD) to deposit metal seed layer, electroplating process (ECP) to build the copper metal lines on selective area which isolated by photoresist patterning; spin-coating process with photosensitive materials to build dielectric layers and developed contact/via opening. Process parameters are optimized to control the thermal budget accumulated from each process steps to minimize the wafer warpage within process window. Dielectric and epoxy mold material evaluation results is presented. The electrically test and reliability test was measured to examine the RDL process connection results and reliability.
{"title":"RDL Process Development of MEMS Wafer Level Chip Scale Packaging with Silicon Pillar/CuPd as Through Mold Interconnection","authors":"Lau Boon Long, C. Zhaohui, Simon Lim Siak Boon, Sharon Lim Pei Siang","doi":"10.1109/EPTC.2018.8654373","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654373","url":null,"abstract":"This paper is presenting the fabrication of wafer substrate level chip-scale packaging process on MEMS. The key processes are to develop the over-mold wafer level chip-scale packaging solution for MEMS which using metal deposited silicon pillar and Cu/Pd vertical wire as through-mold interconnection (TMI). Wafer level RDL process to route the contact point to UBM bumping pads which going to bond with PCB. The key challenges and process steps are discussed here: Wafer level epoxy molding materials selection; several approaches on molding process optimization; silicon to epoxy molded layers density and thickness ratio control and post mold curing conditions settings were studied to minimize the wafer warpage at <1.5 mm which was induced from CTE mismatch between silicon and epoxy materials. After backgrinding process to reveal the silicon pillar or Cu/Pd vertical wire contact surfaces; subsequent RDL processes are following by physical vapour deposition (PVD) to deposit metal seed layer, electroplating process (ECP) to build the copper metal lines on selective area which isolated by photoresist patterning; spin-coating process with photosensitive materials to build dielectric layers and developed contact/via opening. Process parameters are optimized to control the thermal budget accumulated from each process steps to minimize the wafer warpage within process window. Dielectric and epoxy mold material evaluation results is presented. The electrically test and reliability test was measured to examine the RDL process connection results and reliability.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115653338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654414
Zhang Ruifen, Chiong, Kung Chuan Kenny, V. Sureshkumar, Chan Li-san
System in Package (SIP) is a high level integration of different components, dies and chips in one package to achieve multiple function in one system. Solder paste, as a common assembly material, plays the role to connect the components, dies and chips to the substrate to form one package. The dimension of components, die and chip have a big variation in one package, it needs a few different application process to complete the entire package assembly. A new water soluble solder paste (T7 powder) with good printing performance was developed, it can be applied in SiP through printing process to achieve the passive component attach, die attach and flip chip all in one process. The printing performance of a solder paste is critical to improve the production yield in System in Package (SiP). This research work studied the impact of powder type –Type 5, Type 6, Type 7 on the paste printing performance in fine pitch application, mainly on the paste volume deposition and consistency with small opening. The highlight of this paper is to present the excellent printing performance of the newly developed water soluble paste (T7 powder), which can print down to 50um stencil opening with consistent volume deposition and no bridging with line space down to 40um. The void, tombstone and solder bead performance were also tested with 01005 components under actual component attach simulation. The existence of void in solder joint would affect the thermal conductivity and electrical conductivity of the device and hence, minimizing the void in solder joint is critical to improve the reliability of the whole package. This research work also studied on how to reduce void by adjusting reflow profile and applying vacuum during reflow, especially with flip chip and bigger die sizes.
系统级封装(System in Package, SIP)是将不同的元器件、模具和芯片集成到一个封装中，在一个系统中实现多种功能的一种高级集成方式。锡膏作为一种常见的组装材料，起着将元件、模具和芯片连接到基板上形成一个封装的作用。元器件、模具、芯片的尺寸在一个封装中变化较大，需要几个不同的应用工艺才能完成整个封装的组装。研制了一种具有良好印刷性能的新型水溶性焊锡膏(T7粉末)，可通过印刷工艺应用于SiP中，实现无源元件贴附、模具贴附和倒装芯片的一机完成。在系统级封装(SiP)中，焊膏的印刷性能对提高成品率至关重要。本研究主要研究了5型、6型、7型粉末在细间距应用中对浆料印刷性能的影响，主要是对浆料体积沉积和小开口一致性的影响。本文的重点是介绍了新开发的水溶性浆料(T7粉末)优异的打印性能，该浆料可打印至50um的模板开口，体积沉积一致，无桥接，线距低至40um。在实际元器件附着仿真下，对01005元件的空洞、墓碑和焊头性能进行了测试。焊点空隙的存在会影响器件的导热性和导电性，因此减小焊点空隙对提高整个封装的可靠性至关重要。本文还研究了如何通过调整回流曲线和在回流过程中施加真空来减少空穴，特别是在倒装芯片和大尺寸芯片上。
{"title":"Fine Pitch Solder Paste (T7) for System in Package (SiP) Applications","authors":"Zhang Ruifen, Chiong, Kung Chuan Kenny, V. Sureshkumar, Chan Li-san","doi":"10.1109/EPTC.2018.8654414","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654414","url":null,"abstract":"System in Package (SIP) is a high level integration of different components, dies and chips in one package to achieve multiple function in one system. Solder paste, as a common assembly material, plays the role to connect the components, dies and chips to the substrate to form one package. The dimension of components, die and chip have a big variation in one package, it needs a few different application process to complete the entire package assembly. A new water soluble solder paste (T7 powder) with good printing performance was developed, it can be applied in SiP through printing process to achieve the passive component attach, die attach and flip chip all in one process. The printing performance of a solder paste is critical to improve the production yield in System in Package (SiP). This research work studied the impact of powder type –Type 5, Type 6, Type 7 on the paste printing performance in fine pitch application, mainly on the paste volume deposition and consistency with small opening. The highlight of this paper is to present the excellent printing performance of the newly developed water soluble paste (T7 powder), which can print down to 50um stencil opening with consistent volume deposition and no bridging with line space down to 40um. The void, tombstone and solder bead performance were also tested with 01005 components under actual component attach simulation. The existence of void in solder joint would affect the thermal conductivity and electrical conductivity of the device and hence, minimizing the void in solder joint is critical to improve the reliability of the whole package. This research work also studied on how to reduce void by adjusting reflow profile and applying vacuum during reflow, especially with flip chip and bigger die sizes.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115664814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654314
Y. Lu, Bo-Siang Fang, Hsuan-Hao Mi, Kuan-Ta Chen, Mike Tsai
In order to cope with the worldwide shortage of the MLCC (multilayer ceramic capacitor), this paper proposes a methodology of integrated lattice balun using a high permittivity substrate material. It is well known that discrete radio frequency (RF) front-end circuits are composed of MLCCs and chip inductors in many electronic products. Inserting a high permittivity material to replace decoupling capacitors is an effective method. Another way to lessen the quantity of MLCCs is embedding an integrated RF front-end circuit instead of MLCCs, such as a balun, filter or duplexer. In this study, an integrated lattice balun was designed for DCS (digital cellular system) 1800 MHz. The simulation results show that the designed balun achieves a return loss $< -23$ dB, an insertion loss $gt -0.25$ dB, a phase deviation form $180 circ$ to $182 circ$ and a magnitude deviation of less than 1.1 dB in the frequency range of DSC.
{"title":"The Balun Design by Embedding High Permittivity Material in The Substrate of CSP Package with Large Size","authors":"Y. Lu, Bo-Siang Fang, Hsuan-Hao Mi, Kuan-Ta Chen, Mike Tsai","doi":"10.1109/EPTC.2018.8654314","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654314","url":null,"abstract":"In order to cope with the worldwide shortage of the MLCC (multilayer ceramic capacitor), this paper proposes a methodology of integrated lattice balun using a high permittivity substrate material. It is well known that discrete radio frequency (RF) front-end circuits are composed of MLCCs and chip inductors in many electronic products. Inserting a high permittivity material to replace decoupling capacitors is an effective method. Another way to lessen the quantity of MLCCs is embedding an integrated RF front-end circuit instead of MLCCs, such as a balun, filter or duplexer. In this study, an integrated lattice balun was designed for DCS (digital cellular system) 1800 MHz. The simulation results show that the designed balun achieves a return loss $< -23$ dB, an insertion loss $gt -0.25$ dB, a phase deviation form $180 circ$ to $182 circ$ and a magnitude deviation of less than 1.1 dB in the frequency range of DSC.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122678608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654420
Manuel Baeuscher, Bei Wang, Xiaodong Hu, P. Mackowiak, Norman Merchau, O. Ehrmann, M. Schneider-Ramelow, K. Lang, H. Ngo
Due to the growing numbers of elderly people in the world, who suffer from incontinence and are in the need of care, technologies are necessary to increase the effectiveness of nursing staff and enhance the hygiene for humans to improve life quality. For this reason a low cost humidity sensor system printed onto the substrate of a diaper with the novel organic conductive ink PEDOT:PSS (Poly (3,4-ethylenedioxythio-phene):Poly(styrene sulfonate)) was developed in previous work [1]. The novel material PEDOT:PSS is still expensive because of rare use in research and market demand. Therefore a way for optimization of the sensor is aimed to print the sensor with less material, but at the same time with no loss of sensitivity. With this purpose, two theoretical models are developed. An analytic model with geometrical based calculations and a Finite Element Analysis (FEA) simulation model, for deeper understanding of electric field effects with focus on the total capacitance of the sensor. To verify these theoretical models a characterization measurement of manufactured samples of previous work [1] is made, to obtain a comparison between every experimental method. For the theoretical models the necessary material parameters are characterized.
{"title":"Simulation And Electrical Characterization Of A Novel 2D-Printed Incontinence Sensor With Conductive Polymer PEDOT:PSS For Medical Applications","authors":"Manuel Baeuscher, Bei Wang, Xiaodong Hu, P. Mackowiak, Norman Merchau, O. Ehrmann, M. Schneider-Ramelow, K. Lang, H. Ngo","doi":"10.1109/EPTC.2018.8654420","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654420","url":null,"abstract":"Due to the growing numbers of elderly people in the world, who suffer from incontinence and are in the need of care, technologies are necessary to increase the effectiveness of nursing staff and enhance the hygiene for humans to improve life quality. For this reason a low cost humidity sensor system printed onto the substrate of a diaper with the novel organic conductive ink PEDOT:PSS (Poly (3,4-ethylenedioxythio-phene):Poly(styrene sulfonate)) was developed in previous work [1]. The novel material PEDOT:PSS is still expensive because of rare use in research and market demand. Therefore a way for optimization of the sensor is aimed to print the sensor with less material, but at the same time with no loss of sensitivity. With this purpose, two theoretical models are developed. An analytic model with geometrical based calculations and a Finite Element Analysis (FEA) simulation model, for deeper understanding of electric field effects with focus on the total capacitance of the sensor. To verify these theoretical models a characterization measurement of manufactured samples of previous work [1] is made, to obtain a comparison between every experimental method. For the theoretical models the necessary material parameters are characterized.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"87 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124997535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654410
C. Zihao, Lim Teck Guan
In this paper, a 77 GHz reconstitute resonator without TMV is integrated in fan-out wafer level packaging (FOWLP) with mold first process. The resonator is pre-fabricated with a high dielectric constant and low tangent loss dielectric material to achieve small volume and high Q. The side walls of the resonator are plated with copper. The resonator is embedded in the molding compound and RDLs are used to connect the chip and resonator. A Q-factor of 354.4 is achieved. A small form factor and self-shielding cavity-back slot antenna is proposed based on reconstitute resonator. The fractional bandwidth is 1.89% at 79 GHz and the maximal antenna gain is 5 dBi.
{"title":"Millimeter wave resonator and cavity-back slot antenna in Fan-Out Wafer Level Packaging","authors":"C. Zihao, Lim Teck Guan","doi":"10.1109/EPTC.2018.8654410","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654410","url":null,"abstract":"In this paper, a 77 GHz reconstitute resonator without TMV is integrated in fan-out wafer level packaging (FOWLP) with mold first process. The resonator is pre-fabricated with a high dielectric constant and low tangent loss dielectric material to achieve small volume and high Q. The side walls of the resonator are plated with copper. The resonator is embedded in the molding compound and RDLs are used to connect the chip and resonator. A Q-factor of 354.4 is achieved. A small form factor and self-shielding cavity-back slot antenna is proposed based on reconstitute resonator. The fractional bandwidth is 1.89% at 79 GHz and the maximal antenna gain is 5 dBi.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"32 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123430482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654312
M. Eibelhuber, J. Rimböck, T. Zenger, T. Uhrmann, T. Matthias
Photoresist coating and patterning are the most repeated process steps in advanced packaging. Spin coating is still the prevalent method of coating planar surfaces and the patterning of thin films. However thick resist processing [1] and spray coating [2] are nowadays well established and commonly used for advanced patterning requirements. Thick resist processing is widely used for plating of interconnects [3] or LIGA fabrication. Spray coating is mainly used to efficiently protect or pattern severe topography and an essential process for packaging, plasma dicing, and MEMS.
{"title":"Combined Thick Resist Processing and Topography Patterning for Advanced Metal Plating","authors":"M. Eibelhuber, J. Rimböck, T. Zenger, T. Uhrmann, T. Matthias","doi":"10.1109/EPTC.2018.8654312","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654312","url":null,"abstract":"Photoresist coating and patterning are the most repeated process steps in advanced packaging. Spin coating is still the prevalent method of coating planar surfaces and the patterning of thin films. However thick resist processing [1] and spray coating [2] are nowadays well established and commonly used for advanced patterning requirements. Thick resist processing is widely used for plating of interconnects [3] or LIGA fabrication. Spray coating is mainly used to efficiently protect or pattern severe topography and an essential process for packaging, plasma dicing, and MEMS.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129834672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654407
X. Long, C. Du, Wenbin Tang, Yongchao Liu, Yao Yao, Fengrui Jia
Due to scale effect, sintered silver nanoparticles (AgNP) own the most appealing advantage of low temperature sintering and high temperature service. Compared with other solder materials, sintered AgNP has superior high thermal and electrical conductivities, which benefits the application of packaging structures subjected to high current density in advanced electronic devices. This study quantifies the mechanical properties of sintered AgNP using single lap joint specimens, which were prepared with an overlapped area of 2.0 mm $times2.0$ mm and mechanically tested to obtain the shear load-displacement responses under different shear strain rates ranging from $10 ^{-3} /mathrm{s}$ to $5 times 10 ^{-2} /$s. The failure occurred within the sintered AgNP rather than the interface between AgNP and Au coating.
{"title":"Constitutive Behaviour of Single Lap Joint of Sintered Silver Paste","authors":"X. Long, C. Du, Wenbin Tang, Yongchao Liu, Yao Yao, Fengrui Jia","doi":"10.1109/EPTC.2018.8654407","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654407","url":null,"abstract":"Due to scale effect, sintered silver nanoparticles (AgNP) own the most appealing advantage of low temperature sintering and high temperature service. Compared with other solder materials, sintered AgNP has superior high thermal and electrical conductivities, which benefits the application of packaging structures subjected to high current density in advanced electronic devices. This study quantifies the mechanical properties of sintered AgNP using single lap joint specimens, which were prepared with an overlapped area of 2.0 mm $times2.0$ mm and mechanically tested to obtain the shear load-displacement responses under different shear strain rates ranging from $10 ^{-3} /mathrm{s}$ to $5 times 10 ^{-2} /$s. The failure occurred within the sintered AgNP rather than the interface between AgNP and Au coating.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125334774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654401
Daiki Kumagwa, M. Sakamoto, Yohei Aoki, T. Asano
The cone-shaped micro bump provides fine-pitch room-temperature flip-chip Bonding technology. It has been demonstrated to be able to connect $15 mu mathrm {m}$-pitch 640x512 array pixels of an image sensor composed of a compound semiconductor photodetector array and silicon readout integrated circuit. The cone-shaped micro bump is fabricated by utilizing the characteristic of the chemical amplification photoresist. For further shrinkage of the interconnection pitch below $10 mu mathrm {m}$, not only refining of process condition But also a new design of photoresist is required. In this work, we build a model and a simulation method to investigate how the property of the photoresist and process condition determine the final shape of the cone bump.
锥形微凸点提供了细间距室温倒装芯片键合技术。它已被证明能够连接由复合半导体光电探测器阵列和硅读出集成电路组成的图像传感器的$15 mu mathm {m}$-pitch 640x512阵列像素。利用化学放大光刻胶的特性制备了锥形微凸点。为了使互连间距进一步缩小到$10 mu mathm {m}$以下，不仅需要改进工艺条件，而且需要设计新的光刻胶。在这项工作中，我们建立了一个模型和仿真方法来研究光刻胶的性质和工艺条件如何决定锥形凸起的最终形状。
{"title":"Modeling and simulation of chemical amplification photoresist to produce high-density cone-shaped micro bumps","authors":"Daiki Kumagwa, M. Sakamoto, Yohei Aoki, T. Asano","doi":"10.1109/EPTC.2018.8654401","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654401","url":null,"abstract":"The cone-shaped micro bump provides fine-pitch room-temperature flip-chip Bonding technology. It has been demonstrated to be able to connect $15 mu mathrm {m}$-pitch 640x512 array pixels of an image sensor composed of a compound semiconductor photodetector array and silicon readout integrated circuit. The cone-shaped micro bump is fabricated by utilizing the characteristic of the chemical amplification photoresist. For further shrinkage of the interconnection pitch below $10 mu mathrm {m}$, not only refining of process condition But also a new design of photoresist is required. In this work, we build a model and a simulation method to investigate how the property of the photoresist and process condition determine the final shape of the cone bump.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130175193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：