Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654422
L. Bu, Hongyu Li, Xiaowu Zhang
A new architecture has been demonstrated for microfabricated ion traps, built around ceramic ball-grid array (BGA) connections. 56MHz RF frequency is applied to generate the electric field to trap the ions. The interposer is wirebonded to a Kyocera CPGA (Ceramic pin grid array) carrier for signal routing. As low temperature is favorable for ion trap chips, the material selection has to be done carefully in the present paper. Two kinds of materials, i.e., device passivation materials and die attach materials, are simulated and tested by the experiment. In the mechanical simulation, HD-4100 and HD8930 has lower mechanical stress. However, the short loop test reveals that almost all the bumps are detached from HD-4100 material and there are lots of unknown whiskers are founded after the samples are tested at 17K for 1 hour. Hence, SiO2 is still the first choice as passivation material in our process. For die attach materials, two kinds of material are evaluated in our experiment.
{"title":"Material Selection for Ion Trap Chip Working at Extreme Low Temperatures","authors":"L. Bu, Hongyu Li, Xiaowu Zhang","doi":"10.1109/EPTC.2018.8654422","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654422","url":null,"abstract":"A new architecture has been demonstrated for microfabricated ion traps, built around ceramic ball-grid array (BGA) connections. 56MHz RF frequency is applied to generate the electric field to trap the ions. The interposer is wirebonded to a Kyocera CPGA (Ceramic pin grid array) carrier for signal routing. As low temperature is favorable for ion trap chips, the material selection has to be done carefully in the present paper. Two kinds of materials, i.e., device passivation materials and die attach materials, are simulated and tested by the experiment. In the mechanical simulation, HD-4100 and HD8930 has lower mechanical stress. However, the short loop test reveals that almost all the bumps are detached from HD-4100 material and there are lots of unknown whiskers are founded after the samples are tested at 17K for 1 hour. Hence, SiO2 is still the first choice as passivation material in our process. For die attach materials, two kinds of material are evaluated in our experiment.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128129520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654311
Kisu Joo, Kyu Jae Lee, Jung-Woo Hwang, Jin-Ho Yoon, Yoonhyun Kim, Se Young Jeong
We studied and demonstrated high-performance Ag epoxy composites. A variety of shaped Ag particles were teste to optimize the electrical properties and mechanical reliability. The resulting Ag epoxy composites containing flake-shaped Ag particles showed less than $5 times 10 ^{-7} Omega cdot mathrm {m}$ electrical conductivity and about $20mathrm {m} Omega $ series-resistance of PKG daisy chain, which directly corresponded to the excellent shield effectiveness. The shield effectiveness of resulting EMI shielding layer made of Ag and matrix is as high as 60dB, 65dB, 70dB at 5 $mu {mathrm{ m}}$, 10 $mu {mathrm{ m}}$, 20 $mu {mathrm{ m}}$-thick film, respectively by ASTM standard. We studied that how various factors, such as curing temperature, Ag contents, and film thickness, effects the electrical properties of shielding material and FCBGA package. It was found that the resistivity of conductive shielding material and the series-resistance were affected by the curing temperature than the curing time. Additionally, we demonstrated the electrical properties of AgCu epoxy composites.
{"title":"High Performance Package-Level EMI shielding of Ag Epoxy Composites with Spray method for High Frequency FCBGA package Application","authors":"Kisu Joo, Kyu Jae Lee, Jung-Woo Hwang, Jin-Ho Yoon, Yoonhyun Kim, Se Young Jeong","doi":"10.1109/EPTC.2018.8654311","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654311","url":null,"abstract":"We studied and demonstrated high-performance Ag epoxy composites. A variety of shaped Ag particles were teste to optimize the electrical properties and mechanical reliability. The resulting Ag epoxy composites containing flake-shaped Ag particles showed less than $5 times 10 ^{-7} Omega cdot mathrm {m}$ electrical conductivity and about $20mathrm {m} Omega $ series-resistance of PKG daisy chain, which directly corresponded to the excellent shield effectiveness. The shield effectiveness of resulting EMI shielding layer made of Ag and matrix is as high as 60dB, 65dB, 70dB at 5 $mu {mathrm{ m}}$, 10 $mu {mathrm{ m}}$, 20 $mu {mathrm{ m}}$-thick film, respectively by ASTM standard. We studied that how various factors, such as curing temperature, Ag contents, and film thickness, effects the electrical properties of shielding material and FCBGA package. It was found that the resistivity of conductive shielding material and the series-resistance were affected by the curing temperature than the curing time. Additionally, we demonstrated the electrical properties of AgCu epoxy composites.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125689426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654309
Atsuhiro Hamasawa, H. Kanaya
This paper presents the design of a dual-band low noise amplifier (LNA) with a single input differential outputs of 5.2 GHz and 2.4GHz band with $0.18 mu mathrm{m}$ CMOS technology. In order to achieve the goal of expanding the availability of telecommunication system, this LNA is designed as a dual-band operation by using a band pass filter and a notch filter simultaneously [1]. Moreover, by introducing the CG (common gate)-CS (common source) topology [2], we can obtain the output phase differs by 0 and 180 degrees. This will reduce the connection loss to the mixer developed in the previous study [3]. In this paper, simulation results of gain, noise figure and output phase difference are shown, and a chip layout is shown. The proposed LNA has a gain of 16.5 dB and 11.1 dB at 2.4 GHz and 5.2 GHz, a noise figure of 3.1 dB and 3.7 dB, and the phase difference is less than 0.32 degrees.
{"title":"Dual-band differential outputs CMOS Low Noise Amplifier","authors":"Atsuhiro Hamasawa, H. Kanaya","doi":"10.1109/EPTC.2018.8654309","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654309","url":null,"abstract":"This paper presents the design of a dual-band low noise amplifier (LNA) with a single input differential outputs of 5.2 GHz and 2.4GHz band with $0.18 mu mathrm{m}$ CMOS technology. In order to achieve the goal of expanding the availability of telecommunication system, this LNA is designed as a dual-band operation by using a band pass filter and a notch filter simultaneously [1]. Moreover, by introducing the CG (common gate)-CS (common source) topology [2], we can obtain the output phase differs by 0 and 180 degrees. This will reduce the connection loss to the mixer developed in the previous study [3]. In this paper, simulation results of gain, noise figure and output phase difference are shown, and a chip layout is shown. The proposed LNA has a gain of 16.5 dB and 11.1 dB at 2.4 GHz and 5.2 GHz, a noise figure of 3.1 dB and 3.7 dB, and the phase difference is less than 0.32 degrees.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127734910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654349
Zhi Jin, H. Nishikawa, Y. Chan
In recent years, the demand of lithium ion battery is enlarged because of enormous capacity and free from memory effect which was widely applied to electronic devices. However, the explosion of Samsung Note7 battery arouses public attention in of lithium ion battery‘s safety issue. In addition, the capacity of battery will drop during usage time, one battery can only work for two years normally. In this study, we will find caused the explosion and capacity decrease of battery during usage process. The methodology started with thermal shock test to accelerate the aging time of battery. During the testing, the capacity change of battery after each 200 h was recorded. After the test, each component including the protective circuit, cathode and anode were analyzed respectively. From protective circuit aspects, the corrosion of PCB by hydrofluoric acid will cause malfunction of the circuit leading to overcharging or over-discharging. Since the decomposition of SEI on anode leading to exfoliation of graphite. The generation of fresh SEI will consume lithium ion inside the electrolyte leading to capacity decrease. Moreover, the phenomenon why some batteries will be swollen up during usage has been analyzed from chemical reaction aspect. Finally, this study can be used to offer good suggestions to manufacturers in improving the reliability of lithium ion battery.
{"title":"Failure analysis on Mobile Phone Batteries and Accessories","authors":"Zhi Jin, H. Nishikawa, Y. Chan","doi":"10.1109/EPTC.2018.8654349","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654349","url":null,"abstract":"In recent years, the demand of lithium ion battery is enlarged because of enormous capacity and free from memory effect which was widely applied to electronic devices. However, the explosion of Samsung Note7 battery arouses public attention in of lithium ion battery‘s safety issue. In addition, the capacity of battery will drop during usage time, one battery can only work for two years normally. In this study, we will find caused the explosion and capacity decrease of battery during usage process. The methodology started with thermal shock test to accelerate the aging time of battery. During the testing, the capacity change of battery after each 200 h was recorded. After the test, each component including the protective circuit, cathode and anode were analyzed respectively. From protective circuit aspects, the corrosion of PCB by hydrofluoric acid will cause malfunction of the circuit leading to overcharging or over-discharging. Since the decomposition of SEI on anode leading to exfoliation of graphite. The generation of fresh SEI will consume lithium ion inside the electrolyte leading to capacity decrease. Moreover, the phenomenon why some batteries will be swollen up during usage has been analyzed from chemical reaction aspect. Finally, this study can be used to offer good suggestions to manufacturers in improving the reliability of lithium ion battery.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126209457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654269
Yong Han, B. L. Lau, G. Tang, S. Lim, Xiaowu Zhang
Thermal test package has been designed to mimic the thermal performance of mainstream processor used in data center for micro-fluid cooling characterization. The target heat power of the test chip is $gt$150W for characterization. Platinum (Pt) heaters and temperature sensors have been designed in thermal test chip. Regarding meander heat line, three types of structure have been designed while maintaining same total electrical resistance in each chip. To fabricate the thermal test chip, 5 masks have been designed and prepared. Pt heaters and sensors have been fabricated simultaneously using DC sputtering process. The thermal test chips located at different positions in one wafer are measured, and the sensors located at different positions in the chips are tested as well. Results show that average resistances of heater and sensor are 300$Omega$ and 1075$Omega$ respectively, and errors are within ±5%. The thermal test packages work quite well at high heating power in the cooling solution characterization tests
{"title":"Development of Thermal Test Package for Data Center Micro-Fluid Cooling Characterization","authors":"Yong Han, B. L. Lau, G. Tang, S. Lim, Xiaowu Zhang","doi":"10.1109/EPTC.2018.8654269","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654269","url":null,"abstract":"Thermal test package has been designed to mimic the thermal performance of mainstream processor used in data center for micro-fluid cooling characterization. The target heat power of the test chip is $gt$150W for characterization. Platinum (Pt) heaters and temperature sensors have been designed in thermal test chip. Regarding meander heat line, three types of structure have been designed while maintaining same total electrical resistance in each chip. To fabricate the thermal test chip, 5 masks have been designed and prepared. Pt heaters and sensors have been fabricated simultaneously using DC sputtering process. The thermal test chips located at different positions in one wafer are measured, and the sensors located at different positions in the chips are tested as well. Results show that average resistances of heater and sensor are 300$Omega$ and 1075$Omega$ respectively, and errors are within ±5%. The thermal test packages work quite well at high heating power in the cooling solution characterization tests","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127502215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654425
David Choong Sze Wai, Ruiqi Lim, M. R. Damalerio, Weiguo Chen, Ming-Yuan Cheng
In this work, we present a flexible printed multi-functional sensor platform for medical applications. The device consists of printed temperature and force elements on a flexible printed circuit board (FPCB). The thickness, curing temperatures and encapsulating epoxies are optimized for the individual inks and the device is assembled and tested on the benchtop. Force measurements against impedance and temperature measurements against impedance were then conducted and discussed. The performance of both sensors were then characterized.
{"title":"Development of a Flexible Printed Multi-Functional Sensor Platform for Medical Applications","authors":"David Choong Sze Wai, Ruiqi Lim, M. R. Damalerio, Weiguo Chen, Ming-Yuan Cheng","doi":"10.1109/EPTC.2018.8654425","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654425","url":null,"abstract":"In this work, we present a flexible printed multi-functional sensor platform for medical applications. The device consists of printed temperature and force elements on a flexible printed circuit board (FPCB). The thickness, curing temperatures and encapsulating epoxies are optimized for the individual inks and the device is assembled and tested on the benchtop. Force measurements against impedance and temperature measurements against impedance were then conducted and discussed. The performance of both sensors were then characterized.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131296861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654418
N. Subbiah, Qingming Feng, K. Ramirez, J. Wilde, G. Bruckner
Pressure sensors working at high temperatures of $500 ^{circ}C$ are required in various fields like aerospace, automobile and many industries. However, reliable sensors working at such high temperature are still not sufficiently developed. Mainly, developing a high temperature stable package imposes new challenges due to thermal cross-sensitivity and temperature induced stresses. Other major issues are to identify stable materials for high temperatures and stress-tolerant sensor mounting techniques. This research work focuses on the implementation of a stress-tolerant pressure sensor design for applications up to $500 ^{circ}C$: A micro strain gauge is deposited and patterned on a Langasite (LGS) crystal. It is attached to a ceramic substrate Al2O3 like a cantilever by flip-chip interconnection and glass solder underfill. The flip-chip bonding is done using gold stud bumps. The ceramic substrate has a membrane structure which is fabricated by ultrasonic machining. The deflection of the deforming membrane will be transferred pointwise to the free end of the crystal inside the package. The strain induced on the cantilever is measured by the change of resistance of a microstrain gauge. This special design concept aims at the elimination of thermal stresses between membrane and sensing device, which could induce cross-sensitivity. In this paper, processes to develop the complete assembly are presented including the choice of materials and fabrication methodology for individual parts. The resulting sensor package is stable for operations up to $500 ^{circ}C$.
{"title":"Implementation of High-Temperature Pressure Sensor Package and Characterization up to 500°C","authors":"N. Subbiah, Qingming Feng, K. Ramirez, J. Wilde, G. Bruckner","doi":"10.1109/EPTC.2018.8654418","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654418","url":null,"abstract":"Pressure sensors working at high temperatures of $500 ^{circ}C$ are required in various fields like aerospace, automobile and many industries. However, reliable sensors working at such high temperature are still not sufficiently developed. Mainly, developing a high temperature stable package imposes new challenges due to thermal cross-sensitivity and temperature induced stresses. Other major issues are to identify stable materials for high temperatures and stress-tolerant sensor mounting techniques. This research work focuses on the implementation of a stress-tolerant pressure sensor design for applications up to $500 ^{circ}C$: A micro strain gauge is deposited and patterned on a Langasite (LGS) crystal. It is attached to a ceramic substrate Al2O3 like a cantilever by flip-chip interconnection and glass solder underfill. The flip-chip bonding is done using gold stud bumps. The ceramic substrate has a membrane structure which is fabricated by ultrasonic machining. The deflection of the deforming membrane will be transferred pointwise to the free end of the crystal inside the package. The strain induced on the cantilever is measured by the change of resistance of a microstrain gauge. This special design concept aims at the elimination of thermal stresses between membrane and sensing device, which could induce cross-sensitivity. In this paper, processes to develop the complete assembly are presented including the choice of materials and fabrication methodology for individual parts. The resulting sensor package is stable for operations up to $500 ^{circ}C$.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"61 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113977242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654389
W. Loh, Qin Ren
In this paper, Through Silicon Via (TSV) of Silicon on isolator (SOI) platform on via last wafer integration challenges were evaluated. TSV profile at Buried Oxide (BOX) and bulk Silicon of SOI substrates undercut improvement was assessed. Electroplating (ECP) TSV wafer uniformity and its impact on Chemical Mechanical Polishing (CMP) was discussed. Improvement in Electroplating wafer uniformity has shown significant improvement in CMP remaining oxide uniformity.
{"title":"EPIC Via Last on SOI Wafer Integration Challenges","authors":"W. Loh, Qin Ren","doi":"10.1109/EPTC.2018.8654389","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654389","url":null,"abstract":"In this paper, Through Silicon Via (TSV) of Silicon on isolator (SOI) platform on via last wafer integration challenges were evaluated. TSV profile at Buried Oxide (BOX) and bulk Silicon of SOI substrates undercut improvement was assessed. Electroplating (ECP) TSV wafer uniformity and its impact on Chemical Mechanical Polishing (CMP) was discussed. Improvement in Electroplating wafer uniformity has shown significant improvement in CMP remaining oxide uniformity.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"19 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114046465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654300
C. Cavaco, Konstantinos Chatzinis, Bert van Lijnschoten, S. Guerrieri
In this paper is reported for the first-time wafer level electrical data on 200 mm wafer to wafer hybrid copper to dielectric bonding at low temperature, using SiN as the dielectric material. In this work was used up to five metal levels per wafer. SiN is here investigated for its feasibility to replace SiOx or SiCN in the hybrid bonding. Furthermore, for the first-time reliability testing is here reported when using either SiN or SiOx as the dielectric layer.
{"title":"Hybrid Cu-SiN and Cu-SiOx Direct Bonding of 200 MM CMOS Wafers with Five Metal Levels: Morphological, Electrical and Reliability Characterization","authors":"C. Cavaco, Konstantinos Chatzinis, Bert van Lijnschoten, S. Guerrieri","doi":"10.1109/EPTC.2018.8654300","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654300","url":null,"abstract":"In this paper is reported for the first-time wafer level electrical data on 200 mm wafer to wafer hybrid copper to dielectric bonding at low temperature, using SiN as the dielectric material. In this work was used up to five metal levels per wafer. SiN is here investigated for its feasibility to replace SiOx or SiCN in the hybrid bonding. Furthermore, for the first-time reliability testing is here reported when using either SiN or SiOx as the dielectric layer.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127963932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654345
Haiyan Liu, Xiangyang Li, Sean Xu, Jun Li
Converting gold wire to copper wire for IC packaging is a big trend recently which has both advantage and disadvantage. Cu wire is good for packaging cost saving to current semiconductor industry, but it may also create quality and reliability issues. Since Cu is much harder and stiffer material than Au, it may require a greater force and USG power to insure good bonding to pad, and a larger bond force and USG power in turn increases the risk of ILD crack during the bonding process. The wafer tech in this study is CMOS40nm, Al thickness is 28KA, with 53um pad opening. The ILD crack mechanism which is discussed in this paper is different. The failure mode during ATE test is leakage failure. After de-cap and cratering test, there is no cratering / damage on failed pad under microscope check. FIB was performed on failed pad and confirmed the damage between Metal 2 and Metal 3, and no damage on top metal. The link between IV curve trace and ILD crack was studied. The root cause of the ILD crack was studied, material and machine variation were also take into consideration. Parameter optimization DOE was done. Key wire bond parameters include the initial force, USG power etc. The wire pull, ball shear, IMC, Al remnant etc. are key response. The result shows that lower USG and higher initial force can get better wire bond performance. The die was packaged into a MAPBGA package. Electrical test was performed on the assembled parts at T0, post MSL3/260degree C, post 264h UHST $(110 ^{circ}mathrm{C} /85$%RH), and post TC700cycles ($- 55 ^{circ}mathrm{C}$ to $150 ^{circ}mathrm{C})$. All units post stress clean passed without any failure. The overall leakage failure rate at ATE test is reduced.
{"title":"A New Failure Mechanism of Inter Layer Dielectric Crack","authors":"Haiyan Liu, Xiangyang Li, Sean Xu, Jun Li","doi":"10.1109/EPTC.2018.8654345","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654345","url":null,"abstract":"Converting gold wire to copper wire for IC packaging is a big trend recently which has both advantage and disadvantage. Cu wire is good for packaging cost saving to current semiconductor industry, but it may also create quality and reliability issues. Since Cu is much harder and stiffer material than Au, it may require a greater force and USG power to insure good bonding to pad, and a larger bond force and USG power in turn increases the risk of ILD crack during the bonding process. The wafer tech in this study is CMOS40nm, Al thickness is 28KA, with 53um pad opening. The ILD crack mechanism which is discussed in this paper is different. The failure mode during ATE test is leakage failure. After de-cap and cratering test, there is no cratering / damage on failed pad under microscope check. FIB was performed on failed pad and confirmed the damage between Metal 2 and Metal 3, and no damage on top metal. The link between IV curve trace and ILD crack was studied. The root cause of the ILD crack was studied, material and machine variation were also take into consideration. Parameter optimization DOE was done. Key wire bond parameters include the initial force, USG power etc. The wire pull, ball shear, IMC, Al remnant etc. are key response. The result shows that lower USG and higher initial force can get better wire bond performance. The die was packaged into a MAPBGA package. Electrical test was performed on the assembled parts at T0, post MSL3/260degree C, post 264h UHST $(110 ^{circ}mathrm{C} /85$%RH), and post TC700cycles ($- 55 ^{circ}mathrm{C}$ to $150 ^{circ}mathrm{C})$. All units post stress clean passed without any failure. The overall leakage failure rate at ATE test is reduced.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129197770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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