Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654339
Z. Cen, X. Shan, B. Salam, L. S. Rachel Tan, J. Wei
In order to print various functional components for printed electronics, inks with different viscosities may be used in gravure printing. In this study, influence of ink viscosity on gravure printing quality at individual cell level is reported. In gravure printing experiments using dielectric Barium Titanate (BaTiO3) nanoparticles inks of different viscosities, a void defect can be observed at the front edge of the printed pattern of an individual engraved cell. And the void became larger both for ink with higher viscosity and at higher printing speed. In our experiments, it was noticed that the voids can lead to open defects in the whole printed pattern of high viscosity ink, undermining the printing quality. In order to study the forming mechanism of the voids, experimental results were analyzed based on computational fluid dynamic (CFD) simulation studies of wiping step in the gravure printing process. Simulation confirmed that the observed void is caused by the unfilled space at the leading edge of the engraved cell during wiping. Effects of wiping speed and ink viscosity have been investigated, and the simulation results are consistent with experiments. Based on the experimental and theoretical results, it can be concluded that, for gravure printing using high viscosity ink, printing speed needs to be slowed down in order to reduce defects. The present study enhanced understanding of ink transfer in gravure printing and provided a guide line for high quality gravure printing.
{"title":"Void Defect Formed in Wiping Step of Gravure Printing","authors":"Z. Cen, X. Shan, B. Salam, L. S. Rachel Tan, J. Wei","doi":"10.1109/EPTC.2018.8654339","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654339","url":null,"abstract":"In order to print various functional components for printed electronics, inks with different viscosities may be used in gravure printing. In this study, influence of ink viscosity on gravure printing quality at individual cell level is reported. In gravure printing experiments using dielectric Barium Titanate (BaTiO3) nanoparticles inks of different viscosities, a void defect can be observed at the front edge of the printed pattern of an individual engraved cell. And the void became larger both for ink with higher viscosity and at higher printing speed. In our experiments, it was noticed that the voids can lead to open defects in the whole printed pattern of high viscosity ink, undermining the printing quality. In order to study the forming mechanism of the voids, experimental results were analyzed based on computational fluid dynamic (CFD) simulation studies of wiping step in the gravure printing process. Simulation confirmed that the observed void is caused by the unfilled space at the leading edge of the engraved cell during wiping. Effects of wiping speed and ink viscosity have been investigated, and the simulation results are consistent with experiments. Based on the experimental and theoretical results, it can be concluded that, for gravure printing using high viscosity ink, printing speed needs to be slowed down in order to reduce defects. The present study enhanced understanding of ink transfer in gravure printing and provided a guide line for high quality gravure printing.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130409364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654417
Terence Lucero F. Menor, M. Mena, H. Mendoza
Solder paste dispensing is a key process in the electronics assembly. The increased global demand for smaller, lighter, faster and cheaper assemblies drives the electronics industry to use dispensers with finer apertures. However, reduction in the aperture size of dispensers faces the industry with increased clogging of dispensers and incomplete transfer of paste to the printed circuit board (PCB) pads. One factor contributing to the clogging of dispensers is the agglomeration of the solder powder suspensions which depends on the electrokinetic behavior of the particles. When suspensions are close to the point of no charge, wherein zeta potential is equal to zero, the particles tend to agglomerate. This work focuses on the determination of the zeta potential of Sn, SAC305 and PbSn5Ag2.5 suspensions in isopropyl alcohol (IPA) through microelectrophoresis. The effect of acid, base and flux additives were studied. Results showed that the zeta potential of the solder suspensions are negative in pure IPA and charge reversal occurs in both acidic and basic region. In systems containing flux additives, the zeta potential of the suspensions is highly dependent on the type efflux. FTIR spectroscopy, conductivity measurement, and surface analysis was done in order to explain the observed electrokinetic behavior.
{"title":"Electrokinetic Behavior of Solder Powders in Non-aqueous Media","authors":"Terence Lucero F. Menor, M. Mena, H. Mendoza","doi":"10.1109/EPTC.2018.8654417","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654417","url":null,"abstract":"Solder paste dispensing is a key process in the electronics assembly. The increased global demand for smaller, lighter, faster and cheaper assemblies drives the electronics industry to use dispensers with finer apertures. However, reduction in the aperture size of dispensers faces the industry with increased clogging of dispensers and incomplete transfer of paste to the printed circuit board (PCB) pads. One factor contributing to the clogging of dispensers is the agglomeration of the solder powder suspensions which depends on the electrokinetic behavior of the particles. When suspensions are close to the point of no charge, wherein zeta potential is equal to zero, the particles tend to agglomerate. This work focuses on the determination of the zeta potential of Sn, SAC305 and PbSn5Ag2.5 suspensions in isopropyl alcohol (IPA) through microelectrophoresis. The effect of acid, base and flux additives were studied. Results showed that the zeta potential of the solder suspensions are negative in pure IPA and charge reversal occurs in both acidic and basic region. In systems containing flux additives, the zeta potential of the suspensions is highly dependent on the type efflux. FTIR spectroscopy, conductivity measurement, and surface analysis was done in order to explain the observed electrokinetic behavior.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132897845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654422
L. Bu, Hongyu Li, Xiaowu Zhang
A new architecture has been demonstrated for microfabricated ion traps, built around ceramic ball-grid array (BGA) connections. 56MHz RF frequency is applied to generate the electric field to trap the ions. The interposer is wirebonded to a Kyocera CPGA (Ceramic pin grid array) carrier for signal routing. As low temperature is favorable for ion trap chips, the material selection has to be done carefully in the present paper. Two kinds of materials, i.e., device passivation materials and die attach materials, are simulated and tested by the experiment. In the mechanical simulation, HD-4100 and HD8930 has lower mechanical stress. However, the short loop test reveals that almost all the bumps are detached from HD-4100 material and there are lots of unknown whiskers are founded after the samples are tested at 17K for 1 hour. Hence, SiO2 is still the first choice as passivation material in our process. For die attach materials, two kinds of material are evaluated in our experiment.
{"title":"Material Selection for Ion Trap Chip Working at Extreme Low Temperatures","authors":"L. Bu, Hongyu Li, Xiaowu Zhang","doi":"10.1109/EPTC.2018.8654422","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654422","url":null,"abstract":"A new architecture has been demonstrated for microfabricated ion traps, built around ceramic ball-grid array (BGA) connections. 56MHz RF frequency is applied to generate the electric field to trap the ions. The interposer is wirebonded to a Kyocera CPGA (Ceramic pin grid array) carrier for signal routing. As low temperature is favorable for ion trap chips, the material selection has to be done carefully in the present paper. Two kinds of materials, i.e., device passivation materials and die attach materials, are simulated and tested by the experiment. In the mechanical simulation, HD-4100 and HD8930 has lower mechanical stress. However, the short loop test reveals that almost all the bumps are detached from HD-4100 material and there are lots of unknown whiskers are founded after the samples are tested at 17K for 1 hour. Hence, SiO2 is still the first choice as passivation material in our process. For die attach materials, two kinds of material are evaluated in our experiment.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128129520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a feasible algorithm to automatic identify and classify the quality of bonding joint in wire bonding via machine learning, named as KPCA (Kernel Principal Analysis) and Random Forest. The result can be acceptable in calculation time and accuracy, which is possible to use as Feedback to control bonding parameters such as ultrasonic power and pressure, to strength the bonding reliability in production. First, the bonding joint images are mapped to a high dimension space, where KPCA is applied to decrease the image dimension for less calculation consumption and to eliminate high correlation features. The joint defect are then automatically identified and classified by Random Forest algorithm. Several strategies are adopted for improvement of accuracy. Our experiment result shows that the joint classification based on KPCA and Random Forest algorithm are better than conventional SVM and CNN algorithm on efficiency and accuracy.
本文提出了一种基于机器学习的自动识别和分类焊丝焊接接头质量的可行算法，称为KPCA (Kernel Principal Analysis)和随机森林。结果在计算时间和精度上均可接受，可作为反馈控制超声功率、压力等键合参数，提高生产中键合的可靠性。首先，将连接节点图像映射到高维空间，在高维空间中应用KPCA降低图像维数以减少计算量并消除高相关特征。然后采用随机森林算法对接头缺陷进行自动识别和分类。采用了几种策略来提高精度。实验结果表明，基于KPCA和随机森林算法的联合分类在效率和准确率上都优于传统的SVM和CNN算法。
{"title":"Joint Feature Classification for Wire Bond Joint Based on KPCA and Random Forest","authors":"Zhili Long, Xing Zhou, Xiaobing Zhang, Yuyang Yuan","doi":"10.1109/EPTC.2018.8654408","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654408","url":null,"abstract":"We present a feasible algorithm to automatic identify and classify the quality of bonding joint in wire bonding via machine learning, named as KPCA (Kernel Principal Analysis) and Random Forest. The result can be acceptable in calculation time and accuracy, which is possible to use as Feedback to control bonding parameters such as ultrasonic power and pressure, to strength the bonding reliability in production. First, the bonding joint images are mapped to a high dimension space, where KPCA is applied to decrease the image dimension for less calculation consumption and to eliminate high correlation features. The joint defect are then automatically identified and classified by Random Forest algorithm. Several strategies are adopted for improvement of accuracy. Our experiment result shows that the joint classification based on KPCA and Random Forest algorithm are better than conventional SVM and CNN algorithm on efficiency and accuracy.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"83 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131722864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654292
Chih-Sung Chen, N. Kao, P. Liao, Ssu-Cheng Lai, D. Jiang
Embedded trace substrate (ETS), like a typical build-up process that prepreg (PP) has been laminated on the copper trace patent, is a coreless substrate design for improvement both production yield and capability of substrate with finer line and space (L/S) dimension. The manufacturing process of ETS used an electrolytic copper plating method to form copper foil pattern coated on carrier board, and then multi-layers of ETS structure will duplicate the same process flow to been made, such as laser via drill, electro-less copper plating, dry-film lamination, exposure and development, next layer plating of copper pattern, stripping after removing carrier board, micro etching to enhance adhesion with solder mask, and metal treatment of surface finish after process of solder mask opening. Different to traditional build-up process, the trace width of ETS structure would not be attacked during process of micro etching, and the wall structure formed by dry-film between traces can prevent solder bridge problem of copper pillar bump during process of flip chip bond (FCB) [1]. Manufacturing process of ETS must go through a sequential high-temperature and -pressure step, thus the approach to construct a complex and detailed model is so far engineer’s objective for accurate prediction. When the assumption of stress-free at single curing temperature even though the chemical shrinkage has be considered is challenged, manufacturing temperature-independent model could not match well with experimental measurements because they don’t include an integrated processing modeling methodology. In particular, temperature-dependent material properties and different stress-free temperatures for different materials in the same model were considered in order to model the sequential steps during the sequential fabrication of high-density electronic packaging structures. However, the effort on fundamental study usually makes an impossible work due to time-and manpower-consuming, thus the mission has been transferred to construct an effective and simple approach on thermo-mechanical analysis. In this study, the material modeling has been simply constructed on elastically temperature-dependence for polymeric material utilized in packaging extensively. Furthermore, the innovative concept of conservation laws also has been developed on stress constitutive model; meanwhile, the creative ideology, such as cross-linking induced residual strain ($varepsilon_{mathrm {RS}}$) from compound forming and process-induced stress field, further has been embedded. Others, the experimental vehicles also have been performed for a reasonable simplification at single stress-free temperature of substrate, besides measurements were scheduled to confirm the accuracy on warpage. As comparison, these two different warpage modeling methodologies, including processing model and non-processing model, of an encapsulated integrated circuit (IC) package, associated with different schemes of a sequential manufa
{"title":"Processing Models Based on Stress Conservation Law Utilized for Temperature-Dependent Warpage Prediction of MUF FCCSP with 3L ETS","authors":"Chih-Sung Chen, N. Kao, P. Liao, Ssu-Cheng Lai, D. Jiang","doi":"10.1109/EPTC.2018.8654292","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654292","url":null,"abstract":"Embedded trace substrate (ETS), like a typical build-up process that prepreg (PP) has been laminated on the copper trace patent, is a coreless substrate design for improvement both production yield and capability of substrate with finer line and space (L/S) dimension. The manufacturing process of ETS used an electrolytic copper plating method to form copper foil pattern coated on carrier board, and then multi-layers of ETS structure will duplicate the same process flow to been made, such as laser via drill, electro-less copper plating, dry-film lamination, exposure and development, next layer plating of copper pattern, stripping after removing carrier board, micro etching to enhance adhesion with solder mask, and metal treatment of surface finish after process of solder mask opening. Different to traditional build-up process, the trace width of ETS structure would not be attacked during process of micro etching, and the wall structure formed by dry-film between traces can prevent solder bridge problem of copper pillar bump during process of flip chip bond (FCB) [1]. Manufacturing process of ETS must go through a sequential high-temperature and -pressure step, thus the approach to construct a complex and detailed model is so far engineer’s objective for accurate prediction. When the assumption of stress-free at single curing temperature even though the chemical shrinkage has be considered is challenged, manufacturing temperature-independent model could not match well with experimental measurements because they don’t include an integrated processing modeling methodology. In particular, temperature-dependent material properties and different stress-free temperatures for different materials in the same model were considered in order to model the sequential steps during the sequential fabrication of high-density electronic packaging structures. However, the effort on fundamental study usually makes an impossible work due to time-and manpower-consuming, thus the mission has been transferred to construct an effective and simple approach on thermo-mechanical analysis. In this study, the material modeling has been simply constructed on elastically temperature-dependence for polymeric material utilized in packaging extensively. Furthermore, the innovative concept of conservation laws also has been developed on stress constitutive model; meanwhile, the creative ideology, such as cross-linking induced residual strain ($varepsilon_{mathrm {RS}}$) from compound forming and process-induced stress field, further has been embedded. Others, the experimental vehicles also have been performed for a reasonable simplification at single stress-free temperature of substrate, besides measurements were scheduled to confirm the accuracy on warpage. As comparison, these two different warpage modeling methodologies, including processing model and non-processing model, of an encapsulated integrated circuit (IC) package, associated with different schemes of a sequential manufa","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134170478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As the copper pillar bumps with fine pitch and high density were widely applied in high I/O interconnection packaging. It’s increasingly important to study the effect of bonding properties of copper pillar bumps for different morphology and interconnection methods. In the paper, we designed Test Vehicle of copper pillar bumps and manufacture $30 mu mathrm{m}$ pitch copper pillar bumps for verifying the bonding effect between copper pillar bumps. We compared the bonding experiments of copper pillar bumps of different exterior morphology and different bonding methods. Finally, using the four-probe method to test the resistance of the bonded bumps and the bonding yield of partial micro bumps can roughly be evaluated by has been designed daisy chain structure.
由于铜柱凸点具有细间距和高密度的特点，在高I/O互连封装中得到了广泛的应用。研究不同形貌和连接方式对铜柱凸点连接性能的影响显得越来越重要。本文设计了铜柱凸架试验车，制作了$30 mu mathm {m}$节距铜柱凸架，验证了铜柱凸架之间的粘结效果。比较了不同外部形貌和不同连接方式的铜柱凸点的连接实验。最后，利用四探针法测试了粘结凸点的电阻，通过设计的菊花链结构可以大致评价局部微凸点的粘结成品率。
{"title":"Research on the effect of bonding properties of micro bumps for different morphology and interconnection methods","authors":"Fengwei Dai, David-Wei Zhang, Guojun Wang, Dengfen Yang, Wenqi Zhang, Liqiang Cao","doi":"10.1109/EPTC.2018.8654346","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654346","url":null,"abstract":"As the copper pillar bumps with fine pitch and high density were widely applied in high I/O interconnection packaging. It’s increasingly important to study the effect of bonding properties of copper pillar bumps for different morphology and interconnection methods. In the paper, we designed Test Vehicle of copper pillar bumps and manufacture $30 mu mathrm{m}$ pitch copper pillar bumps for verifying the bonding effect between copper pillar bumps. We compared the bonding experiments of copper pillar bumps of different exterior morphology and different bonding methods. Finally, using the four-probe method to test the resistance of the bonded bumps and the bonding yield of partial micro bumps can roughly be evaluated by has been designed daisy chain structure.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"29 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131830096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654418
N. Subbiah, Qingming Feng, K. Ramirez, J. Wilde, G. Bruckner
Pressure sensors working at high temperatures of $500 ^{circ}C$ are required in various fields like aerospace, automobile and many industries. However, reliable sensors working at such high temperature are still not sufficiently developed. Mainly, developing a high temperature stable package imposes new challenges due to thermal cross-sensitivity and temperature induced stresses. Other major issues are to identify stable materials for high temperatures and stress-tolerant sensor mounting techniques. This research work focuses on the implementation of a stress-tolerant pressure sensor design for applications up to $500 ^{circ}C$: A micro strain gauge is deposited and patterned on a Langasite (LGS) crystal. It is attached to a ceramic substrate Al2O3 like a cantilever by flip-chip interconnection and glass solder underfill. The flip-chip bonding is done using gold stud bumps. The ceramic substrate has a membrane structure which is fabricated by ultrasonic machining. The deflection of the deforming membrane will be transferred pointwise to the free end of the crystal inside the package. The strain induced on the cantilever is measured by the change of resistance of a microstrain gauge. This special design concept aims at the elimination of thermal stresses between membrane and sensing device, which could induce cross-sensitivity. In this paper, processes to develop the complete assembly are presented including the choice of materials and fabrication methodology for individual parts. The resulting sensor package is stable for operations up to $500 ^{circ}C$.
{"title":"Implementation of High-Temperature Pressure Sensor Package and Characterization up to 500°C","authors":"N. Subbiah, Qingming Feng, K. Ramirez, J. Wilde, G. Bruckner","doi":"10.1109/EPTC.2018.8654418","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654418","url":null,"abstract":"Pressure sensors working at high temperatures of $500 ^{circ}C$ are required in various fields like aerospace, automobile and many industries. However, reliable sensors working at such high temperature are still not sufficiently developed. Mainly, developing a high temperature stable package imposes new challenges due to thermal cross-sensitivity and temperature induced stresses. Other major issues are to identify stable materials for high temperatures and stress-tolerant sensor mounting techniques. This research work focuses on the implementation of a stress-tolerant pressure sensor design for applications up to $500 ^{circ}C$: A micro strain gauge is deposited and patterned on a Langasite (LGS) crystal. It is attached to a ceramic substrate Al2O3 like a cantilever by flip-chip interconnection and glass solder underfill. The flip-chip bonding is done using gold stud bumps. The ceramic substrate has a membrane structure which is fabricated by ultrasonic machining. The deflection of the deforming membrane will be transferred pointwise to the free end of the crystal inside the package. The strain induced on the cantilever is measured by the change of resistance of a microstrain gauge. This special design concept aims at the elimination of thermal stresses between membrane and sensing device, which could induce cross-sensitivity. In this paper, processes to develop the complete assembly are presented including the choice of materials and fabrication methodology for individual parts. The resulting sensor package is stable for operations up to $500 ^{circ}C$.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"61 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113977242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654389
W. Loh, Qin Ren
In this paper, Through Silicon Via (TSV) of Silicon on isolator (SOI) platform on via last wafer integration challenges were evaluated. TSV profile at Buried Oxide (BOX) and bulk Silicon of SOI substrates undercut improvement was assessed. Electroplating (ECP) TSV wafer uniformity and its impact on Chemical Mechanical Polishing (CMP) was discussed. Improvement in Electroplating wafer uniformity has shown significant improvement in CMP remaining oxide uniformity.
{"title":"EPIC Via Last on SOI Wafer Integration Challenges","authors":"W. Loh, Qin Ren","doi":"10.1109/EPTC.2018.8654389","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654389","url":null,"abstract":"In this paper, Through Silicon Via (TSV) of Silicon on isolator (SOI) platform on via last wafer integration challenges were evaluated. TSV profile at Buried Oxide (BOX) and bulk Silicon of SOI substrates undercut improvement was assessed. Electroplating (ECP) TSV wafer uniformity and its impact on Chemical Mechanical Polishing (CMP) was discussed. Improvement in Electroplating wafer uniformity has shown significant improvement in CMP remaining oxide uniformity.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"19 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114046465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654300
C. Cavaco, Konstantinos Chatzinis, Bert van Lijnschoten, S. Guerrieri
In this paper is reported for the first-time wafer level electrical data on 200 mm wafer to wafer hybrid copper to dielectric bonding at low temperature, using SiN as the dielectric material. In this work was used up to five metal levels per wafer. SiN is here investigated for its feasibility to replace SiOx or SiCN in the hybrid bonding. Furthermore, for the first-time reliability testing is here reported when using either SiN or SiOx as the dielectric layer.
{"title":"Hybrid Cu-SiN and Cu-SiOx Direct Bonding of 200 MM CMOS Wafers with Five Metal Levels: Morphological, Electrical and Reliability Characterization","authors":"C. Cavaco, Konstantinos Chatzinis, Bert van Lijnschoten, S. Guerrieri","doi":"10.1109/EPTC.2018.8654300","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654300","url":null,"abstract":"In this paper is reported for the first-time wafer level electrical data on 200 mm wafer to wafer hybrid copper to dielectric bonding at low temperature, using SiN as the dielectric material. In this work was used up to five metal levels per wafer. SiN is here investigated for its feasibility to replace SiOx or SiCN in the hybrid bonding. Furthermore, for the first-time reliability testing is here reported when using either SiN or SiOx as the dielectric layer.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127963932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654345
Haiyan Liu, Xiangyang Li, Sean Xu, Jun Li
Converting gold wire to copper wire for IC packaging is a big trend recently which has both advantage and disadvantage. Cu wire is good for packaging cost saving to current semiconductor industry, but it may also create quality and reliability issues. Since Cu is much harder and stiffer material than Au, it may require a greater force and USG power to insure good bonding to pad, and a larger bond force and USG power in turn increases the risk of ILD crack during the bonding process. The wafer tech in this study is CMOS40nm, Al thickness is 28KA, with 53um pad opening. The ILD crack mechanism which is discussed in this paper is different. The failure mode during ATE test is leakage failure. After de-cap and cratering test, there is no cratering / damage on failed pad under microscope check. FIB was performed on failed pad and confirmed the damage between Metal 2 and Metal 3, and no damage on top metal. The link between IV curve trace and ILD crack was studied. The root cause of the ILD crack was studied, material and machine variation were also take into consideration. Parameter optimization DOE was done. Key wire bond parameters include the initial force, USG power etc. The wire pull, ball shear, IMC, Al remnant etc. are key response. The result shows that lower USG and higher initial force can get better wire bond performance. The die was packaged into a MAPBGA package. Electrical test was performed on the assembled parts at T0, post MSL3/260degree C, post 264h UHST $(110 ^{circ}mathrm{C} /85$%RH), and post TC700cycles ($- 55 ^{circ}mathrm{C}$ to $150 ^{circ}mathrm{C})$. All units post stress clean passed without any failure. The overall leakage failure rate at ATE test is reduced.
{"title":"A New Failure Mechanism of Inter Layer Dielectric Crack","authors":"Haiyan Liu, Xiangyang Li, Sean Xu, Jun Li","doi":"10.1109/EPTC.2018.8654345","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654345","url":null,"abstract":"Converting gold wire to copper wire for IC packaging is a big trend recently which has both advantage and disadvantage. Cu wire is good for packaging cost saving to current semiconductor industry, but it may also create quality and reliability issues. Since Cu is much harder and stiffer material than Au, it may require a greater force and USG power to insure good bonding to pad, and a larger bond force and USG power in turn increases the risk of ILD crack during the bonding process. The wafer tech in this study is CMOS40nm, Al thickness is 28KA, with 53um pad opening. The ILD crack mechanism which is discussed in this paper is different. The failure mode during ATE test is leakage failure. After de-cap and cratering test, there is no cratering / damage on failed pad under microscope check. FIB was performed on failed pad and confirmed the damage between Metal 2 and Metal 3, and no damage on top metal. The link between IV curve trace and ILD crack was studied. The root cause of the ILD crack was studied, material and machine variation were also take into consideration. Parameter optimization DOE was done. Key wire bond parameters include the initial force, USG power etc. The wire pull, ball shear, IMC, Al remnant etc. are key response. The result shows that lower USG and higher initial force can get better wire bond performance. The die was packaged into a MAPBGA package. Electrical test was performed on the assembled parts at T0, post MSL3/260degree C, post 264h UHST $(110 ^{circ}mathrm{C} /85$%RH), and post TC700cycles ($- 55 ^{circ}mathrm{C}$ to $150 ^{circ}mathrm{C})$. All units post stress clean passed without any failure. The overall leakage failure rate at ATE test is reduced.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129197770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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