Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654289
Gilho Hwang, Hsiao Hsiang-Yao, D. Wee
In this study, stepwise current was used for TSV Cu electroplating. TSV with void defect and solid filled TSV showed different voltage behavior at low current density. Based on voltage behavior of stepwise current electroplating and linear current sweep, TSV Cu electroplating process was optimized and stable solid TSV filling was achieved without any defect.
{"title":"Study on bottom-up Cu filling process for Through Silicon Via (TSV) metallization","authors":"Gilho Hwang, Hsiao Hsiang-Yao, D. Wee","doi":"10.1109/EPTC.2018.8654289","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654289","url":null,"abstract":"In this study, stepwise current was used for TSV Cu electroplating. TSV with void defect and solid filled TSV showed different voltage behavior at low current density. Based on voltage behavior of stepwise current electroplating and linear current sweep, TSV Cu electroplating process was optimized and stable solid TSV filling was achieved without any defect.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129663932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654264
Zhaohui Chen, Xiaowu Zhang, S. Lim, S. Lim, B. L. Lau, Yong Han, M. C. Jong, Songlin Liu, Xiaobai Wang, Y. Andriani
In this paper, the package level warpage of different package sizes of mold-first and redistribution layer-first (RDL-first) Fan-out wafer level package (FOWLP) with single chip was studied by finite element simulation considering viscoelastic material properties of epoxy molding compound (EMC), dielectric and underfill. Package level warpage at high temperature is underestimated for mold-first/RDL-first FOWLP with elastic material properties of EMC, dielectric and underfill. The package warpage changing before and after reflow can be captured with viscoelastic material properties. Package level warpage increases with the package size. Warpage of RDL-first FOWLP is larger than that of mold-first FOWLP with same package thickness of $200 mu mathrm{m}$ which is caused by the stiffness reduction due to thinner silicon chip and additional CTE mismatch of underfill/micro-bump layer. Package level warpage of mold-first and RDL-first FOWLP reduces with increasing of package thickness. Thickness of mold-first and RDL-first FOWLP was determined in order to meet the target of within $pm 100 mu mathrm{m}$ warpage during reflow process required by the JEITA ED7306 standard of $250 mu mathrm{m}$ diameter solder joint with $400 mu mathrm{m}$ pitch.
本文采用有限元模拟方法，研究了单芯片模优先和重分布层优先(RDL-first)扇形外圆片级封装(FOWLP)不同封装尺寸的封装翘曲问题，并考虑了环氧模复合材料(EMC)、介电介质和下填料的粘弹性材料特性。具有电磁兼容、介电和下填料弹性材料特性的模具优先/ rdl优先FOWLP在高温下低估了封装级翘曲。利用粘弹性材料特性可以捕捉回流前后包装翘曲的变化。包层翘曲随包的大小而增加。相同封装厚度$200 mu mathm {m}$时，RDL-first FOWLP的翘曲量大于模具-first FOWLP，这是由于硅片变薄导致刚度降低以及下填充层/微凹凸层CTE的额外失配造成的。模具优先和rdl优先的FOWLP随包装厚度的增加而减小。为了满足JEITA ED7306标准中直径为250 mu mathm {m}$、节距为400 mu mathm {m}$的焊点在回流过程中翘曲量在$pm 100 mu mathm {m}$的要求，确定了模具优先和rdl优先的FOWLP厚度。
{"title":"Package Level Warpage Simulation of Fan-out Wafer Level Package (FOWLP) Considering Viscoelastic Material Properties","authors":"Zhaohui Chen, Xiaowu Zhang, S. Lim, S. Lim, B. L. Lau, Yong Han, M. C. Jong, Songlin Liu, Xiaobai Wang, Y. Andriani","doi":"10.1109/EPTC.2018.8654264","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654264","url":null,"abstract":"In this paper, the package level warpage of different package sizes of mold-first and redistribution layer-first (RDL-first) Fan-out wafer level package (FOWLP) with single chip was studied by finite element simulation considering viscoelastic material properties of epoxy molding compound (EMC), dielectric and underfill. Package level warpage at high temperature is underestimated for mold-first/RDL-first FOWLP with elastic material properties of EMC, dielectric and underfill. The package warpage changing before and after reflow can be captured with viscoelastic material properties. Package level warpage increases with the package size. Warpage of RDL-first FOWLP is larger than that of mold-first FOWLP with same package thickness of $200 mu mathrm{m}$ which is caused by the stiffness reduction due to thinner silicon chip and additional CTE mismatch of underfill/micro-bump layer. Package level warpage of mold-first and RDL-first FOWLP reduces with increasing of package thickness. Thickness of mold-first and RDL-first FOWLP was determined in order to meet the target of within $pm 100 mu mathrm{m}$ warpage during reflow process required by the JEITA ED7306 standard of $250 mu mathrm{m}$ diameter solder joint with $400 mu mathrm{m}$ pitch.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126908508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654432
C. H. Kumar, Satish Bonam, S. Vanjari, S. Singh
The solder is the one of the most interconnect joining material in the denser electronic interconnects. To follow the paradigm, shift towards the Moor’s law, an advanced electronic industry motivated towards the vertical integration of multifunctioning dies. Here the solder is used to connect the dies vertically and also at the packaging level, i.e. Die to PCB (printed circuit board) or silicon interposer. The reliability and electromigration issues of solder, when interconnect dimensions become smaller. This makes the way for involvement of new materials at the die interconnections and at the package level. In this work, the direct bonding of metal alloy (Cu-Cr (0.6 to 1.2% of Cr), which is not only resistive to surface oxidation but also a highly conductive material is proposed. A novel bonding approach which helped in achieving good bonding quality at low temperature and pressure, by creating a density variation in thin film of alloy on silicon substrate. By adjusting the deposition parameters while sputtering, we have created density variation in thin film of Cu-Cr alloy on silicon substrate. Then applied higher temperature to a substrate having high density thin film of Cu-Cr and low temperature to low density varied substrate while performing bonding the used high temperature is $190^{circ}mathrm{C}$ with gradient of $30^{o}mathrm{C}$ for other substrate and applied pressure is $sim$0.5 MPa for 40 min. The density variation was verified in terms of bond shear strength analysis. we observed the bonding interfacial quality using cross sectional - FESEM and bonding interfacial strength by manually breaking by diamond cutter and sharp blade insertion. High bonding interfacial strength of $sim$70 MPa, is obtained with proposed bonding method is higher than conventional methodology by $sim$20 MPa. Using these bonding conditions, we achieved the fine pitch bonding of $10 mu mathrm{m}$ features, inspected using IR imaging. The proposed novel methods maybe useful for achieving high density 3D interconnects both at chip and package level, immaterial of the surface roughness of the thin films.
焊料是高密度电子互连中最常用的互连材料之一。为了遵循范式，转向摩尔定律，一个先进的电子工业朝着多功能模具的垂直整合发展。在这里，焊料用于垂直连接模具，也用于封装层，即模具到PCB(印刷电路板)或硅中间层。当互连尺寸变小时，焊料的可靠性和电迁移问题。这使得新材料在模具互连和封装层面的参与。在本工作中，直接键合金属合金(Cu-Cr (0.6 ～ 1.2)% of Cr), which is not only resistive to surface oxidation but also a highly conductive material is proposed. A novel bonding approach which helped in achieving good bonding quality at low temperature and pressure, by creating a density variation in thin film of alloy on silicon substrate. By adjusting the deposition parameters while sputtering, we have created density variation in thin film of Cu-Cr alloy on silicon substrate. Then applied higher temperature to a substrate having high density thin film of Cu-Cr and low temperature to low density varied substrate while performing bonding the used high temperature is $190^{circ}mathrm{C}$ with gradient of $30^{o}mathrm{C}$ for other substrate and applied pressure is $sim$0.5 MPa for 40 min. The density variation was verified in terms of bond shear strength analysis. we observed the bonding interfacial quality using cross sectional - FESEM and bonding interfacial strength by manually breaking by diamond cutter and sharp blade insertion. High bonding interfacial strength of $sim$70 MPa, is obtained with proposed bonding method is higher than conventional methodology by $sim$20 MPa. Using these bonding conditions, we achieved the fine pitch bonding of $10 mu mathrm{m}$ features, inspected using IR imaging. The proposed novel methods maybe useful for achieving high density 3D interconnects both at chip and package level, immaterial of the surface roughness of the thin films.
{"title":"High Density metal alloy Interconnections Using Novel Wafer Bonding Approach For 3D IC Packaging Applications","authors":"C. H. Kumar, Satish Bonam, S. Vanjari, S. Singh","doi":"10.1109/EPTC.2018.8654432","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654432","url":null,"abstract":"The solder is the one of the most interconnect joining material in the denser electronic interconnects. To follow the paradigm, shift towards the Moor’s law, an advanced electronic industry motivated towards the vertical integration of multifunctioning dies. Here the solder is used to connect the dies vertically and also at the packaging level, i.e. Die to PCB (printed circuit board) or silicon interposer. The reliability and electromigration issues of solder, when interconnect dimensions become smaller. This makes the way for involvement of new materials at the die interconnections and at the package level. In this work, the direct bonding of metal alloy (Cu-Cr (0.6 to 1.2% of Cr), which is not only resistive to surface oxidation but also a highly conductive material is proposed. A novel bonding approach which helped in achieving good bonding quality at low temperature and pressure, by creating a density variation in thin film of alloy on silicon substrate. By adjusting the deposition parameters while sputtering, we have created density variation in thin film of Cu-Cr alloy on silicon substrate. Then applied higher temperature to a substrate having high density thin film of Cu-Cr and low temperature to low density varied substrate while performing bonding the used high temperature is $190^{circ}mathrm{C}$ with gradient of $30^{o}mathrm{C}$ for other substrate and applied pressure is $sim$0.5 MPa for 40 min. The density variation was verified in terms of bond shear strength analysis. we observed the bonding interfacial quality using cross sectional - FESEM and bonding interfacial strength by manually breaking by diamond cutter and sharp blade insertion. High bonding interfacial strength of $sim$70 MPa, is obtained with proposed bonding method is higher than conventional methodology by $sim$20 MPa. Using these bonding conditions, we achieved the fine pitch bonding of $10 mu mathrm{m}$ features, inspected using IR imaging. The proposed novel methods maybe useful for achieving high density 3D interconnects both at chip and package level, immaterial of the surface roughness of the thin films.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121167636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654378
Low Suat-Mooi, Guo Fei, Wong Wui-Weng
This paper discusses low impedance characterization techniques used for power delivery network (PDN) in today's high-performance digital systems. More importantly, sensitivity analysis is presented to study impact of measurement accuracy against landing locations of probes onto a flip chip package and more specifically relative distance between two micro-probes in S21 measurements by vector network analyzer (VNA). Milliohms impedances across wide bandwidth, from approximately DC to GHz frequency range, can be measured accurately and well-correlated with simulation data on a microprocessor micro PGA substrate sitting in a socket mounted onto a printed circuit board (PCB) with cutting edge design of capacitive decoupling scheme. Conventionally, transfer-impedance obtained by two-port VNA measurement is used for PDN characterization. Being challenged by accessibility of test points in a complex package and board design, closely landing of the two micro-probes onto C4 pads would induce unwanted measurement noise caused by inductive coupling while excessive distance between the two micro-probes would result into artificial low impedance caused by parasitic inductance in the power planes of the package. Cautious arrangement of probing scheme in measurement that mimic to port setting in simulation is crucial in low impedance characterization of PDN at frequency range of interested. The accuracy of this low impedance characterization with optimized probing locations is verified by analytic calculation and simulation
{"title":"Impedance Characterization of Power Delivery Network in a Flip Chip Package on a Printed Circuit Board","authors":"Low Suat-Mooi, Guo Fei, Wong Wui-Weng","doi":"10.1109/EPTC.2018.8654378","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654378","url":null,"abstract":"This paper discusses low impedance characterization techniques used for power delivery network (PDN) in today's high-performance digital systems. More importantly, sensitivity analysis is presented to study impact of measurement accuracy against landing locations of probes onto a flip chip package and more specifically relative distance between two micro-probes in S21 measurements by vector network analyzer (VNA). Milliohms impedances across wide bandwidth, from approximately DC to GHz frequency range, can be measured accurately and well-correlated with simulation data on a microprocessor micro PGA substrate sitting in a socket mounted onto a printed circuit board (PCB) with cutting edge design of capacitive decoupling scheme. Conventionally, transfer-impedance obtained by two-port VNA measurement is used for PDN characterization. Being challenged by accessibility of test points in a complex package and board design, closely landing of the two micro-probes onto C4 pads would induce unwanted measurement noise caused by inductive coupling while excessive distance between the two micro-probes would result into artificial low impedance caused by parasitic inductance in the power planes of the package. Cautious arrangement of probing scheme in measurement that mimic to port setting in simulation is crucial in low impedance characterization of PDN at frequency range of interested. The accuracy of this low impedance characterization with optimized probing locations is verified by analytic calculation and simulation","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121382168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654358
L. Y. Lim, Yao-Huang Huang
Copper Pillar bump Flipchip in the key solution in providing the breakthrough in package size reduction, lower cost package and better product performance. However there are challenges in creating a reliable copper pillar bump. Proper choice of electroplating materials and process are critical in meeting the design goals, quality and reliability. During a qualification run on a copper pillar bump flipchip on a thin small no lead package, excessive Kirkendall voids growth was found in the copper and SnAg (Tin-sliver) layer after 1000 hours of High Temperature storage at 150 deg C and 1000 cycles temperature cycle from −55°C to 150°. Methodologies like 8D, fishbone diagram and 5 why are used to investigate the root cause of this abnormality formation and deriving a robust solution to resolve the issue. The Investigation include evaluation of 2 different plating chemical and the plating parameter optimization with some improvement on the current copper pillar bump stack up. The evaluation will further validate by HTSL 175 deg C for 168 hours and X-ray and X-sectional analysis of packages.
{"title":"Kirkendall Voids Improvement in Thin Small No Lead Package","authors":"L. Y. Lim, Yao-Huang Huang","doi":"10.1109/EPTC.2018.8654358","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654358","url":null,"abstract":"Copper Pillar bump Flipchip in the key solution in providing the breakthrough in package size reduction, lower cost package and better product performance. However there are challenges in creating a reliable copper pillar bump. Proper choice of electroplating materials and process are critical in meeting the design goals, quality and reliability. During a qualification run on a copper pillar bump flipchip on a thin small no lead package, excessive Kirkendall voids growth was found in the copper and SnAg (Tin-sliver) layer after 1000 hours of High Temperature storage at 150 deg C and 1000 cycles temperature cycle from −55°C to 150°. Methodologies like 8D, fishbone diagram and 5 why are used to investigate the root cause of this abnormality formation and deriving a robust solution to resolve the issue. The Investigation include evaluation of 2 different plating chemical and the plating parameter optimization with some improvement on the current copper pillar bump stack up. The evaluation will further validate by HTSL 175 deg C for 168 hours and X-ray and X-sectional analysis of packages.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"11 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113941647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654412
J. Ooi, T. Mori, Hiroyuki Tsuritani, T. Sayama, Y. Okamoto, M. Hoshino, K. Uesugi
In this study, in order to evaluate the fatigue crack propagation in solder joints of printed circuit boards (PCBs) under a condition close to the actual temperature change and distribution, a die-attached-type specimen that generates heat owing to energization was fabricated. Subsequently, synchrotron radiation X-ray laminography was employed to observe the fatigue crack propagation process. The specimens included a typical die-attached joint structure, in which five square Al2O3 ceramic dies of side 3 mm are mounted in a cross shape at intervals of 2 mm and in the center position of a square FR-4 substrate of side 40 mm, and subsequently joined by Sn-3.0Ag-0.5Cu solder layers. The following results were obtained. First, the image quality of laminography was evaluated by comparing the obtained laminography images with scanning electron microscope (SEM) images of the same cross-section of the specimen. In the specimen, it was possible to observe cracks with an opening over several micrometers using the laminography system. In addition, a verification test was conducted to determine whether in situ observation is possible while applying thermal load via energization. Consequently, through continuous monitoring of the same position in the same specimen, it was confirmed that the quality of the obtained laminography image in the specimen undergoing energization was equivalent to that in a non energization state, provided that the temperature of the specimen was stable after sufficient time had passed. Subsequently, to observe and quantify the thermal fatigue crack propagation process, a thermal cyclic loading was applied to the specimen, laminography images were obtained at arbitrary number of cycles, and the cross-sectional area of the cracks was measured. It was observed that the crosssectional area of the cracks increases linearly as the number of cycles increases, and that the average crack growth rate can also be calculated. This will make it possible to estimate the life time of the fatigue cracks generated in solder joints. Finally, for comparison, other die-attached specimens were loaded through thermal cycle tests under accelerated conditions using a thermal shock chamber, which are more severe than the energization test. However, even after the thermal cycle proceeded, there was hardly any change in the laminography images, and no evidence of fatigue crack propagation at the solder joint could be confirmed. The images suggested that interfacial delamination may occur at some boundaries, and this was confirmed through SEM observations of the same specimen.
{"title":"Evaluation of Thermal Crack Propagation in Die-attached Joints Due to Cyclic Energization by Synchrotron Radiation Laminography Monitoring","authors":"J. Ooi, T. Mori, Hiroyuki Tsuritani, T. Sayama, Y. Okamoto, M. Hoshino, K. Uesugi","doi":"10.1109/EPTC.2018.8654412","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654412","url":null,"abstract":"In this study, in order to evaluate the fatigue crack propagation in solder joints of printed circuit boards (PCBs) under a condition close to the actual temperature change and distribution, a die-attached-type specimen that generates heat owing to energization was fabricated. Subsequently, synchrotron radiation X-ray laminography was employed to observe the fatigue crack propagation process. The specimens included a typical die-attached joint structure, in which five square Al2O3 ceramic dies of side 3 mm are mounted in a cross shape at intervals of 2 mm and in the center position of a square FR-4 substrate of side 40 mm, and subsequently joined by Sn-3.0Ag-0.5Cu solder layers. The following results were obtained. First, the image quality of laminography was evaluated by comparing the obtained laminography images with scanning electron microscope (SEM) images of the same cross-section of the specimen. In the specimen, it was possible to observe cracks with an opening over several micrometers using the laminography system. In addition, a verification test was conducted to determine whether in situ observation is possible while applying thermal load via energization. Consequently, through continuous monitoring of the same position in the same specimen, it was confirmed that the quality of the obtained laminography image in the specimen undergoing energization was equivalent to that in a non energization state, provided that the temperature of the specimen was stable after sufficient time had passed. Subsequently, to observe and quantify the thermal fatigue crack propagation process, a thermal cyclic loading was applied to the specimen, laminography images were obtained at arbitrary number of cycles, and the cross-sectional area of the cracks was measured. It was observed that the crosssectional area of the cracks increases linearly as the number of cycles increases, and that the average crack growth rate can also be calculated. This will make it possible to estimate the life time of the fatigue cracks generated in solder joints. Finally, for comparison, other die-attached specimens were loaded through thermal cycle tests under accelerated conditions using a thermal shock chamber, which are more severe than the energization test. However, even after the thermal cycle proceeded, there was hardly any change in the laminography images, and no evidence of fatigue crack propagation at the solder joint could be confirmed. The images suggested that interfacial delamination may occur at some boundaries, and this was confirmed through SEM observations of the same specimen.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127986089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654297
Meiying Su, Cheng Chen, Minghao Zhou, Jun Li, Liqiang Cao
In the study, warpage as a serious problem need to be investigated for large size TSV interposer package technology. The most important task for TSV interposer package is to discuss the warpage influence on some critical assembly processes. In the paper, two kinds of assembly processes were described in detail: one is based on strip-level assembly processes, the other is based on individual package-level one. By using finite element method, warpage simulation results were analyzed for TSV interposer attach, die attach, stiffener attach, etc. Besides, board-level lifetime prediction under the harsh TC condition (−65 °C ~ 150 °C) was investigated in the study based on Darveaux’s model of strain energy density.
{"title":"Warpage Prediction and Lifetime Analysis for Large Size Through-silicon-via (TSV) Interposer Package","authors":"Meiying Su, Cheng Chen, Minghao Zhou, Jun Li, Liqiang Cao","doi":"10.1109/EPTC.2018.8654297","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654297","url":null,"abstract":"In the study, warpage as a serious problem need to be investigated for large size TSV interposer package technology. The most important task for TSV interposer package is to discuss the warpage influence on some critical assembly processes. In the paper, two kinds of assembly processes were described in detail: one is based on strip-level assembly processes, the other is based on individual package-level one. By using finite element method, warpage simulation results were analyzed for TSV interposer attach, die attach, stiffener attach, etc. Besides, board-level lifetime prediction under the harsh TC condition (−65 °C ~ 150 °C) was investigated in the study based on Darveaux’s model of strain energy density.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132232796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654404
Ly May Chew, W. Schmitt, M. Dubis
Owing to its superb properties such as high melting temperature, high thermal and electrical conductivity, silver sintering is considered as a promising die attach technology in recent years for high power electronics packaging with demanding requirements such as high power density, high current capacity and high operating temperature. Our previous studies have demonstrated the feasibility of semiconductor devices attachment on silver, gold and copper surfaces by silver sintering. Eliminating precious metal finishing on substrate would represent significant compatibility to present supply chain and lower the entry barrier to adopt silver sinter solution. In this paper, we extended our study to semiconductor devices attachment on non-precious metal surfaces by pressure sintering process in air atmosphere. We attached Ag metallized Si dies on direct copper bonding substrates with nickel plated and without plating as well as on aluminum plate by silver sintering process at $250^{circ}mathrm{C}$ with a pressure of 10 MPa for 3 min using a newly developed silver sinter paste. We demonstrate that it is feasible to create high bonding strength of silver sintered joint on Ni, Al and Cu surfaces with an average die shear strength above 15 N/mm$^{2}$. The die shear failure mode shows that cohesive break in the sintered layer was obtained for all the samples. SEM-EDX results further confirmed that silver sintered joint was formed on Ni, Al and Cu surfaces with an interdiffusion between Ag and Ni, Ag and Al as well as Ag and Cu. SAM was performed on the samples after pressure sintering and the SAM images clearly illustrate that void, drying channel and delamination in the silver sintered layer were not observed.
{"title":"High bonding strength of silver sintered joints on non-precious metal surfaces by pressure sintering under air atmosphere using micro-silver sinter paste","authors":"Ly May Chew, W. Schmitt, M. Dubis","doi":"10.1109/EPTC.2018.8654404","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654404","url":null,"abstract":"Owing to its superb properties such as high melting temperature, high thermal and electrical conductivity, silver sintering is considered as a promising die attach technology in recent years for high power electronics packaging with demanding requirements such as high power density, high current capacity and high operating temperature. Our previous studies have demonstrated the feasibility of semiconductor devices attachment on silver, gold and copper surfaces by silver sintering. Eliminating precious metal finishing on substrate would represent significant compatibility to present supply chain and lower the entry barrier to adopt silver sinter solution. In this paper, we extended our study to semiconductor devices attachment on non-precious metal surfaces by pressure sintering process in air atmosphere. We attached Ag metallized Si dies on direct copper bonding substrates with nickel plated and without plating as well as on aluminum plate by silver sintering process at $250^{circ}mathrm{C}$ with a pressure of 10 MPa for 3 min using a newly developed silver sinter paste. We demonstrate that it is feasible to create high bonding strength of silver sintered joint on Ni, Al and Cu surfaces with an average die shear strength above 15 N/mm$^{2}$. The die shear failure mode shows that cohesive break in the sintered layer was obtained for all the samples. SEM-EDX results further confirmed that silver sintered joint was formed on Ni, Al and Cu surfaces with an interdiffusion between Ag and Ni, Ag and Al as well as Ag and Cu. SAM was performed on the samples after pressure sintering and the SAM images clearly illustrate that void, drying channel and delamination in the silver sintered layer were not observed.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130081952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654374
Tianqing Wu, P. Lee, J. Mathew, SiuMing Lu
In recent years, there is an increasing need for better cooling solutions to maintain a uniform and low temperature in high power density electronic devices. With much research effort devoted to it, pool boiling has been identified as a promising method to remove heat with less moving parts and high efficiency. The phase change during pool boiling can absorb large amount of heat and the nucleating bubbles can evacuate into the liquid pool automatically due to buoyance force, thereby assuring liquid rewetting of the heat sink surface and lower its working temperature. For the utilization of pool boiling heat sinks in industries like power generation plants, data centers and military systems, heat sinks are expected to operate consistently with high performance. Therefore, the effect of aging on heat sink performance needs to be evaluated closely. In this study, pool boiling experiments have been conducted with plain and finned heat sinks each for several times with a certain gap up to the highest heat flux and the ageing problem have been examined for the influence in heat transfer performance and heat sink surface characteristics. The main reasons for ageing have been identified as oxidation and deposition and chrome plating has been proved to be a possible solution to alleviate the ageing problem. Also the significance of accounting for ageing effect in reporting for research results and designing pool boiling heat sinks have been discussed.
{"title":"Experimental Study of Ageing Effect in Pool Boiling Heat Transfer","authors":"Tianqing Wu, P. Lee, J. Mathew, SiuMing Lu","doi":"10.1109/EPTC.2018.8654374","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654374","url":null,"abstract":"In recent years, there is an increasing need for better cooling solutions to maintain a uniform and low temperature in high power density electronic devices. With much research effort devoted to it, pool boiling has been identified as a promising method to remove heat with less moving parts and high efficiency. The phase change during pool boiling can absorb large amount of heat and the nucleating bubbles can evacuate into the liquid pool automatically due to buoyance force, thereby assuring liquid rewetting of the heat sink surface and lower its working temperature. For the utilization of pool boiling heat sinks in industries like power generation plants, data centers and military systems, heat sinks are expected to operate consistently with high performance. Therefore, the effect of aging on heat sink performance needs to be evaluated closely. In this study, pool boiling experiments have been conducted with plain and finned heat sinks each for several times with a certain gap up to the highest heat flux and the ageing problem have been examined for the influence in heat transfer performance and heat sink surface characteristics. The main reasons for ageing have been identified as oxidation and deposition and chrome plating has been proved to be a possible solution to alleviate the ageing problem. Also the significance of accounting for ageing effect in reporting for research results and designing pool boiling heat sinks have been discussed.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"211 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134305087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654403
Toshizumi Yoshino, Toshimasa Nagoshi, S. Nomoto, A. Nakamura, Nobuhito Komuro, Hayato Sawamoto, Yuta Daijima, Yoshikazu Suzuki
As the functionality of electronic devices is becoming higher, semiconductors with multiple pins and thinner packages are dramatically proceeding. For the photo sensitive insulation is tied to be used for those devices, high reliability such as crack resistance and Highly Accelerated temperature and humidity Stress Test (HAST) resistance is required.
{"title":"Development of PID material for top thin layer and inner layer insulation","authors":"Toshizumi Yoshino, Toshimasa Nagoshi, S. Nomoto, A. Nakamura, Nobuhito Komuro, Hayato Sawamoto, Yuta Daijima, Yoshikazu Suzuki","doi":"10.1109/EPTC.2018.8654403","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654403","url":null,"abstract":"As the functionality of electronic devices is becoming higher, semiconductors with multiple pins and thinner packages are dramatically proceeding. For the photo sensitive insulation is tied to be used for those devices, high reliability such as crack resistance and Highly Accelerated temperature and humidity Stress Test (HAST) resistance is required.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131767894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：