Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654327
Tan Leng Hin “Adrian”, Pan Wei Chih “Lenz”, Chan Li-san, Lo Yee Ting, Fritzsche Sebastian
With the miniaturization of components in advanced packaging, interconnect requires fine solder joints to be formed. To be able to form small solder joints, solder paste with ultrafine solder particles is required. For ultrafine powder there are important powder characteristics such as particle size distributions (PSD), surface oxide and aspect ratio which need to be considered.A proprietary process technology is used to produce ultrafine SAC305 (Sn-3Ag-0.5Cu) powder with particle size ranging from $2 mu mathrm{m}$ to $25 mu mathrm{m}$ with tight particle size distributions and high sphericity. Focus will be on new ultrafine powders $(28 mu mathrm{m})$ and characterization will be presented for PSD, surface oxide content and aspect ratio. Surface oxide content will be characterized using inert gas fusion infrared technology while particle size distribution is characterized using laser diffraction method.The ultrafine powder was made into solder paste (water soluble) for feasibility studies. Impact of PSD and surface oxide on paste characteristics like solder balling, solder bridging and cold slump will be discussed. Finally, results for printability on ultrafine pitch and solder volume after reflow will be discussed.
随着先进封装中元件的小型化，互连需要形成精细的焊点。为了能够形成小的焊点，需要具有超细焊料颗粒的锡膏。对于超细粉体，需要考虑粒度分布(PSD)、表面氧化物和长径比等粉体特性。采用自主研发的工艺技术，可制得粒度为$2 mu mathrm{m}$ ~ $25 mu mathrm{m}$的超细SAC305 (Sn-3Ag-0.5Cu)粉体，粉体粒度分布紧密，球形度高。重点将是新的超细粉末$(28 mu mathm {m})$，并将介绍PSD，表面氧化物含量和纵横比的表征。采用惰性气体融合红外技术对表面氧化物含量进行表征，采用激光衍射法对粒度分布进行表征。将超细粉末制成可溶于水的锡膏，进行可行性研究。将讨论PSD和表面氧化物对膏体特性的影响，如焊锡球团、焊锡桥接和冷坍落度。最后，讨论了回流后超细间距和焊料体积的印刷适性。
{"title":"Characterization and Performance of Ultrafine Lead-Free powders","authors":"Tan Leng Hin “Adrian”, Pan Wei Chih “Lenz”, Chan Li-san, Lo Yee Ting, Fritzsche Sebastian","doi":"10.1109/EPTC.2018.8654327","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654327","url":null,"abstract":"With the miniaturization of components in advanced packaging, interconnect requires fine solder joints to be formed. To be able to form small solder joints, solder paste with ultrafine solder particles is required. For ultrafine powder there are important powder characteristics such as particle size distributions (PSD), surface oxide and aspect ratio which need to be considered.A proprietary process technology is used to produce ultrafine SAC305 (Sn-3Ag-0.5Cu) powder with particle size ranging from $2 mu mathrm{m}$ to $25 mu mathrm{m}$ with tight particle size distributions and high sphericity. Focus will be on new ultrafine powders $(28 mu mathrm{m})$ and characterization will be presented for PSD, surface oxide content and aspect ratio. Surface oxide content will be characterized using inert gas fusion infrared technology while particle size distribution is characterized using laser diffraction method.The ultrafine powder was made into solder paste (water soluble) for feasibility studies. Impact of PSD and surface oxide on paste characteristics like solder balling, solder bridging and cold slump will be discussed. Finally, results for printability on ultrafine pitch and solder volume after reflow will be discussed.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123943777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654349
Zhi Jin, H. Nishikawa, Y. Chan
In recent years, the demand of lithium ion battery is enlarged because of enormous capacity and free from memory effect which was widely applied to electronic devices. However, the explosion of Samsung Note7 battery arouses public attention in of lithium ion battery‘s safety issue. In addition, the capacity of battery will drop during usage time, one battery can only work for two years normally. In this study, we will find caused the explosion and capacity decrease of battery during usage process. The methodology started with thermal shock test to accelerate the aging time of battery. During the testing, the capacity change of battery after each 200 h was recorded. After the test, each component including the protective circuit, cathode and anode were analyzed respectively. From protective circuit aspects, the corrosion of PCB by hydrofluoric acid will cause malfunction of the circuit leading to overcharging or over-discharging. Since the decomposition of SEI on anode leading to exfoliation of graphite. The generation of fresh SEI will consume lithium ion inside the electrolyte leading to capacity decrease. Moreover, the phenomenon why some batteries will be swollen up during usage has been analyzed from chemical reaction aspect. Finally, this study can be used to offer good suggestions to manufacturers in improving the reliability of lithium ion battery.
{"title":"Failure analysis on Mobile Phone Batteries and Accessories","authors":"Zhi Jin, H. Nishikawa, Y. Chan","doi":"10.1109/EPTC.2018.8654349","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654349","url":null,"abstract":"In recent years, the demand of lithium ion battery is enlarged because of enormous capacity and free from memory effect which was widely applied to electronic devices. However, the explosion of Samsung Note7 battery arouses public attention in of lithium ion battery‘s safety issue. In addition, the capacity of battery will drop during usage time, one battery can only work for two years normally. In this study, we will find caused the explosion and capacity decrease of battery during usage process. The methodology started with thermal shock test to accelerate the aging time of battery. During the testing, the capacity change of battery after each 200 h was recorded. After the test, each component including the protective circuit, cathode and anode were analyzed respectively. From protective circuit aspects, the corrosion of PCB by hydrofluoric acid will cause malfunction of the circuit leading to overcharging or over-discharging. Since the decomposition of SEI on anode leading to exfoliation of graphite. The generation of fresh SEI will consume lithium ion inside the electrolyte leading to capacity decrease. Moreover, the phenomenon why some batteries will be swollen up during usage has been analyzed from chemical reaction aspect. Finally, this study can be used to offer good suggestions to manufacturers in improving the reliability of lithium ion battery.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126209457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654369
B. Eichinger, T. Behrendt, S. Ohm, F. Craes, M. Mischitz, R. Brunner
In this study, we investigate Cu sinter pastes consisting of coated and dispersed nano- and micro-particles for pure-Cu die-attach applications of Si dies on Cu-plated DCB. The sinter pastes are deposited on wafer level by stencil printing prior to thermal pre-conditioning and die separation. We show the required process conditions for die-attach formation by pressure sintering of Cu pastes in reducing atmosphere at elevated temperatures. We evaluate the quality of the sinter interconnect by mandrel bending, Scanning Acoustic Microscopy (SAM), Scanning Electron Microscopy (SEM) and thermal shock testing (TST). Using a linear regression analysis and putting the results into context with the SEM and SAM analysis, we can show that sinter force and sinter duration are highly influential process parameters, while Cu thickness and a HCOOH pre-cleaning step do not show any significant effect on the joint formation. We further show that on DCB level, the Cu sinter joint can withstand dynamic temperature loading between $-40^{circ}mathrm{C}$ and $+150^{circ}mathrm{C}$ up to 500 cycles without showing any significant signs of degradation.
{"title":"Cu Sinter Pastes for Pure-Cu Die-Attach Applications of Power Modules","authors":"B. Eichinger, T. Behrendt, S. Ohm, F. Craes, M. Mischitz, R. Brunner","doi":"10.1109/EPTC.2018.8654369","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654369","url":null,"abstract":"In this study, we investigate Cu sinter pastes consisting of coated and dispersed nano- and micro-particles for pure-Cu die-attach applications of Si dies on Cu-plated DCB. The sinter pastes are deposited on wafer level by stencil printing prior to thermal pre-conditioning and die separation. We show the required process conditions for die-attach formation by pressure sintering of Cu pastes in reducing atmosphere at elevated temperatures. We evaluate the quality of the sinter interconnect by mandrel bending, Scanning Acoustic Microscopy (SAM), Scanning Electron Microscopy (SEM) and thermal shock testing (TST). Using a linear regression analysis and putting the results into context with the SEM and SAM analysis, we can show that sinter force and sinter duration are highly influential process parameters, while Cu thickness and a HCOOH pre-cleaning step do not show any significant effect on the joint formation. We further show that on DCB level, the Cu sinter joint can withstand dynamic temperature loading between $-40^{circ}mathrm{C}$ and $+150^{circ}mathrm{C}$ up to 500 cycles without showing any significant signs of degradation.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128513411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654355
Zhaohui Chen, Xiaowu Zhang, S. Lim, S. Lim, B. L. Lau, Yong Han, M. C. Jong, Songlin Liu, Xiaobai Wang, Y. Andriani
In this paper, the solder joint reliability under $-40^{circ} mathrm{C} -125^{circ}mathrm{C}$ thermal cycling loading of different package sizes of mold-first FOWLP and redistribution layer first (RDL-first) FOWLP was studied by finite element simulation considering the viscoelastic material property of epoxy molding compound (EMC), dielectric and underfill. The critical solder joint is located at the die corner for the designed mold-first and RDL-first FOWLP. Volume average creep strain energy density range of critical solder joint increases with the package size from 12 mm $times$12 mm $times$0.2 mm to 18 mm $times$ 18 mm $times$0.2 mm for mold-first FOWLP. The distance to neutral point (DNP) becomes invalid when the RDL-first FOWLP package size increases to 18 mm $times$18 mm $times$0.2 mm. Volume average creep strain energy density range of package corner solder joint is overestimated without considering the viscoelastic material properties. However, the volume average creep strain energy density range of die corner solder joint is underestimated without considering the viscoelastic material properties. Low CTE PCB can help to improve the reliability of the critical solder joint at die corner of the designed mold-first FOWLP. The effects of the low CTE PCB for improving solder joint reliability the designed RDL-first FOWLP is not significant. Thinner PCB can help to improve the reliability of the critical solder joint at die corner of both mold-first and RDL-first FOWLP.
考虑环氧成型复合材料(EMC)、介电介质和下填料的粘弹性材料特性，采用有限元模拟方法研究了不同封装尺寸的模具优先和再分布层优先(RDL-first) FOWLP在$-40^{circ} mathm {C} -125^{circ} mathm {C}$热循环载荷下的焊点可靠性。对于设计的模具优先和rdl优先的FOWLP，关键焊点位于模具角。对于模具优先型FOWLP，关键焊点的体积平均蠕变应变能密度范围随着封装尺寸的增加而增加，从12 mm × 12 mm × 0.2 mm到18 mm × 18 mm × 0.2 mm。当RDL-first FOWLP封装尺寸增加到18mm × 18mm × 0.2 mm时，到中立点的距离(DNP)失效。在不考虑材料粘弹性的情况下，高估了封装角焊点的体积平均蠕变应变能密度范围。然而，在不考虑材料粘弹性的情况下，模具角焊点的体积平均蠕变应变能密度范围被低估了。低CTE PCB有助于提高设计的模具优先型FOWLP的模角关键焊点的可靠性。低CTE PCB对提高RDL-first FOWLP焊点可靠性的影响不显著。更薄的PCB有助于提高模具优先和rdl优先的FOWLP的模具角关键焊点的可靠性。
{"title":"Solder Joint Reliability Simulation of Fan-out Wafer Level Package (FOWLP) Considering Viscoelastic Material Properties","authors":"Zhaohui Chen, Xiaowu Zhang, S. Lim, S. Lim, B. L. Lau, Yong Han, M. C. Jong, Songlin Liu, Xiaobai Wang, Y. Andriani","doi":"10.1109/EPTC.2018.8654355","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654355","url":null,"abstract":"In this paper, the solder joint reliability under $-40^{circ} mathrm{C} -125^{circ}mathrm{C}$ thermal cycling loading of different package sizes of mold-first FOWLP and redistribution layer first (RDL-first) FOWLP was studied by finite element simulation considering the viscoelastic material property of epoxy molding compound (EMC), dielectric and underfill. The critical solder joint is located at the die corner for the designed mold-first and RDL-first FOWLP. Volume average creep strain energy density range of critical solder joint increases with the package size from 12 mm $times$12 mm $times$0.2 mm to 18 mm $times$ 18 mm $times$0.2 mm for mold-first FOWLP. The distance to neutral point (DNP) becomes invalid when the RDL-first FOWLP package size increases to 18 mm $times$18 mm $times$0.2 mm. Volume average creep strain energy density range of package corner solder joint is overestimated without considering the viscoelastic material properties. However, the volume average creep strain energy density range of die corner solder joint is underestimated without considering the viscoelastic material properties. Low CTE PCB can help to improve the reliability of the critical solder joint at die corner of the designed mold-first FOWLP. The effects of the low CTE PCB for improving solder joint reliability the designed RDL-first FOWLP is not significant. Thinner PCB can help to improve the reliability of the critical solder joint at die corner of both mold-first and RDL-first FOWLP.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130908567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654425
David Choong Sze Wai, Ruiqi Lim, M. R. Damalerio, Weiguo Chen, Ming-Yuan Cheng
In this work, we present a flexible printed multi-functional sensor platform for medical applications. The device consists of printed temperature and force elements on a flexible printed circuit board (FPCB). The thickness, curing temperatures and encapsulating epoxies are optimized for the individual inks and the device is assembled and tested on the benchtop. Force measurements against impedance and temperature measurements against impedance were then conducted and discussed. The performance of both sensors were then characterized.
{"title":"Development of a Flexible Printed Multi-Functional Sensor Platform for Medical Applications","authors":"David Choong Sze Wai, Ruiqi Lim, M. R. Damalerio, Weiguo Chen, Ming-Yuan Cheng","doi":"10.1109/EPTC.2018.8654425","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654425","url":null,"abstract":"In this work, we present a flexible printed multi-functional sensor platform for medical applications. The device consists of printed temperature and force elements on a flexible printed circuit board (FPCB). The thickness, curing temperatures and encapsulating epoxies are optimized for the individual inks and the device is assembled and tested on the benchtop. Force measurements against impedance and temperature measurements against impedance were then conducted and discussed. The performance of both sensors were then characterized.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131296861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654311
Kisu Joo, Kyu Jae Lee, Jung-Woo Hwang, Jin-Ho Yoon, Yoonhyun Kim, Se Young Jeong
We studied and demonstrated high-performance Ag epoxy composites. A variety of shaped Ag particles were teste to optimize the electrical properties and mechanical reliability. The resulting Ag epoxy composites containing flake-shaped Ag particles showed less than $5 times 10 ^{-7} Omega cdot mathrm {m}$ electrical conductivity and about $20mathrm {m} Omega $ series-resistance of PKG daisy chain, which directly corresponded to the excellent shield effectiveness. The shield effectiveness of resulting EMI shielding layer made of Ag and matrix is as high as 60dB, 65dB, 70dB at 5 $mu {mathrm{ m}}$, 10 $mu {mathrm{ m}}$, 20 $mu {mathrm{ m}}$-thick film, respectively by ASTM standard. We studied that how various factors, such as curing temperature, Ag contents, and film thickness, effects the electrical properties of shielding material and FCBGA package. It was found that the resistivity of conductive shielding material and the series-resistance were affected by the curing temperature than the curing time. Additionally, we demonstrated the electrical properties of AgCu epoxy composites.
{"title":"High Performance Package-Level EMI shielding of Ag Epoxy Composites with Spray method for High Frequency FCBGA package Application","authors":"Kisu Joo, Kyu Jae Lee, Jung-Woo Hwang, Jin-Ho Yoon, Yoonhyun Kim, Se Young Jeong","doi":"10.1109/EPTC.2018.8654311","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654311","url":null,"abstract":"We studied and demonstrated high-performance Ag epoxy composites. A variety of shaped Ag particles were teste to optimize the electrical properties and mechanical reliability. The resulting Ag epoxy composites containing flake-shaped Ag particles showed less than $5 times 10 ^{-7} Omega cdot mathrm {m}$ electrical conductivity and about $20mathrm {m} Omega $ series-resistance of PKG daisy chain, which directly corresponded to the excellent shield effectiveness. The shield effectiveness of resulting EMI shielding layer made of Ag and matrix is as high as 60dB, 65dB, 70dB at 5 $mu {mathrm{ m}}$, 10 $mu {mathrm{ m}}$, 20 $mu {mathrm{ m}}$-thick film, respectively by ASTM standard. We studied that how various factors, such as curing temperature, Ag contents, and film thickness, effects the electrical properties of shielding material and FCBGA package. It was found that the resistivity of conductive shielding material and the series-resistance were affected by the curing temperature than the curing time. Additionally, we demonstrated the electrical properties of AgCu epoxy composites.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125689426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654309
Atsuhiro Hamasawa, H. Kanaya
This paper presents the design of a dual-band low noise amplifier (LNA) with a single input differential outputs of 5.2 GHz and 2.4GHz band with $0.18 mu mathrm{m}$ CMOS technology. In order to achieve the goal of expanding the availability of telecommunication system, this LNA is designed as a dual-band operation by using a band pass filter and a notch filter simultaneously [1]. Moreover, by introducing the CG (common gate)-CS (common source) topology [2], we can obtain the output phase differs by 0 and 180 degrees. This will reduce the connection loss to the mixer developed in the previous study [3]. In this paper, simulation results of gain, noise figure and output phase difference are shown, and a chip layout is shown. The proposed LNA has a gain of 16.5 dB and 11.1 dB at 2.4 GHz and 5.2 GHz, a noise figure of 3.1 dB and 3.7 dB, and the phase difference is less than 0.32 degrees.
{"title":"Dual-band differential outputs CMOS Low Noise Amplifier","authors":"Atsuhiro Hamasawa, H. Kanaya","doi":"10.1109/EPTC.2018.8654309","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654309","url":null,"abstract":"This paper presents the design of a dual-band low noise amplifier (LNA) with a single input differential outputs of 5.2 GHz and 2.4GHz band with $0.18 mu mathrm{m}$ CMOS technology. In order to achieve the goal of expanding the availability of telecommunication system, this LNA is designed as a dual-band operation by using a band pass filter and a notch filter simultaneously [1]. Moreover, by introducing the CG (common gate)-CS (common source) topology [2], we can obtain the output phase differs by 0 and 180 degrees. This will reduce the connection loss to the mixer developed in the previous study [3]. In this paper, simulation results of gain, noise figure and output phase difference are shown, and a chip layout is shown. The proposed LNA has a gain of 16.5 dB and 11.1 dB at 2.4 GHz and 5.2 GHz, a noise figure of 3.1 dB and 3.7 dB, and the phase difference is less than 0.32 degrees.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127734910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654433
Yong Han, B. L. Lau, G. Tang, S. Lim, Xiaowu Zhang
Si micro-fluid heat sink, which has attracted extensive attentions, can achieve high heat dissipation capability, while requiring very low pumping power and small coolant volume. Based on simulation investigation, a Si-based micro-fluidic solution has been developed for high performance processor cooling. A stacked micro-fluid heat sink with micro-jet slot array, micro-scale draining trenches and micro-pin fins, is designed and fabricated. With volume flow rate 1L/min and pressure drop smaller than 3kPa, spatially averaged heat transfer coefficient of $sim9.6times10^{4}mathrm{W}/mathrm{m}^{2}mathrm{K}$ can be achieved using the designed micro-fluid structure. Experimental tests have been performed, and the results agreed quite well with the simulation data. To dissipate 150W heating power of thermal test chip, the maximum chip temperature rise can be maintained less than $25^{circ}mathrm{C}$. The developed hybrid microfluidic solution will be a good candidate for thermal management of server processor in future advanced data center.
{"title":"Si-Based Hybrid Microfluidic Cooling for Server Processor of Data Centre","authors":"Yong Han, B. L. Lau, G. Tang, S. Lim, Xiaowu Zhang","doi":"10.1109/EPTC.2018.8654433","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654433","url":null,"abstract":"Si micro-fluid heat sink, which has attracted extensive attentions, can achieve high heat dissipation capability, while requiring very low pumping power and small coolant volume. Based on simulation investigation, a Si-based micro-fluidic solution has been developed for high performance processor cooling. A stacked micro-fluid heat sink with micro-jet slot array, micro-scale draining trenches and micro-pin fins, is designed and fabricated. With volume flow rate 1L/min and pressure drop smaller than 3kPa, spatially averaged heat transfer coefficient of $sim9.6times10^{4}mathrm{W}/mathrm{m}^{2}mathrm{K}$ can be achieved using the designed micro-fluid structure. Experimental tests have been performed, and the results agreed quite well with the simulation data. To dissipate 150W heating power of thermal test chip, the maximum chip temperature rise can be maintained less than $25^{circ}mathrm{C}$. The developed hybrid microfluidic solution will be a good candidate for thermal management of server processor in future advanced data center.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127759313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654269
Yong Han, B. L. Lau, G. Tang, S. Lim, Xiaowu Zhang
Thermal test package has been designed to mimic the thermal performance of mainstream processor used in data center for micro-fluid cooling characterization. The target heat power of the test chip is $gt$150W for characterization. Platinum (Pt) heaters and temperature sensors have been designed in thermal test chip. Regarding meander heat line, three types of structure have been designed while maintaining same total electrical resistance in each chip. To fabricate the thermal test chip, 5 masks have been designed and prepared. Pt heaters and sensors have been fabricated simultaneously using DC sputtering process. The thermal test chips located at different positions in one wafer are measured, and the sensors located at different positions in the chips are tested as well. Results show that average resistances of heater and sensor are 300$Omega$ and 1075$Omega$ respectively, and errors are within ±5%. The thermal test packages work quite well at high heating power in the cooling solution characterization tests
{"title":"Development of Thermal Test Package for Data Center Micro-Fluid Cooling Characterization","authors":"Yong Han, B. L. Lau, G. Tang, S. Lim, Xiaowu Zhang","doi":"10.1109/EPTC.2018.8654269","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654269","url":null,"abstract":"Thermal test package has been designed to mimic the thermal performance of mainstream processor used in data center for micro-fluid cooling characterization. The target heat power of the test chip is $gt$150W for characterization. Platinum (Pt) heaters and temperature sensors have been designed in thermal test chip. Regarding meander heat line, three types of structure have been designed while maintaining same total electrical resistance in each chip. To fabricate the thermal test chip, 5 masks have been designed and prepared. Pt heaters and sensors have been fabricated simultaneously using DC sputtering process. The thermal test chips located at different positions in one wafer are measured, and the sensors located at different positions in the chips are tested as well. Results show that average resistances of heater and sensor are 300$Omega$ and 1075$Omega$ respectively, and errors are within ±5%. The thermal test packages work quite well at high heating power in the cooling solution characterization tests","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127502215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654347
Lim Ming Siong, Chai Yuan Tat
Changing of quality requirement in manufacturing technologies has to be followed by an adaption of material and process parameters. With the rapid emerging vision inspection technologies, 100% automated optical inspection as quality firewall is always a preferred option to pursue. In the case of transition from human to automated optical inspection to enhance defect detectability, the adaption effort is high due to different capabilities between human and machines on observation and interpretation of the criteria. This will strongly affect the justification of acceptance level which will subsequently cause over or under rejection. For encapsulated IC, the challenges are not only on the ability to detect the defect but also to recognize the laser marking character printed on the surface of the mold compound, which are used as traceability and identification purpose.A theoretical concept is being described to get a grasp of the occurring mechanism. From laser mark aspect, respective factors such as marking depth range coupled with correct marking size with respect to the field of view (FOV) are identified as major contributor for mark legibility. From material point of view, the compatibility of wax type (ratio of hydrophilic and hydrophobic parts) towards multi aromatic resin (MAR) or multifunctional resin (MFR) is identified as the cause of the flow mark or wax stain which eventually contribute the noise of visual inspection. Also from material aspect, types of flame retardant either metal hydroxide or organic phosphorous cause low curability which affects the molded package surface evenness eventually affect visual inspection results. From mold tool aspect, the range of lower roughness average (Ra) of the Electrical Discharge Surface (EDM) mold cavity surface is preferred for better mark legibility. At the end, a proposal is given on parameters, material and tool set to get the best encapsulated IC package surfaces with clear and legible marking. The constraints and corresponding potential risks are also discussed in this paper in order to achieve the best results yet not induce other negative impact.
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