Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654292
Chih-Sung Chen, N. Kao, P. Liao, Ssu-Cheng Lai, D. Jiang
Embedded trace substrate (ETS), like a typical build-up process that prepreg (PP) has been laminated on the copper trace patent, is a coreless substrate design for improvement both production yield and capability of substrate with finer line and space (L/S) dimension. The manufacturing process of ETS used an electrolytic copper plating method to form copper foil pattern coated on carrier board, and then multi-layers of ETS structure will duplicate the same process flow to been made, such as laser via drill, electro-less copper plating, dry-film lamination, exposure and development, next layer plating of copper pattern, stripping after removing carrier board, micro etching to enhance adhesion with solder mask, and metal treatment of surface finish after process of solder mask opening. Different to traditional build-up process, the trace width of ETS structure would not be attacked during process of micro etching, and the wall structure formed by dry-film between traces can prevent solder bridge problem of copper pillar bump during process of flip chip bond (FCB) [1]. Manufacturing process of ETS must go through a sequential high-temperature and -pressure step, thus the approach to construct a complex and detailed model is so far engineer’s objective for accurate prediction. When the assumption of stress-free at single curing temperature even though the chemical shrinkage has be considered is challenged, manufacturing temperature-independent model could not match well with experimental measurements because they don’t include an integrated processing modeling methodology. In particular, temperature-dependent material properties and different stress-free temperatures for different materials in the same model were considered in order to model the sequential steps during the sequential fabrication of high-density electronic packaging structures. However, the effort on fundamental study usually makes an impossible work due to time-and manpower-consuming, thus the mission has been transferred to construct an effective and simple approach on thermo-mechanical analysis. In this study, the material modeling has been simply constructed on elastically temperature-dependence for polymeric material utilized in packaging extensively. Furthermore, the innovative concept of conservation laws also has been developed on stress constitutive model; meanwhile, the creative ideology, such as cross-linking induced residual strain ($varepsilon_{mathrm {RS}}$) from compound forming and process-induced stress field, further has been embedded. Others, the experimental vehicles also have been performed for a reasonable simplification at single stress-free temperature of substrate, besides measurements were scheduled to confirm the accuracy on warpage. As comparison, these two different warpage modeling methodologies, including processing model and non-processing model, of an encapsulated integrated circuit (IC) package, associated with different schemes of a sequential manufa
{"title":"Processing Models Based on Stress Conservation Law Utilized for Temperature-Dependent Warpage Prediction of MUF FCCSP with 3L ETS","authors":"Chih-Sung Chen, N. Kao, P. Liao, Ssu-Cheng Lai, D. Jiang","doi":"10.1109/EPTC.2018.8654292","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654292","url":null,"abstract":"Embedded trace substrate (ETS), like a typical build-up process that prepreg (PP) has been laminated on the copper trace patent, is a coreless substrate design for improvement both production yield and capability of substrate with finer line and space (L/S) dimension. The manufacturing process of ETS used an electrolytic copper plating method to form copper foil pattern coated on carrier board, and then multi-layers of ETS structure will duplicate the same process flow to been made, such as laser via drill, electro-less copper plating, dry-film lamination, exposure and development, next layer plating of copper pattern, stripping after removing carrier board, micro etching to enhance adhesion with solder mask, and metal treatment of surface finish after process of solder mask opening. Different to traditional build-up process, the trace width of ETS structure would not be attacked during process of micro etching, and the wall structure formed by dry-film between traces can prevent solder bridge problem of copper pillar bump during process of flip chip bond (FCB) [1]. Manufacturing process of ETS must go through a sequential high-temperature and -pressure step, thus the approach to construct a complex and detailed model is so far engineer’s objective for accurate prediction. When the assumption of stress-free at single curing temperature even though the chemical shrinkage has be considered is challenged, manufacturing temperature-independent model could not match well with experimental measurements because they don’t include an integrated processing modeling methodology. In particular, temperature-dependent material properties and different stress-free temperatures for different materials in the same model were considered in order to model the sequential steps during the sequential fabrication of high-density electronic packaging structures. However, the effort on fundamental study usually makes an impossible work due to time-and manpower-consuming, thus the mission has been transferred to construct an effective and simple approach on thermo-mechanical analysis. In this study, the material modeling has been simply constructed on elastically temperature-dependence for polymeric material utilized in packaging extensively. Furthermore, the innovative concept of conservation laws also has been developed on stress constitutive model; meanwhile, the creative ideology, such as cross-linking induced residual strain ($varepsilon_{mathrm {RS}}$) from compound forming and process-induced stress field, further has been embedded. Others, the experimental vehicles also have been performed for a reasonable simplification at single stress-free temperature of substrate, besides measurements were scheduled to confirm the accuracy on warpage. As comparison, these two different warpage modeling methodologies, including processing model and non-processing model, of an encapsulated integrated circuit (IC) package, associated with different schemes of a sequential manufa","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134170478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As the copper pillar bumps with fine pitch and high density were widely applied in high I/O interconnection packaging. It’s increasingly important to study the effect of bonding properties of copper pillar bumps for different morphology and interconnection methods. In the paper, we designed Test Vehicle of copper pillar bumps and manufacture $30 mu mathrm{m}$ pitch copper pillar bumps for verifying the bonding effect between copper pillar bumps. We compared the bonding experiments of copper pillar bumps of different exterior morphology and different bonding methods. Finally, using the four-probe method to test the resistance of the bonded bumps and the bonding yield of partial micro bumps can roughly be evaluated by has been designed daisy chain structure.
由于铜柱凸点具有细间距和高密度的特点，在高I/O互连封装中得到了广泛的应用。研究不同形貌和连接方式对铜柱凸点连接性能的影响显得越来越重要。本文设计了铜柱凸架试验车，制作了$30 mu mathm {m}$节距铜柱凸架，验证了铜柱凸架之间的粘结效果。比较了不同外部形貌和不同连接方式的铜柱凸点的连接实验。最后，利用四探针法测试了粘结凸点的电阻，通过设计的菊花链结构可以大致评价局部微凸点的粘结成品率。
{"title":"Research on the effect of bonding properties of micro bumps for different morphology and interconnection methods","authors":"Fengwei Dai, David-Wei Zhang, Guojun Wang, Dengfen Yang, Wenqi Zhang, Liqiang Cao","doi":"10.1109/EPTC.2018.8654346","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654346","url":null,"abstract":"As the copper pillar bumps with fine pitch and high density were widely applied in high I/O interconnection packaging. It’s increasingly important to study the effect of bonding properties of copper pillar bumps for different morphology and interconnection methods. In the paper, we designed Test Vehicle of copper pillar bumps and manufacture $30 mu mathrm{m}$ pitch copper pillar bumps for verifying the bonding effect between copper pillar bumps. We compared the bonding experiments of copper pillar bumps of different exterior morphology and different bonding methods. Finally, using the four-probe method to test the resistance of the bonded bumps and the bonding yield of partial micro bumps can roughly be evaluated by has been designed daisy chain structure.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"29 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131830096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654347
Lim Ming Siong, Chai Yuan Tat
Changing of quality requirement in manufacturing technologies has to be followed by an adaption of material and process parameters. With the rapid emerging vision inspection technologies, 100% automated optical inspection as quality firewall is always a preferred option to pursue. In the case of transition from human to automated optical inspection to enhance defect detectability, the adaption effort is high due to different capabilities between human and machines on observation and interpretation of the criteria. This will strongly affect the justification of acceptance level which will subsequently cause over or under rejection. For encapsulated IC, the challenges are not only on the ability to detect the defect but also to recognize the laser marking character printed on the surface of the mold compound, which are used as traceability and identification purpose.A theoretical concept is being described to get a grasp of the occurring mechanism. From laser mark aspect, respective factors such as marking depth range coupled with correct marking size with respect to the field of view (FOV) are identified as major contributor for mark legibility. From material point of view, the compatibility of wax type (ratio of hydrophilic and hydrophobic parts) towards multi aromatic resin (MAR) or multifunctional resin (MFR) is identified as the cause of the flow mark or wax stain which eventually contribute the noise of visual inspection. Also from material aspect, types of flame retardant either metal hydroxide or organic phosphorous cause low curability which affects the molded package surface evenness eventually affect visual inspection results. From mold tool aspect, the range of lower roughness average (Ra) of the Electrical Discharge Surface (EDM) mold cavity surface is preferred for better mark legibility. At the end, a proposal is given on parameters, material and tool set to get the best encapsulated IC package surfaces with clear and legible marking. The constraints and corresponding potential risks are also discussed in this paper in order to achieve the best results yet not induce other negative impact.
{"title":"Effect of the laser parameters, epoxy mold compound properties and mold tool surface finishing on mark legibility of encapsulated IC package","authors":"Lim Ming Siong, Chai Yuan Tat","doi":"10.1109/EPTC.2018.8654347","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654347","url":null,"abstract":"Changing of quality requirement in manufacturing technologies has to be followed by an adaption of material and process parameters. With the rapid emerging vision inspection technologies, 100% automated optical inspection as quality firewall is always a preferred option to pursue. In the case of transition from human to automated optical inspection to enhance defect detectability, the adaption effort is high due to different capabilities between human and machines on observation and interpretation of the criteria. This will strongly affect the justification of acceptance level which will subsequently cause over or under rejection. For encapsulated IC, the challenges are not only on the ability to detect the defect but also to recognize the laser marking character printed on the surface of the mold compound, which are used as traceability and identification purpose.A theoretical concept is being described to get a grasp of the occurring mechanism. From laser mark aspect, respective factors such as marking depth range coupled with correct marking size with respect to the field of view (FOV) are identified as major contributor for mark legibility. From material point of view, the compatibility of wax type (ratio of hydrophilic and hydrophobic parts) towards multi aromatic resin (MAR) or multifunctional resin (MFR) is identified as the cause of the flow mark or wax stain which eventually contribute the noise of visual inspection. Also from material aspect, types of flame retardant either metal hydroxide or organic phosphorous cause low curability which affects the molded package surface evenness eventually affect visual inspection results. From mold tool aspect, the range of lower roughness average (Ra) of the Electrical Discharge Surface (EDM) mold cavity surface is preferred for better mark legibility. At the end, a proposal is given on parameters, material and tool set to get the best encapsulated IC package surfaces with clear and legible marking. The constraints and corresponding potential risks are also discussed in this paper in order to achieve the best results yet not induce other negative impact.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"41 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132678137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654417
Terence Lucero F. Menor, M. Mena, H. Mendoza
Solder paste dispensing is a key process in the electronics assembly. The increased global demand for smaller, lighter, faster and cheaper assemblies drives the electronics industry to use dispensers with finer apertures. However, reduction in the aperture size of dispensers faces the industry with increased clogging of dispensers and incomplete transfer of paste to the printed circuit board (PCB) pads. One factor contributing to the clogging of dispensers is the agglomeration of the solder powder suspensions which depends on the electrokinetic behavior of the particles. When suspensions are close to the point of no charge, wherein zeta potential is equal to zero, the particles tend to agglomerate. This work focuses on the determination of the zeta potential of Sn, SAC305 and PbSn5Ag2.5 suspensions in isopropyl alcohol (IPA) through microelectrophoresis. The effect of acid, base and flux additives were studied. Results showed that the zeta potential of the solder suspensions are negative in pure IPA and charge reversal occurs in both acidic and basic region. In systems containing flux additives, the zeta potential of the suspensions is highly dependent on the type efflux. FTIR spectroscopy, conductivity measurement, and surface analysis was done in order to explain the observed electrokinetic behavior.
{"title":"Electrokinetic Behavior of Solder Powders in Non-aqueous Media","authors":"Terence Lucero F. Menor, M. Mena, H. Mendoza","doi":"10.1109/EPTC.2018.8654417","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654417","url":null,"abstract":"Solder paste dispensing is a key process in the electronics assembly. The increased global demand for smaller, lighter, faster and cheaper assemblies drives the electronics industry to use dispensers with finer apertures. However, reduction in the aperture size of dispensers faces the industry with increased clogging of dispensers and incomplete transfer of paste to the printed circuit board (PCB) pads. One factor contributing to the clogging of dispensers is the agglomeration of the solder powder suspensions which depends on the electrokinetic behavior of the particles. When suspensions are close to the point of no charge, wherein zeta potential is equal to zero, the particles tend to agglomerate. This work focuses on the determination of the zeta potential of Sn, SAC305 and PbSn5Ag2.5 suspensions in isopropyl alcohol (IPA) through microelectrophoresis. The effect of acid, base and flux additives were studied. Results showed that the zeta potential of the solder suspensions are negative in pure IPA and charge reversal occurs in both acidic and basic region. In systems containing flux additives, the zeta potential of the suspensions is highly dependent on the type efflux. FTIR spectroscopy, conductivity measurement, and surface analysis was done in order to explain the observed electrokinetic behavior.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132897845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654305
Xiangy-Yu Wang, Hongyu Li
As Moore’s law appears to come to the end when the transistor size approaches to its physical scaling limits, peoples begin to look for the new technology to break through the barrier beyond Moore’s law. TSV is one potential option as it could further increase integration density vertically. In this study, a high aspect ratio 10$mu mathrm{m} times100 mu$m TSV from the wafer back side is demonstrated and some of the critical process will be discussed.
{"title":"High Aspect Ratio~10 TSV Via-last-from-back Process Development and Integration","authors":"Xiangy-Yu Wang, Hongyu Li","doi":"10.1109/EPTC.2018.8654305","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654305","url":null,"abstract":"As Moore’s law appears to come to the end when the transistor size approaches to its physical scaling limits, peoples begin to look for the new technology to break through the barrier beyond Moore’s law. TSV is one potential option as it could further increase integration density vertically. In this study, a high aspect ratio 10$mu mathrm{m} times100 mu$m TSV from the wafer back side is demonstrated and some of the critical process will be discussed.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115889009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654411
S. Lim, S. Chong, W. Seit, T. Chai
The continuous requirements of package miniaturization in the demand of mobile application market have shown the increase in demand of many FOWLP packaging [1]. The applications of FOWLP has many advantages including shorter interconnection, lower heat resistance, better electrical efficiency and smaller package form factor [2].The work presented in this paper describes the reconfigured wafer approach in fan-out wafer level technology that allows multiple dies with high solder interconnect to package using the molded interposer for FOWLP technology. In this work, we presented some of the work done prior to the flip chip bonding process and the different approaches to resolve some of the process issues encountered in the assembly process for 3 test dies with high I/Os onto a fan-out mold interposer. The 1st test die is the 15x15mm ASIC die with 21472 I/Os and the remaining 2 dies are the 7x7mm HBM dies with 4942 I/Os. Both the ASIC and HBM dies have a minimum bump pitch at 55 μ m. The 12 inch through molded interposer wafer is singulated into individual interposer prior to the flip chip attachment process.The package warpage remains the main concern in the through mold interposer assembly. To minimize interposer warpage, a metal stiffener was attached to the molded interposer. Results shows the attachment of the metal stiffener helps to reduce the package warpage. In addition, a thinner die thickness of 150 μ m helps to reduce the overall molded interposer package‘s warpage after assembly compared to a die thickness of 500 μ m. Cross-section analysis was done to inspect the solderjoint shape at 150 μ m and 500 μ m die thickness. Further optimized thermocompression bonding process and capillary underfill process helps to ensure good solderjoint interconnection and no underfill voids for a robust Fine pitch interconnect Fan-out WLP assembly.
{"title":"Challenges and Approaches of 2.5D high density Flip chip interconnect on through mold interposer","authors":"S. Lim, S. Chong, W. Seit, T. Chai","doi":"10.1109/EPTC.2018.8654411","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654411","url":null,"abstract":"The continuous requirements of package miniaturization in the demand of mobile application market have shown the increase in demand of many FOWLP packaging [1]. The applications of FOWLP has many advantages including shorter interconnection, lower heat resistance, better electrical efficiency and smaller package form factor [2].The work presented in this paper describes the reconfigured wafer approach in fan-out wafer level technology that allows multiple dies with high solder interconnect to package using the molded interposer for FOWLP technology. In this work, we presented some of the work done prior to the flip chip bonding process and the different approaches to resolve some of the process issues encountered in the assembly process for 3 test dies with high I/Os onto a fan-out mold interposer. The 1st test die is the 15x15mm ASIC die with 21472 I/Os and the remaining 2 dies are the 7x7mm HBM dies with 4942 I/Os. Both the ASIC and HBM dies have a minimum bump pitch at 55 μ m. The 12 inch through molded interposer wafer is singulated into individual interposer prior to the flip chip attachment process.The package warpage remains the main concern in the through mold interposer assembly. To minimize interposer warpage, a metal stiffener was attached to the molded interposer. Results shows the attachment of the metal stiffener helps to reduce the package warpage. In addition, a thinner die thickness of 150 μ m helps to reduce the overall molded interposer package‘s warpage after assembly compared to a die thickness of 500 μ m. Cross-section analysis was done to inspect the solderjoint shape at 150 μ m and 500 μ m die thickness. Further optimized thermocompression bonding process and capillary underfill process helps to ensure good solderjoint interconnection and no underfill voids for a robust Fine pitch interconnect Fan-out WLP assembly.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116099245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654327
Tan Leng Hin “Adrian”, Pan Wei Chih “Lenz”, Chan Li-san, Lo Yee Ting, Fritzsche Sebastian
With the miniaturization of components in advanced packaging, interconnect requires fine solder joints to be formed. To be able to form small solder joints, solder paste with ultrafine solder particles is required. For ultrafine powder there are important powder characteristics such as particle size distributions (PSD), surface oxide and aspect ratio which need to be considered.A proprietary process technology is used to produce ultrafine SAC305 (Sn-3Ag-0.5Cu) powder with particle size ranging from $2 mu mathrm{m}$ to $25 mu mathrm{m}$ with tight particle size distributions and high sphericity. Focus will be on new ultrafine powders $(28 mu mathrm{m})$ and characterization will be presented for PSD, surface oxide content and aspect ratio. Surface oxide content will be characterized using inert gas fusion infrared technology while particle size distribution is characterized using laser diffraction method.The ultrafine powder was made into solder paste (water soluble) for feasibility studies. Impact of PSD and surface oxide on paste characteristics like solder balling, solder bridging and cold slump will be discussed. Finally, results for printability on ultrafine pitch and solder volume after reflow will be discussed.
随着先进封装中元件的小型化，互连需要形成精细的焊点。为了能够形成小的焊点，需要具有超细焊料颗粒的锡膏。对于超细粉体，需要考虑粒度分布(PSD)、表面氧化物和长径比等粉体特性。采用自主研发的工艺技术，可制得粒度为$2 mu mathrm{m}$ ~ $25 mu mathrm{m}$的超细SAC305 (Sn-3Ag-0.5Cu)粉体，粉体粒度分布紧密，球形度高。重点将是新的超细粉末$(28 mu mathm {m})$，并将介绍PSD，表面氧化物含量和纵横比的表征。采用惰性气体融合红外技术对表面氧化物含量进行表征，采用激光衍射法对粒度分布进行表征。将超细粉末制成可溶于水的锡膏，进行可行性研究。将讨论PSD和表面氧化物对膏体特性的影响，如焊锡球团、焊锡桥接和冷坍落度。最后，讨论了回流后超细间距和焊料体积的印刷适性。
{"title":"Characterization and Performance of Ultrafine Lead-Free powders","authors":"Tan Leng Hin “Adrian”, Pan Wei Chih “Lenz”, Chan Li-san, Lo Yee Ting, Fritzsche Sebastian","doi":"10.1109/EPTC.2018.8654327","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654327","url":null,"abstract":"With the miniaturization of components in advanced packaging, interconnect requires fine solder joints to be formed. To be able to form small solder joints, solder paste with ultrafine solder particles is required. For ultrafine powder there are important powder characteristics such as particle size distributions (PSD), surface oxide and aspect ratio which need to be considered.A proprietary process technology is used to produce ultrafine SAC305 (Sn-3Ag-0.5Cu) powder with particle size ranging from $2 mu mathrm{m}$ to $25 mu mathrm{m}$ with tight particle size distributions and high sphericity. Focus will be on new ultrafine powders $(28 mu mathrm{m})$ and characterization will be presented for PSD, surface oxide content and aspect ratio. Surface oxide content will be characterized using inert gas fusion infrared technology while particle size distribution is characterized using laser diffraction method.The ultrafine powder was made into solder paste (water soluble) for feasibility studies. Impact of PSD and surface oxide on paste characteristics like solder balling, solder bridging and cold slump will be discussed. Finally, results for printability on ultrafine pitch and solder volume after reflow will be discussed.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123943777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654369
B. Eichinger, T. Behrendt, S. Ohm, F. Craes, M. Mischitz, R. Brunner
In this study, we investigate Cu sinter pastes consisting of coated and dispersed nano- and micro-particles for pure-Cu die-attach applications of Si dies on Cu-plated DCB. The sinter pastes are deposited on wafer level by stencil printing prior to thermal pre-conditioning and die separation. We show the required process conditions for die-attach formation by pressure sintering of Cu pastes in reducing atmosphere at elevated temperatures. We evaluate the quality of the sinter interconnect by mandrel bending, Scanning Acoustic Microscopy (SAM), Scanning Electron Microscopy (SEM) and thermal shock testing (TST). Using a linear regression analysis and putting the results into context with the SEM and SAM analysis, we can show that sinter force and sinter duration are highly influential process parameters, while Cu thickness and a HCOOH pre-cleaning step do not show any significant effect on the joint formation. We further show that on DCB level, the Cu sinter joint can withstand dynamic temperature loading between $-40^{circ}mathrm{C}$ and $+150^{circ}mathrm{C}$ up to 500 cycles without showing any significant signs of degradation.
{"title":"Cu Sinter Pastes for Pure-Cu Die-Attach Applications of Power Modules","authors":"B. Eichinger, T. Behrendt, S. Ohm, F. Craes, M. Mischitz, R. Brunner","doi":"10.1109/EPTC.2018.8654369","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654369","url":null,"abstract":"In this study, we investigate Cu sinter pastes consisting of coated and dispersed nano- and micro-particles for pure-Cu die-attach applications of Si dies on Cu-plated DCB. The sinter pastes are deposited on wafer level by stencil printing prior to thermal pre-conditioning and die separation. We show the required process conditions for die-attach formation by pressure sintering of Cu pastes in reducing atmosphere at elevated temperatures. We evaluate the quality of the sinter interconnect by mandrel bending, Scanning Acoustic Microscopy (SAM), Scanning Electron Microscopy (SEM) and thermal shock testing (TST). Using a linear regression analysis and putting the results into context with the SEM and SAM analysis, we can show that sinter force and sinter duration are highly influential process parameters, while Cu thickness and a HCOOH pre-cleaning step do not show any significant effect on the joint formation. We further show that on DCB level, the Cu sinter joint can withstand dynamic temperature loading between $-40^{circ}mathrm{C}$ and $+150^{circ}mathrm{C}$ up to 500 cycles without showing any significant signs of degradation.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128513411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654339
Z. Cen, X. Shan, B. Salam, L. S. Rachel Tan, J. Wei
In order to print various functional components for printed electronics, inks with different viscosities may be used in gravure printing. In this study, influence of ink viscosity on gravure printing quality at individual cell level is reported. In gravure printing experiments using dielectric Barium Titanate (BaTiO3) nanoparticles inks of different viscosities, a void defect can be observed at the front edge of the printed pattern of an individual engraved cell. And the void became larger both for ink with higher viscosity and at higher printing speed. In our experiments, it was noticed that the voids can lead to open defects in the whole printed pattern of high viscosity ink, undermining the printing quality. In order to study the forming mechanism of the voids, experimental results were analyzed based on computational fluid dynamic (CFD) simulation studies of wiping step in the gravure printing process. Simulation confirmed that the observed void is caused by the unfilled space at the leading edge of the engraved cell during wiping. Effects of wiping speed and ink viscosity have been investigated, and the simulation results are consistent with experiments. Based on the experimental and theoretical results, it can be concluded that, for gravure printing using high viscosity ink, printing speed needs to be slowed down in order to reduce defects. The present study enhanced understanding of ink transfer in gravure printing and provided a guide line for high quality gravure printing.
{"title":"Void Defect Formed in Wiping Step of Gravure Printing","authors":"Z. Cen, X. Shan, B. Salam, L. S. Rachel Tan, J. Wei","doi":"10.1109/EPTC.2018.8654339","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654339","url":null,"abstract":"In order to print various functional components for printed electronics, inks with different viscosities may be used in gravure printing. In this study, influence of ink viscosity on gravure printing quality at individual cell level is reported. In gravure printing experiments using dielectric Barium Titanate (BaTiO3) nanoparticles inks of different viscosities, a void defect can be observed at the front edge of the printed pattern of an individual engraved cell. And the void became larger both for ink with higher viscosity and at higher printing speed. In our experiments, it was noticed that the voids can lead to open defects in the whole printed pattern of high viscosity ink, undermining the printing quality. In order to study the forming mechanism of the voids, experimental results were analyzed based on computational fluid dynamic (CFD) simulation studies of wiping step in the gravure printing process. Simulation confirmed that the observed void is caused by the unfilled space at the leading edge of the engraved cell during wiping. Effects of wiping speed and ink viscosity have been investigated, and the simulation results are consistent with experiments. Based on the experimental and theoretical results, it can be concluded that, for gravure printing using high viscosity ink, printing speed needs to be slowed down in order to reduce defects. The present study enhanced understanding of ink transfer in gravure printing and provided a guide line for high quality gravure printing.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130409364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654355
Zhaohui Chen, Xiaowu Zhang, S. Lim, S. Lim, B. L. Lau, Yong Han, M. C. Jong, Songlin Liu, Xiaobai Wang, Y. Andriani
In this paper, the solder joint reliability under $-40^{circ} mathrm{C} -125^{circ}mathrm{C}$ thermal cycling loading of different package sizes of mold-first FOWLP and redistribution layer first (RDL-first) FOWLP was studied by finite element simulation considering the viscoelastic material property of epoxy molding compound (EMC), dielectric and underfill. The critical solder joint is located at the die corner for the designed mold-first and RDL-first FOWLP. Volume average creep strain energy density range of critical solder joint increases with the package size from 12 mm $times$12 mm $times$0.2 mm to 18 mm $times$ 18 mm $times$0.2 mm for mold-first FOWLP. The distance to neutral point (DNP) becomes invalid when the RDL-first FOWLP package size increases to 18 mm $times$18 mm $times$0.2 mm. Volume average creep strain energy density range of package corner solder joint is overestimated without considering the viscoelastic material properties. However, the volume average creep strain energy density range of die corner solder joint is underestimated without considering the viscoelastic material properties. Low CTE PCB can help to improve the reliability of the critical solder joint at die corner of the designed mold-first FOWLP. The effects of the low CTE PCB for improving solder joint reliability the designed RDL-first FOWLP is not significant. Thinner PCB can help to improve the reliability of the critical solder joint at die corner of both mold-first and RDL-first FOWLP.
考虑环氧成型复合材料(EMC)、介电介质和下填料的粘弹性材料特性，采用有限元模拟方法研究了不同封装尺寸的模具优先和再分布层优先(RDL-first) FOWLP在$-40^{circ} mathm {C} -125^{circ} mathm {C}$热循环载荷下的焊点可靠性。对于设计的模具优先和rdl优先的FOWLP，关键焊点位于模具角。对于模具优先型FOWLP，关键焊点的体积平均蠕变应变能密度范围随着封装尺寸的增加而增加，从12 mm × 12 mm × 0.2 mm到18 mm × 18 mm × 0.2 mm。当RDL-first FOWLP封装尺寸增加到18mm × 18mm × 0.2 mm时，到中立点的距离(DNP)失效。在不考虑材料粘弹性的情况下，高估了封装角焊点的体积平均蠕变应变能密度范围。然而，在不考虑材料粘弹性的情况下，模具角焊点的体积平均蠕变应变能密度范围被低估了。低CTE PCB有助于提高设计的模具优先型FOWLP的模角关键焊点的可靠性。低CTE PCB对提高RDL-first FOWLP焊点可靠性的影响不显著。更薄的PCB有助于提高模具优先和rdl优先的FOWLP的模具角关键焊点的可靠性。
{"title":"Solder Joint Reliability Simulation of Fan-out Wafer Level Package (FOWLP) Considering Viscoelastic Material Properties","authors":"Zhaohui Chen, Xiaowu Zhang, S. Lim, S. Lim, B. L. Lau, Yong Han, M. C. Jong, Songlin Liu, Xiaobai Wang, Y. Andriani","doi":"10.1109/EPTC.2018.8654355","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654355","url":null,"abstract":"In this paper, the solder joint reliability under $-40^{circ} mathrm{C} -125^{circ}mathrm{C}$ thermal cycling loading of different package sizes of mold-first FOWLP and redistribution layer first (RDL-first) FOWLP was studied by finite element simulation considering the viscoelastic material property of epoxy molding compound (EMC), dielectric and underfill. The critical solder joint is located at the die corner for the designed mold-first and RDL-first FOWLP. Volume average creep strain energy density range of critical solder joint increases with the package size from 12 mm $times$12 mm $times$0.2 mm to 18 mm $times$ 18 mm $times$0.2 mm for mold-first FOWLP. The distance to neutral point (DNP) becomes invalid when the RDL-first FOWLP package size increases to 18 mm $times$18 mm $times$0.2 mm. Volume average creep strain energy density range of package corner solder joint is overestimated without considering the viscoelastic material properties. However, the volume average creep strain energy density range of die corner solder joint is underestimated without considering the viscoelastic material properties. Low CTE PCB can help to improve the reliability of the critical solder joint at die corner of the designed mold-first FOWLP. The effects of the low CTE PCB for improving solder joint reliability the designed RDL-first FOWLP is not significant. Thinner PCB can help to improve the reliability of the critical solder joint at die corner of both mold-first and RDL-first FOWLP.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130908567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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