Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654445
Satish Bonam, C. H. Kumar, S. Vanjari, S. Singh
In the present modern era of electronic industry has motivated for high performance integration by vertically stacked three dimensional integrated circuits (3D ICs). Electronic interconnections at packaging and die levels, Pbfree solder micro bumps are intended to replace conventional Pb-containing solder joints due to increasing awareness of an environmental conservation, and processing at low thermal budgets. The better alternative for solder is copper, due to its high electrical and thermal properties. But the surface oxidation was the major bottleneck. In this work, we have demonstrated low temperature and low-pressure copper to copper interconnect bonding using optimized thin gold passivation layer. Here the passivation layer over the copper surface was optimized to a thickness of 3nm there by helps in preventing Cu surface oxidation and makes lower surface RMS roughness. High-density surface plane orientations that have been studied using XRD helped in faster diffusion through an interface. Majorly in this work, we have discussed the time taken for copper atoms to diffuse over the ultra-thin passivation layer of gold using Fick’s second law approximation. These conditions have been used while bonding. Bonded samples were subjected to various reliability studies in order to confirm the efficacy of the proposed Au passivation based bonded structure. Also, we have observed the Interface quality using TEM, and C-SAM (mode C-Scanning acoustic microscopy) imaging resulting in good quality of bonding. The diffusion of copper atomic species movement across the interface is confirmed by EDS analysis. Low and stable specific contact resistance ($sim$1.43 $times$ 10-8 $Omega$ cm2) at robust conditions are confirmed to be effective and front runner for low temperature, low pressure Cu-Cu bonding for 3D IC packaging and heterogeneous integration.
{"title":"Gold Passivated Cu-Cu Bonding At 140°C For 3D IC Packaging And Heterogeneous Integration Applications.","authors":"Satish Bonam, C. H. Kumar, S. Vanjari, S. Singh","doi":"10.1109/EPTC.2018.8654445","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654445","url":null,"abstract":"In the present modern era of electronic industry has motivated for high performance integration by vertically stacked three dimensional integrated circuits (3D ICs). Electronic interconnections at packaging and die levels, Pbfree solder micro bumps are intended to replace conventional Pb-containing solder joints due to increasing awareness of an environmental conservation, and processing at low thermal budgets. The better alternative for solder is copper, due to its high electrical and thermal properties. But the surface oxidation was the major bottleneck. In this work, we have demonstrated low temperature and low-pressure copper to copper interconnect bonding using optimized thin gold passivation layer. Here the passivation layer over the copper surface was optimized to a thickness of 3nm there by helps in preventing Cu surface oxidation and makes lower surface RMS roughness. High-density surface plane orientations that have been studied using XRD helped in faster diffusion through an interface. Majorly in this work, we have discussed the time taken for copper atoms to diffuse over the ultra-thin passivation layer of gold using Fick’s second law approximation. These conditions have been used while bonding. Bonded samples were subjected to various reliability studies in order to confirm the efficacy of the proposed Au passivation based bonded structure. Also, we have observed the Interface quality using TEM, and C-SAM (mode C-Scanning acoustic microscopy) imaging resulting in good quality of bonding. The diffusion of copper atomic species movement across the interface is confirmed by EDS analysis. Low and stable specific contact resistance ($sim$1.43 $times$ 10-8 $Omega$ cm2) at robust conditions are confirmed to be effective and front runner for low temperature, low pressure Cu-Cu bonding for 3D IC packaging and heterogeneous integration.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129209029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654365
I. Qin, Aashish Shah, B. Milton, G. Schulze, A. Chang, N. Wong
More and more semiconductor manufacturers are adopting “smart” technology to improve throughput, yield and factory efficiency. In this paper, we examine how smart technology addresses two big challenges of wire bonding including fine pitch Cu first bond process and multi-tier looping. Fine pitch Cu first bond process has smaller process window and is harder to optimize than the traditional Au wire process. Through extensive research and development, a smart response based process was developed to provide wider process windows and easier adjustments. The main input to this process is desired ball diameter. Based on the desired ball diameter and other device information, optimal bonding parameters are calculated. This new smart 1st bond process is compared to traditional process to demonstrate fine pitch Cu wire bonding capability. In addition to the response based process with automatic parameter calculation, real time control is added for process monitoring and closed loop control. A new feature called Deformation Control is developed to control ball deformation using real time bonder signal feedback. Test results show that the ball size range and shear Cpk is significantly improved using this feature.The second area where major improvements have been made using smart wire bonding technology is multi-tier looping. For multi-tier devices, multiple tiers of loops with different loop heights and wire lengths need to be optimized to ensure high yield wire bonding production. A 1000 +I /O multi-tier package often requires more than 100 looping parameter groups. This results in months of looping development before a new device can be run in production. A new smart looping process was developed to address these challenges. The new looping process contains a 3D Loop Design software (3D AutoOLP) which is an offline loop design tool, and a wire loop model (ProCu Loop) that automatically calculates the looping motions to produce desired loop shapes. Four different real life applications were designed and tested with the new looping process and compared to traditional method. The average optimization time is reduced from 6 weeks to 1 week for these packages and there is a more than 50% reduction of the number of looping parameter groups. In addition, real time loop height monitor is developed to monitor loop height during production.
{"title":"Smart Wire Bonding Processes for Smart Factories","authors":"I. Qin, Aashish Shah, B. Milton, G. Schulze, A. Chang, N. Wong","doi":"10.1109/EPTC.2018.8654365","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654365","url":null,"abstract":"More and more semiconductor manufacturers are adopting “smart” technology to improve throughput, yield and factory efficiency. In this paper, we examine how smart technology addresses two big challenges of wire bonding including fine pitch Cu first bond process and multi-tier looping. Fine pitch Cu first bond process has smaller process window and is harder to optimize than the traditional Au wire process. Through extensive research and development, a smart response based process was developed to provide wider process windows and easier adjustments. The main input to this process is desired ball diameter. Based on the desired ball diameter and other device information, optimal bonding parameters are calculated. This new smart 1st bond process is compared to traditional process to demonstrate fine pitch Cu wire bonding capability. In addition to the response based process with automatic parameter calculation, real time control is added for process monitoring and closed loop control. A new feature called Deformation Control is developed to control ball deformation using real time bonder signal feedback. Test results show that the ball size range and shear Cpk is significantly improved using this feature.The second area where major improvements have been made using smart wire bonding technology is multi-tier looping. For multi-tier devices, multiple tiers of loops with different loop heights and wire lengths need to be optimized to ensure high yield wire bonding production. A 1000 +I /O multi-tier package often requires more than 100 looping parameter groups. This results in months of looping development before a new device can be run in production. A new smart looping process was developed to address these challenges. The new looping process contains a 3D Loop Design software (3D AutoOLP) which is an offline loop design tool, and a wire loop model (ProCu Loop) that automatically calculates the looping motions to produce desired loop shapes. Four different real life applications were designed and tested with the new looping process and compared to traditional method. The average optimization time is reduced from 6 weeks to 1 week for these packages and there is a more than 50% reduction of the number of looping parameter groups. In addition, real time loop height monitor is developed to monitor loop height during production.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116755820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654273
Zheng Zhang, Chuangtong Chen, S. Kurosaka, K. Suganuma
Realizing silver (Ag) sinter joining on gold surface finished substrates has attracted extensive attention because gold surfaces have superior performance and durability. In this work, the bonding strength was improved by increasing the grain size of gold layer, which was accomplished by preheating gold surface finished substrates or changing thickness of gold layer. With the different processes, the bonding strength of Ag sinter joining can be increased in varying degrees, which ranges from 25 % to 100 %. SEM observation and XRD analysis were conducted to calculate the grain size of gold and clarify the mechanism of improvement in bonding strength. The results indicated that gold layer with the large gold grains shows a better bonding strength than the fine gold grains substrates, which because two different Au-Ag diffusion patterns happened on gold surface finished substrates. A possible equation that indicates the relationship between the bonding strength and the gold grain size was also proposed in this work.
{"title":"Improvement in bonding strength of Ag sinter joining on gold surface finished substrates by increasing the gold grain size","authors":"Zheng Zhang, Chuangtong Chen, S. Kurosaka, K. Suganuma","doi":"10.1109/EPTC.2018.8654273","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654273","url":null,"abstract":"Realizing silver (Ag) sinter joining on gold surface finished substrates has attracted extensive attention because gold surfaces have superior performance and durability. In this work, the bonding strength was improved by increasing the grain size of gold layer, which was accomplished by preheating gold surface finished substrates or changing thickness of gold layer. With the different processes, the bonding strength of Ag sinter joining can be increased in varying degrees, which ranges from 25 % to 100 %. SEM observation and XRD analysis were conducted to calculate the grain size of gold and clarify the mechanism of improvement in bonding strength. The results indicated that gold layer with the large gold grains shows a better bonding strength than the fine gold grains substrates, which because two different Au-Ag diffusion patterns happened on gold surface finished substrates. A possible equation that indicates the relationship between the bonding strength and the gold grain size was also proposed in this work.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117212933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654357
S. Masuda, Y. Iwai, M. Sawano, Kotaro Okabe, Kazuto Shimada, Caparas Jose Alvin, W. Choi
The wafer thinning process and making backside redistribution layer (RDL) process were key technologies for assembling 2.5D and 3D IC the low profile device manufacturing. It was widely studied about temporary bonding material (TBM) for those advanced device packaging. The key issues here were void free, bonding, thermal resistance without having delamination and defect free cleaning after debonding. To minimize the cost effective 3D IC manufacturing, we have developed single layer temperature bonding material designed for room temperature mechanical debonding process. The materials have a high thermal resistance over 230 °C for 4 hours without having any void formation, delamination and no residue on the eWLB device after solvent cleaning.
{"title":"Temporary Bonding Material Study for Room Temperature Mechanical Debonding with eWLB Wafer Application","authors":"S. Masuda, Y. Iwai, M. Sawano, Kotaro Okabe, Kazuto Shimada, Caparas Jose Alvin, W. Choi","doi":"10.1109/EPTC.2018.8654357","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654357","url":null,"abstract":"The wafer thinning process and making backside redistribution layer (RDL) process were key technologies for assembling 2.5D and 3D IC the low profile device manufacturing. It was widely studied about temporary bonding material (TBM) for those advanced device packaging. The key issues here were void free, bonding, thermal resistance without having delamination and defect free cleaning after debonding. To minimize the cost effective 3D IC manufacturing, we have developed single layer temperature bonding material designed for room temperature mechanical debonding process. The materials have a high thermal resistance over 230 °C for 4 hours without having any void formation, delamination and no residue on the eWLB device after solvent cleaning.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115322107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654430
Wayne Ng, T. Akaiwa, P. Narayanan, K. Sweatman, T. Nishimura, T. Nishimura
The function of the strengthening mechanism in Sn-based Pbfree solder alloys is to inhibit the movement through the Sn crystals, which make up the bulk of the solder volume, of the dislocations that can otherwise move relatively freely along crystal slip planes. Available mechanisms include, particle strengthening, solid solution strengthening and grain refining. The widely used Sn-3.0Ag-0.5Cu alloy (SAC305) relies on particle strengthening by the fine eutectic Ag3 Sn intermetallic compound that is dispersed in the Sn phase in the interdendritic spaces. However, these fine particles with their high surface area:volume ratio are thermodynamically unstable and by the process known as Ostwald ripening gradually coarsen, even at ambient temperature, so that their effectiveness as obstacles to dislocation movement fades and the strength of the solder declines towards that of unalloyed Sn. The realisation that the particle strengthening effect of the Ag is only temporary has triggered a search for alternative strengthening mechanism and solid solution strengthening has been identified as a promising candidate. The solid solution strengthening effect is not degraded by ageing and is therefore more stable than that provided by particle strengthening. In the as-soldered condition the particle strengthening by Ag3 Sn is effective, delivering good performance in accelerated thermal cycle testing. However, the flow stress of the particle strengthened alloy is sensitive to strain rate. At high strain rates that increased resistance to strain means that the stress is transmitted largely undiminished to the solder substrate interface or to the underlying laminate where brittle fracture can easily propagate. It is for this reason that SAC305 is notoriously susceptible to failure in drop impact. While it is well recognised that the performance of SAC alloys in drop impact is improved by reducing the Ag content reliability in other stress conditions is compromised. While the flow stress of a solid solution strengthened Ag-free Pb-free alloy can be as high as that of SAC305 it might be that because of the different mechanism is different it might be less sensitivity to strain rate than a particle strengthened alloy. In the work reported in this paper BGA solder spheres of three alloys with different strengthening mechanisms, particle strengthening with Ag, solid solution strengthening with Bi and a combination of both were reflowed to a Cu substrate and the resulting ball tested in shear impact at displacement speeds of 10mm/s, 1000mm/s and 2000mm/s in the as reflowed condition and after ageing for 500h at $150 ^{circ}mathrm{C}$. In the interpretation of the results account is taken of the variation in fracture modes in the 20 repeats undertaken for each test condition (alloy, shear speed, as-reflowed and after ageing).
在锡基无铅钎料合金中，强化机制的作用是抑制位错在锡晶体中的移动，否则这些位错可以沿着晶体滑移面相对自由地移动。锡晶体占焊料体积的大部分。现有的机制包括:颗粒强化、固溶强化和晶粒细化。广泛应用的Sn-3.0 ag -0.5 cu合金(SAC305)依赖于分散在枝晶间隙Sn相中的细小共晶Ag3 Sn金属间化合物的颗粒强化。然而，这些具有高表面积:体积比的细颗粒在热力学上是不稳定的，并且通过称为奥斯特瓦尔德成熟的过程逐渐变粗，即使在环境温度下，因此它们作为位错运动障碍的有效性逐渐减弱，焊料的强度下降到非合金化锡的强度。认识到Ag的颗粒强化作用只是暂时的，引发了对替代强化机制的探索，而固溶体强化已被确定为有希望的候选机制。固溶强化效果不会因时效而降低，因此比颗粒强化更稳定。在焊接状态下，ag3sn的颗粒强化是有效的，在加速热循环测试中表现良好。而颗粒强化合金的流变应力对应变速率很敏感。在高应变率下，增加的抗应变能力意味着应力在很大程度上不减少地传递到焊料基板界面或下层层板，脆性断裂很容易在那里传播。正是由于这个原因，SAC305是出了名的容易在跌落冲击失败。虽然人们普遍认为，降低Ag含量可以提高SAC合金在跌落冲击中的性能，但在其他应力条件下的可靠性却受到损害。固溶强化无银无铅合金的流变应力可以达到SAC305的水平，但由于机制不同，对应变速率的敏感性可能低于颗粒强化合金。在本文报道的工作中，将三种不同强化机制的合金(Ag颗粒强化、Bi固溶体强化和两者结合)的BGA焊锡球回流到Cu基体上，并在回流条件下，在位移速度为10mm/s、1000mm/s和2000mm/s的情况下，在150 ^{circ}数学{C}$时效500h后进行剪切冲击试验。在解释结果时，考虑到在每种测试条件下(合金、剪切速度、再流和时效后)进行的20次重复中断裂模式的变化。
{"title":"Effect of the Strengthening Mechanism on the Response of a Solder Alloy to Strain Rate and Ageing","authors":"Wayne Ng, T. Akaiwa, P. Narayanan, K. Sweatman, T. Nishimura, T. Nishimura","doi":"10.1109/EPTC.2018.8654430","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654430","url":null,"abstract":"The function of the strengthening mechanism in Sn-based Pbfree solder alloys is to inhibit the movement through the Sn crystals, which make up the bulk of the solder volume, of the dislocations that can otherwise move relatively freely along crystal slip planes. Available mechanisms include, particle strengthening, solid solution strengthening and grain refining. The widely used Sn-3.0Ag-0.5Cu alloy (SAC305) relies on particle strengthening by the fine eutectic Ag3 Sn intermetallic compound that is dispersed in the Sn phase in the interdendritic spaces. However, these fine particles with their high surface area:volume ratio are thermodynamically unstable and by the process known as Ostwald ripening gradually coarsen, even at ambient temperature, so that their effectiveness as obstacles to dislocation movement fades and the strength of the solder declines towards that of unalloyed Sn. The realisation that the particle strengthening effect of the Ag is only temporary has triggered a search for alternative strengthening mechanism and solid solution strengthening has been identified as a promising candidate. The solid solution strengthening effect is not degraded by ageing and is therefore more stable than that provided by particle strengthening. In the as-soldered condition the particle strengthening by Ag3 Sn is effective, delivering good performance in accelerated thermal cycle testing. However, the flow stress of the particle strengthened alloy is sensitive to strain rate. At high strain rates that increased resistance to strain means that the stress is transmitted largely undiminished to the solder substrate interface or to the underlying laminate where brittle fracture can easily propagate. It is for this reason that SAC305 is notoriously susceptible to failure in drop impact. While it is well recognised that the performance of SAC alloys in drop impact is improved by reducing the Ag content reliability in other stress conditions is compromised. While the flow stress of a solid solution strengthened Ag-free Pb-free alloy can be as high as that of SAC305 it might be that because of the different mechanism is different it might be less sensitivity to strain rate than a particle strengthened alloy. In the work reported in this paper BGA solder spheres of three alloys with different strengthening mechanisms, particle strengthening with Ag, solid solution strengthening with Bi and a combination of both were reflowed to a Cu substrate and the resulting ball tested in shear impact at displacement speeds of 10mm/s, 1000mm/s and 2000mm/s in the as reflowed condition and after ageing for 500h at $150 ^{circ}mathrm{C}$. In the interpretation of the results account is taken of the variation in fracture modes in the 20 repeats undertaken for each test condition (alloy, shear speed, as-reflowed and after ageing).","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127460778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654360
N. Ichikawa, M. Mogi
The electrostatics phenomenon is frequently used in photocopiers and other applications, but it is a source of malfunctions or failures of electronic equipment. The electronic equipment of a personal computer, etc. occasionally malfunctions owing to the occurrence of electrostatically induced voltages generated in the metal box housing of the equipment. Malfunctions or other failures of an electronic device used in electronic equipment can occur when induced voltages of 10 V or lower are generated. The voltage of a charged human body can occasionally exceed 10 kV in an office. Thus, when such a charged body moves near the metal housing of electronic equipment, a high induced voltage can be generated in the box. In high-voltage engineering, voltage measurement using the Paschen voltage of an electrical spark gap is frequently performed. In the experiments of the present study, the induced voltages in an ungrounded metal box and on an ungrounded metal box are measured when a charged body moves away from the metal box. The induced voltage generated in the ungrounded metal box is measured using a spark gap and an electromagnetic-wave sensor. The results show that the induced voltage generated in the ungrounded metal box is −1.2 times the voltage of a charged body when the charged body moves away from the metal box. The results are helpful for solving such electrostatic problems and designing electronic equipment.
{"title":"Electrostatically Induced Voltages Generated in Ungrounded Metal Box and on the Box When Charged Body Moves Away from the Box","authors":"N. Ichikawa, M. Mogi","doi":"10.1109/EPTC.2018.8654360","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654360","url":null,"abstract":"The electrostatics phenomenon is frequently used in photocopiers and other applications, but it is a source of malfunctions or failures of electronic equipment. The electronic equipment of a personal computer, etc. occasionally malfunctions owing to the occurrence of electrostatically induced voltages generated in the metal box housing of the equipment. Malfunctions or other failures of an electronic device used in electronic equipment can occur when induced voltages of 10 V or lower are generated. The voltage of a charged human body can occasionally exceed 10 kV in an office. Thus, when such a charged body moves near the metal housing of electronic equipment, a high induced voltage can be generated in the box. In high-voltage engineering, voltage measurement using the Paschen voltage of an electrical spark gap is frequently performed. In the experiments of the present study, the induced voltages in an ungrounded metal box and on an ungrounded metal box are measured when a charged body moves away from the metal box. The induced voltage generated in the ungrounded metal box is measured using a spark gap and an electromagnetic-wave sensor. The results show that the induced voltage generated in the ungrounded metal box is −1.2 times the voltage of a charged body when the charged body moves away from the metal box. The results are helpful for solving such electrostatic problems and designing electronic equipment.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125408097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654283
A. Adibi, A. Isapour, Mohsen Niayesh, A. Kouki
Higher data speeds spurred on by the arrival of 5G technology and the Internet of Things (IoT) have accelerated the need for increased circuit integration with shorter interconnects. 3D integration and packaging techniques that employ silicon interposers with Through Silicon Vias (TSVs) have emerged as one of the key technologies in enabling this trend. In this paper, a cost-effective alternative to silicon interposers based on Low Temperature Co-fired Ceramic (LTCC) technology is proposed and demonstrated. Using ultra-thin ceramic layers and laser ablation, ceramic interposers with micro-via holes as small as $20 mu mathrm{m}$ in diameter and $40 mu mathrm{m}$ pitch have been successfully realized. In addition to the standalone interposers, the developed fabrication process has been used to design a high-density package for the integration of Silicon Photonic (SiP) and electronic chips with operational bandwidth up to 48 GHz. This novel cost-effective packaging technology offers a viable alternative to silicon interposers for the integration of multi-chip high-speed electronic systems in a single package with high reliability and very good performance to maintain signal integrity.
5G技术和物联网(IoT)的到来刺激了更高的数据速度，加速了对更短互连的电路集成的需求。采用带有硅通孔(tsv)的硅中间层的3D集成和封装技术已经成为实现这一趋势的关键技术之一。本文提出并论证了一种基于低温共烧陶瓷(LTCC)技术的低成本硅中间体替代方案。利用超薄陶瓷层和激光烧蚀技术，成功实现了直径仅为$20 mu mathm {m}$、间距仅为$40 mu mathm {m}$的微通孔陶瓷中间体。除了独立的中间体外，开发的制造工艺已用于设计用于集成硅光子(SiP)和电子芯片的高密度封装，其操作带宽高达48 GHz。这种新颖的具有成本效益的封装技术为在单个封装中集成多芯片高速电子系统提供了一种可行的替代方案，具有高可靠性和非常好的性能，以保持信号完整性。
{"title":"Ceramic Interposers for Ultra-High Density Packaging and 3D Circuit Integration","authors":"A. Adibi, A. Isapour, Mohsen Niayesh, A. Kouki","doi":"10.1109/EPTC.2018.8654283","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654283","url":null,"abstract":"Higher data speeds spurred on by the arrival of 5G technology and the Internet of Things (IoT) have accelerated the need for increased circuit integration with shorter interconnects. 3D integration and packaging techniques that employ silicon interposers with Through Silicon Vias (TSVs) have emerged as one of the key technologies in enabling this trend. In this paper, a cost-effective alternative to silicon interposers based on Low Temperature Co-fired Ceramic (LTCC) technology is proposed and demonstrated. Using ultra-thin ceramic layers and laser ablation, ceramic interposers with micro-via holes as small as $20 mu mathrm{m}$ in diameter and $40 mu mathrm{m}$ pitch have been successfully realized. In addition to the standalone interposers, the developed fabrication process has been used to design a high-density package for the integration of Silicon Photonic (SiP) and electronic chips with operational bandwidth up to 48 GHz. This novel cost-effective packaging technology offers a viable alternative to silicon interposers for the integration of multi-chip high-speed electronic systems in a single package with high reliability and very good performance to maintain signal integrity.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125657907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654440
Jose Arvin M. Plomantes, Ruby Ann D. Mamangun, Armando T. Clarina, R. Guevara
In order to fabricate tall post technologies, chemically amplified positive resist with high viscosity is usually used. Thick and uniformly coated resist is patterned during lithography to act as mold prior copper (Cu) electroplating. An unoptimized photolithography process can consequently result to defects in the plated Cu pillar – among which is Cu footing. This defect poses electrical and reliability risks such as shorting and Cu migration.In this study, Cu post footing is resolved by enhancing the thick resist lithography process. The baseline recipe was initially optimized in order to set the parameters for the design of experiment (DOE). Among the settings checked include soft bake and post-exposure bake time and z-axis settings to optimize the heat transfer process, and the develop spin direction to improve the developer coverage. The confirmation run yielded a 20.6% improvement in resist undercut measurements.Using the baseline split as comparison, a 24-split multiple-facet four-variable full-factorial design of experiment was executed by taking into consideration the soft bake (125C, 80140–125C, 80–140C), expose (1800, 2000 mJ/cm2), postexposure bake (100C, 105C) and puddle develop settings (8x, 11x).The best DOE split (140C, 1800 mJ/cm2, 100C, 8x puddle) resulted to 58.8% reduction in the actual resist undercut which translates to Cu foot elimination. This is backed up by improvement in the undercut uniformity across the wafer as the standard deviation was also reduced by 63.9%. Considering a theoretical resist undercut to ensure optimization without jeopardizing the critical dimension, an 81.4% and 81.9% improvement was observed on the undercut readings and standard deviation, accordingly.Among the parameters involved, post-exposure bake, soft bake, and develop settings are shown to have significant effects in the improvement. The optimized heat transfer during the bake process helped in the uniform solvent dissipation and enhanced resist-to-substrate adhesion. Also, the stabilization of the photoactive compound (PAC) to carboxylic acid conversion during post-exposure bake at lower temperature ensured avoidance of over production of soluble acid. Finally, development at less puddle intervals caused controlled resist dissolution and removal.
{"title":"Enhancing Bump Thick Resist Lithography: Establishing Process Controls to Eliminate Copper Pillar Footing","authors":"Jose Arvin M. Plomantes, Ruby Ann D. Mamangun, Armando T. Clarina, R. Guevara","doi":"10.1109/EPTC.2018.8654440","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654440","url":null,"abstract":"In order to fabricate tall post technologies, chemically amplified positive resist with high viscosity is usually used. Thick and uniformly coated resist is patterned during lithography to act as mold prior copper (Cu) electroplating. An unoptimized photolithography process can consequently result to defects in the plated Cu pillar – among which is Cu footing. This defect poses electrical and reliability risks such as shorting and Cu migration.In this study, Cu post footing is resolved by enhancing the thick resist lithography process. The baseline recipe was initially optimized in order to set the parameters for the design of experiment (DOE). Among the settings checked include soft bake and post-exposure bake time and z-axis settings to optimize the heat transfer process, and the develop spin direction to improve the developer coverage. The confirmation run yielded a 20.6% improvement in resist undercut measurements.Using the baseline split as comparison, a 24-split multiple-facet four-variable full-factorial design of experiment was executed by taking into consideration the soft bake (125C, 80140–125C, 80–140C), expose (1800, 2000 mJ/cm2), postexposure bake (100C, 105C) and puddle develop settings (8x, 11x).The best DOE split (140C, 1800 mJ/cm2, 100C, 8x puddle) resulted to 58.8% reduction in the actual resist undercut which translates to Cu foot elimination. This is backed up by improvement in the undercut uniformity across the wafer as the standard deviation was also reduced by 63.9%. Considering a theoretical resist undercut to ensure optimization without jeopardizing the critical dimension, an 81.4% and 81.9% improvement was observed on the undercut readings and standard deviation, accordingly.Among the parameters involved, post-exposure bake, soft bake, and develop settings are shown to have significant effects in the improvement. The optimized heat transfer during the bake process helped in the uniform solvent dissipation and enhanced resist-to-substrate adhesion. Also, the stabilization of the photoactive compound (PAC) to carboxylic acid conversion during post-exposure bake at lower temperature ensured avoidance of over production of soluble acid. Finally, development at less puddle intervals caused controlled resist dissolution and removal.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"33 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125802058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654276
Si Chen, Zhizhe Wang, Bin Zhou, Y. En, Yun Huang, Bin Yao
Three current density levels, $2 times 10 ^{4},mathrm{A} /cm^{2}$, $2.5 times 10 ^{4},mathrm{A} /cm^{2}$ and $3 times 10 ^{4},mathrm{A} /cm^{2}$, were selected to conduct the electromigration tests on the Cu pillar bump samples at ambient temperatures of $100 ^{circ}mathrm{C}, 125 ^{circ}mathrm{C}$ and $150 ^{circ}mathrm{C}$ respectively. Scanning electron microscope (SEM) was used to observe the microstructure evolution and failure mode of Cu pillar bumps after electromigration. A finite element model is established to reveal the mechanical property degradation of Cu pillar bump caused by material migration during electromigration. The results show that, higher current density and higher ambient temperature can induce a faster electromigration of Cu pillar bump, thus results in a large number of cavities generate in the solder IMC. These cavities expanded continuously and caused more and more obvious stress concentration in the IMC during the process of electromigration. This stress concentration reached above 68MPa, exceeding the fracture strength of Cu6 Sn5, which can be partly explained the fracture failure of Cu pillar bumps observed in the experiment.
{"title":"Cracking failure of Cu pillar bump caused by electromigration and stress concentration under thermo-electric coupling loads","authors":"Si Chen, Zhizhe Wang, Bin Zhou, Y. En, Yun Huang, Bin Yao","doi":"10.1109/EPTC.2018.8654276","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654276","url":null,"abstract":"Three current density levels, $2 times 10 ^{4},mathrm{A} /cm^{2}$, $2.5 times 10 ^{4},mathrm{A} /cm^{2}$ and $3 times 10 ^{4},mathrm{A} /cm^{2}$, were selected to conduct the electromigration tests on the Cu pillar bump samples at ambient temperatures of $100 ^{circ}mathrm{C}, 125 ^{circ}mathrm{C}$ and $150 ^{circ}mathrm{C}$ respectively. Scanning electron microscope (SEM) was used to observe the microstructure evolution and failure mode of Cu pillar bumps after electromigration. A finite element model is established to reveal the mechanical property degradation of Cu pillar bump caused by material migration during electromigration. The results show that, higher current density and higher ambient temperature can induce a faster electromigration of Cu pillar bump, thus results in a large number of cavities generate in the solder IMC. These cavities expanded continuously and caused more and more obvious stress concentration in the IMC during the process of electromigration. This stress concentration reached above 68MPa, exceeding the fracture strength of Cu6 Sn5, which can be partly explained the fracture failure of Cu pillar bumps observed in the experiment.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122573304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654307
A. Aree-Uea, A. Mavinkurve, M. Soestbergen, R. Rongen
This paper assesses the feasibility of a shorter moisture soak when performing Moisture Sensitivity level assessments (MSLA) based on Level 1 (implying unlimited floor life before PCB assembly at the semiconductor user). The standard soak time during preconditioning for Level 1 is 168 h at 85°C/85% R.H. As microelectronics packages in the mobile and personal application space evolve into thinner and smaller products, it is often a matter of conjecture whether a shorter soak time is justified. Based purely on moisture diffusion kinetics, it can be shown that thinner (and smaller) packages will saturate much faster than older generation, thicker packages. This paper demonstrates a novel way to quantify damage response after MSL, to compare the effect of a shorter soak with the standard soak time. Although in some cases, a shorter soak time was shown to give a comparable damage response compared to that after the standard soak time, it is not always the case. However, based on a comparison with older generation, thicker packages, an alternative approach to define a shorter soak time for such packages is proposed.
{"title":"Accelerated Moisture Soak for Moisture Sensitivity Analysis Revisited","authors":"A. Aree-Uea, A. Mavinkurve, M. Soestbergen, R. Rongen","doi":"10.1109/EPTC.2018.8654307","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654307","url":null,"abstract":"This paper assesses the feasibility of a shorter moisture soak when performing Moisture Sensitivity level assessments (MSLA) based on Level 1 (implying unlimited floor life before PCB assembly at the semiconductor user). The standard soak time during preconditioning for Level 1 is 168 h at 85°C/85% R.H. As microelectronics packages in the mobile and personal application space evolve into thinner and smaller products, it is often a matter of conjecture whether a shorter soak time is justified. Based purely on moisture diffusion kinetics, it can be shown that thinner (and smaller) packages will saturate much faster than older generation, thicker packages. This paper demonstrates a novel way to quantify damage response after MSL, to compare the effect of a shorter soak with the standard soak time. Although in some cases, a shorter soak time was shown to give a comparable damage response compared to that after the standard soak time, it is not always the case. However, based on a comparison with older generation, thicker packages, an alternative approach to define a shorter soak time for such packages is proposed.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125106368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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