Pub Date : 2014-11-01DOI: 10.1109/ICSJ.2014.7009615
K. Otsuka, F. Fujii, Y. Akiyama, K. Hashimoto
Recent communication for cloud computing strongly requires one order magnitude wider bandwidth than current one, such as over 28Gbps in SerDes and Interlaken protocols. So the technology of IO transmitter and receiver becomes to one of key issues. In generally, those high bandwidth IO systems consume relative high power due to relate with fCV^2 by CMOS transistor and parasitic capacitances. Additional problem is that the transmitter needs to drive long wiring of mother board or plug-in board. Some adaptive equalizer and timing adjust circuits must be implemented in the IO circuit that subsequently requires power consumption. Our research has been aimed to save to quarter times power of current ones even in over 28Gbps band width operation. The key was for balanced concurrent design from chip design to board design and open termination circuit system. These will be mentioned here.
{"title":"IO interface for over 25Gbps operation with low power","authors":"K. Otsuka, F. Fujii, Y. Akiyama, K. Hashimoto","doi":"10.1109/ICSJ.2014.7009615","DOIUrl":"https://doi.org/10.1109/ICSJ.2014.7009615","url":null,"abstract":"Recent communication for cloud computing strongly requires one order magnitude wider bandwidth than current one, such as over 28Gbps in SerDes and Interlaken protocols. So the technology of IO transmitter and receiver becomes to one of key issues. In generally, those high bandwidth IO systems consume relative high power due to relate with fCV^2 by CMOS transistor and parasitic capacitances. Additional problem is that the transmitter needs to drive long wiring of mother board or plug-in board. Some adaptive equalizer and timing adjust circuits must be implemented in the IO circuit that subsequently requires power consumption. Our research has been aimed to save to quarter times power of current ones even in over 28Gbps band width operation. The key was for balanced concurrent design from chip design to board design and open termination circuit system. These will be mentioned here.","PeriodicalId":362502,"journal":{"name":"IEEE CPMT Symposium Japan 2014","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122145155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-01DOI: 10.1109/ICSJ.2014.7009634
Kousuke Nambara, Shoichi Umezu, H. Yotsuyanagi, M. Hashizume, Shyue-Kung Lu
An estimation method of a threshold value for electrical interconnect tests is proposed for detecting open defects at interconnects between dies in a 3D IC. Threshold values of a circuit made of our prototyping IC on a printed circuit board are derived by the estimation method. The results show us that resistive open defects whose resistance is larger than 16.1Ω can be detected with a threshold value estimated by the method.
{"title":"Threshold value estimation of electrical interconnect tests with scan FFs","authors":"Kousuke Nambara, Shoichi Umezu, H. Yotsuyanagi, M. Hashizume, Shyue-Kung Lu","doi":"10.1109/ICSJ.2014.7009634","DOIUrl":"https://doi.org/10.1109/ICSJ.2014.7009634","url":null,"abstract":"An estimation method of a threshold value for electrical interconnect tests is proposed for detecting open defects at interconnects between dies in a 3D IC. Threshold values of a circuit made of our prototyping IC on a printed circuit board are derived by the estimation method. The results show us that resistive open defects whose resistance is larger than 16.1Ω can be detected with a threshold value estimated by the method.","PeriodicalId":362502,"journal":{"name":"IEEE CPMT Symposium Japan 2014","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131647123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-01DOI: 10.1109/ICSJ.2014.7009632
T. Murayama, T. Sakuishi, Y. Morikawa, N. Tani, K. Saitou
TSV (Thru Silicon Via) application for 2.5D silicon interposers and 3D stacked devices is expected to realize a next-generation semiconductor device with high packaging density, power saving, and high-speed signal transmission, etc. Recently, discussions on long-term reliability of TSV has been triggered, the establishment of TSV integration technologies contribute to reliability is strongly requested to enable TSV packaging promote mass production. We have developed Si etching technology for high aspect ratio (>20) ultra low leak high-capacitor by using TSV production technology. As anisotropic deep silicon etching method, cycle etching and non-cycle etching method have been offered. Cycle etching is a general anisotropic Si etching method by cyclic etching of deposit (fluorocarbon polymer) and etching. In cycle etching, sidewall is protected by fluorocarbon polymer, periodic roughness appears on etched sidewall called “scallops”. On the other hand, non-cycle etching is without using fluorocarbon. In non-cycle etching, sidewall is protected by thin SiOX, non-cyclic etching process achieves smooth etched “scallops-free” sidewall. It is considered that the quality of etched sidewall influences capacitor reliability in process integration, it is necessary to investigate sidewall condition about both cycle etching and non-cycle/scallops-free etching because of differences of each etching process property; process gas, sidewall protection mechanism, scallops/scallopsfree, and so on. Therefore we conducted XPS analysis etched trench sidewall; depth of 10 um, 25 um, 40 um. It is showed that in cycle etching there are more residual F and C on etched sidewall due to fluorocarbon polymer than non-cycle without using fluorocarbon. It is considered that more residual F and C on etched sidewall might influence capacitor and TSV reliability.
{"title":"High aspect ratio TSV etching process for high-capacitor","authors":"T. Murayama, T. Sakuishi, Y. Morikawa, N. Tani, K. Saitou","doi":"10.1109/ICSJ.2014.7009632","DOIUrl":"https://doi.org/10.1109/ICSJ.2014.7009632","url":null,"abstract":"TSV (Thru Silicon Via) application for 2.5D silicon interposers and 3D stacked devices is expected to realize a next-generation semiconductor device with high packaging density, power saving, and high-speed signal transmission, etc. Recently, discussions on long-term reliability of TSV has been triggered, the establishment of TSV integration technologies contribute to reliability is strongly requested to enable TSV packaging promote mass production. We have developed Si etching technology for high aspect ratio (>20) ultra low leak high-capacitor by using TSV production technology. As anisotropic deep silicon etching method, cycle etching and non-cycle etching method have been offered. Cycle etching is a general anisotropic Si etching method by cyclic etching of deposit (fluorocarbon polymer) and etching. In cycle etching, sidewall is protected by fluorocarbon polymer, periodic roughness appears on etched sidewall called “scallops”. On the other hand, non-cycle etching is without using fluorocarbon. In non-cycle etching, sidewall is protected by thin SiOX, non-cyclic etching process achieves smooth etched “scallops-free” sidewall. It is considered that the quality of etched sidewall influences capacitor reliability in process integration, it is necessary to investigate sidewall condition about both cycle etching and non-cycle/scallops-free etching because of differences of each etching process property; process gas, sidewall protection mechanism, scallops/scallopsfree, and so on. Therefore we conducted XPS analysis etched trench sidewall; depth of 10 um, 25 um, 40 um. It is showed that in cycle etching there are more residual F and C on etched sidewall due to fluorocarbon polymer than non-cycle without using fluorocarbon. It is considered that more residual F and C on etched sidewall might influence capacitor and TSV reliability.","PeriodicalId":362502,"journal":{"name":"IEEE CPMT Symposium Japan 2014","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129023890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-01DOI: 10.1109/ICSJ.2014.7009595
N. Morita, R. Sawada
Integrating and miniaturizing optical equipment confers many advantages: low weight, low power consumption, portability, and ease to embed. However, integration and miniaturization presents difficulties because optical elements in the equipment need precise alignment and packaging. We have previously developed several types of optical micro-sensors, including micro-electromechanical systems (MEMS) blood flow sensors, micro-optical encoders, and a micro-laser Doppler velocimeter. Cavities containing empty space and mirrors, through-silicon vias, and three-dimensional electrodes enable our sensors achieve wafer-level packaging of the optical MEMS chip. We introduce the integration of our developed miniaturized optical sensors and several applications.
{"title":"Optical micro sensors integration and application","authors":"N. Morita, R. Sawada","doi":"10.1109/ICSJ.2014.7009595","DOIUrl":"https://doi.org/10.1109/ICSJ.2014.7009595","url":null,"abstract":"Integrating and miniaturizing optical equipment confers many advantages: low weight, low power consumption, portability, and ease to embed. However, integration and miniaturization presents difficulties because optical elements in the equipment need precise alignment and packaging. We have previously developed several types of optical micro-sensors, including micro-electromechanical systems (MEMS) blood flow sensors, micro-optical encoders, and a micro-laser Doppler velocimeter. Cavities containing empty space and mirrors, through-silicon vias, and three-dimensional electrodes enable our sensors achieve wafer-level packaging of the optical MEMS chip. We introduce the integration of our developed miniaturized optical sensors and several applications.","PeriodicalId":362502,"journal":{"name":"IEEE CPMT Symposium Japan 2014","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129070075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-01-13DOI: 10.1109/ICSJ.2014.7009617
T. Yamaguchi, Kanae Kurita, T. Sudo
Power supply noise is a serious issue for advanced CMOS LSIs and systems, since the performance of LSI chip is becoming more sensitive to power supply fluctuation under the lower power supply voltage. Because power supply noises are strongly related to the anti-resonance peak frequency in the total power distribution network (PDN), suppressing the anti-resonance peak is one of the most important design concerns. In this paper, the on-board snubber circuits (RC series circuits) has been studied to suppress the anti-resonance peak. The optimal circuit parameters of the on-board snubber circuits such as capacitance (Csnb) and resistance (Rdmp) were derived for quad flat package (QFP) and ball grid array (BGA) to effectively suppress the anti-resonance peak of the total PDN impedance. As a result, the settling time of power supply noises were greatly decreased. Furthermore, clock frequency dependency of power supply noise was also significantly decreased.
{"title":"On-board snubber circuit for damping of anti-resonance peak in total PDN","authors":"T. Yamaguchi, Kanae Kurita, T. Sudo","doi":"10.1109/ICSJ.2014.7009617","DOIUrl":"https://doi.org/10.1109/ICSJ.2014.7009617","url":null,"abstract":"Power supply noise is a serious issue for advanced CMOS LSIs and systems, since the performance of LSI chip is becoming more sensitive to power supply fluctuation under the lower power supply voltage. Because power supply noises are strongly related to the anti-resonance peak frequency in the total power distribution network (PDN), suppressing the anti-resonance peak is one of the most important design concerns. In this paper, the on-board snubber circuits (RC series circuits) has been studied to suppress the anti-resonance peak. The optimal circuit parameters of the on-board snubber circuits such as capacitance (Csnb) and resistance (Rdmp) were derived for quad flat package (QFP) and ball grid array (BGA) to effectively suppress the anti-resonance peak of the total PDN impedance. As a result, the settling time of power supply noises were greatly decreased. Furthermore, clock frequency dependency of power supply noise was also significantly decreased.","PeriodicalId":362502,"journal":{"name":"IEEE CPMT Symposium Japan 2014","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129730805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-01-13DOI: 10.1109/ICSJ.2014.7009614
Y. Toyota
For suppressing the power-bus resonance at higher frequencies, which causes propagation of electromagnetic noise and detraction of power integrity, we proposed a lossy resonator filter with frequency selectivity and low loss. To suppress noise propagation in the power-ground plane pair of a printed circuit board (PCB) at high frequencies (over 1 GHz), a ferrite-covered open stub was formed on a PCB as a lossy resonator filter. Its characteristics were verified by not only full-wave simulation but also measurement using a vector network analyzer. The simulation and measurement results show that the noise in the power bus of the PCB at frequencies over 1 GHz is suppressed. Through a series of investigations focusing on the input impedance characteristics, this paper clarified that low impedance of the open stub around resonant frequency helps prevent the impedance of the power-ground plane pair from increasing due to parallel plate resonances to achieve power-bus noise reduction.
{"title":"Power-bus noise reduction using ferrite-covered open stub in printed circuit board","authors":"Y. Toyota","doi":"10.1109/ICSJ.2014.7009614","DOIUrl":"https://doi.org/10.1109/ICSJ.2014.7009614","url":null,"abstract":"For suppressing the power-bus resonance at higher frequencies, which causes propagation of electromagnetic noise and detraction of power integrity, we proposed a lossy resonator filter with frequency selectivity and low loss. To suppress noise propagation in the power-ground plane pair of a printed circuit board (PCB) at high frequencies (over 1 GHz), a ferrite-covered open stub was formed on a PCB as a lossy resonator filter. Its characteristics were verified by not only full-wave simulation but also measurement using a vector network analyzer. The simulation and measurement results show that the noise in the power bus of the PCB at frequencies over 1 GHz is suppressed. Through a series of investigations focusing on the input impedance characteristics, this paper clarified that low impedance of the open stub around resonant frequency helps prevent the impedance of the power-ground plane pair from increasing due to parallel plate resonances to achieve power-bus noise reduction.","PeriodicalId":362502,"journal":{"name":"IEEE CPMT Symposium Japan 2014","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128486842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-01-13DOI: 10.1109/ICSJ.2014.7009635
Asami Takahashi, T. Ishigure
We fabricate graded index (GI) circular core multimode polymer optical waveguides with 90° bending using the Mosquito method, and demonstrate low bending loss even if the bend radius is as small as 1 mm.
{"title":"Fabrication for low-loss polymer optical waveguides with 90° bending using the Mosquito method","authors":"Asami Takahashi, T. Ishigure","doi":"10.1109/ICSJ.2014.7009635","DOIUrl":"https://doi.org/10.1109/ICSJ.2014.7009635","url":null,"abstract":"We fabricate graded index (GI) circular core multimode polymer optical waveguides with 90° bending using the Mosquito method, and demonstrate low bending loss even if the bend radius is as small as 1 mm.","PeriodicalId":362502,"journal":{"name":"IEEE CPMT Symposium Japan 2014","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124742833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-01-13DOI: 10.1109/ICSJ.2014.7009616
Masahiro Terasaki, Yuta Oohashi, Y. Masuyama, T. Sudo
DC/DC converters are widely used to produce various power supply voltages required for various electronic components on a board. Though DC/DC converter is more efficient than the linear regulator is, however, the switching noise becomes larger with the increase of the switching frequency. In particular, ringing noises at the sharp rising edge of the switching waveform generated by the effect of the parasitic inductance becomes a serious issue. This noise spreads out to the whole circuit board, and then generates electromagnetic interference (EMI), which often causes a malfunction of the electronic systems. In this paper, the methods to accurately reproduce the switching waveforms and to reduce ringing noises and resulting EMI from DC/DC converters were investigated. For this purpose, several evaluation boards were designed, and total electrical model was constructed by taking into account the parasitic inductances of traces on a board. First, frequency-domain analysis for the switching loop of the DC/DC converters was executed to find the optimum condition to suppress ringing noise effectively. Next, time-domain simulation was executed by considering the recovering time of MOS reverse current, which is not provided from device vendors. Finally, measured switching waveforms were well correlated with the simulated ones, and the optimal condition to suppress the ringing noise.
{"title":"Measurement and modeling for MOS reverse current of switching DC/DC converter","authors":"Masahiro Terasaki, Yuta Oohashi, Y. Masuyama, T. Sudo","doi":"10.1109/ICSJ.2014.7009616","DOIUrl":"https://doi.org/10.1109/ICSJ.2014.7009616","url":null,"abstract":"DC/DC converters are widely used to produce various power supply voltages required for various electronic components on a board. Though DC/DC converter is more efficient than the linear regulator is, however, the switching noise becomes larger with the increase of the switching frequency. In particular, ringing noises at the sharp rising edge of the switching waveform generated by the effect of the parasitic inductance becomes a serious issue. This noise spreads out to the whole circuit board, and then generates electromagnetic interference (EMI), which often causes a malfunction of the electronic systems. In this paper, the methods to accurately reproduce the switching waveforms and to reduce ringing noises and resulting EMI from DC/DC converters were investigated. For this purpose, several evaluation boards were designed, and total electrical model was constructed by taking into account the parasitic inductances of traces on a board. First, frequency-domain analysis for the switching loop of the DC/DC converters was executed to find the optimum condition to suppress ringing noise effectively. Next, time-domain simulation was executed by considering the recovering time of MOS reverse current, which is not provided from device vendors. Finally, measured switching waveforms were well correlated with the simulated ones, and the optimal condition to suppress the ringing noise.","PeriodicalId":362502,"journal":{"name":"IEEE CPMT Symposium Japan 2014","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121605022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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