Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753554
S. C. Hilla
The development of multichip modules (MCMs) is confronted by many challenges in the area of testing. This paper details the solutions to some of these challenges which resulted in the successful development of a wafer scale, silicon-on silicon multichip module. The end product is a 4" silicon substrate mounted on a SEM-E frame. The SEM-E module was designed to perform image processing and is one of many modules making up a high performance image processing computer. Through the extensive use of boundary scan to perform both interconnect testing and functional testing, the wafer scale MCM was inserted into the target system rack and worked correctly the first time.
{"title":"Boundary Scan Techniques in an Mcm-D Application","authors":"S. C. Hilla","doi":"10.1109/ICMCM.1994.753554","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753554","url":null,"abstract":"The development of multichip modules (MCMs) is confronted by many challenges in the area of testing. This paper details the solutions to some of these challenges which resulted in the successful development of a wafer scale, silicon-on silicon multichip module. The end product is a 4\" silicon substrate mounted on a SEM-E frame. The SEM-E module was designed to perform image processing and is one of many modules making up a high performance image processing computer. Through the extensive use of boundary scan to perform both interconnect testing and functional testing, the wafer scale MCM was inserted into the target system rack and worked correctly the first time.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"14 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124191448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753542
R. Kambe, R. Imai, T. Takada, M. Arakawa, M. Kuroda
It is well established that thin film capacitors have good electrical characteristics and for that reason are often used in high frequency applications. Unfortunately, it is also very difficult to form thin film capacitors on the relatively rough surface of cofired ceramics. We have investigated planarization of bottom capacitive electrodes which must make direct contact with a cofired ceramic surface, and adjustment and control of the T.C.E. difference between high dielectric constant material and the bass MCM ceramic substrate. Combining thin film capacitors with MCM substrates can result in high frequency decoupling capacitors (with 100X the capacitance of comparable cofired thin layer alumina constructions); space saving, and significant improvements in performance over conventional discrete chip capacitors.
{"title":"Mcm Substrate with High Capacitance","authors":"R. Kambe, R. Imai, T. Takada, M. Arakawa, M. Kuroda","doi":"10.1109/ICMCM.1994.753542","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753542","url":null,"abstract":"It is well established that thin film capacitors have good electrical characteristics and for that reason are often used in high frequency applications. Unfortunately, it is also very difficult to form thin film capacitors on the relatively rough surface of cofired ceramics. We have investigated planarization of bottom capacitive electrodes which must make direct contact with a cofired ceramic surface, and adjustment and control of the T.C.E. difference between high dielectric constant material and the bass MCM ceramic substrate. Combining thin film capacitors with MCM substrates can result in high frequency decoupling capacitors (with 100X the capacitance of comparable cofired thin layer alumina constructions); space saving, and significant improvements in performance over conventional discrete chip capacitors.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124212396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753568
D. Tuckerman, D. Benson, H. Moore, J. Horner, J. Gibbons
ROSS Technology, Inc., and nCHIP, Inc., have successfully produced a second-generation SPARC processor multichip module (MCM). Based on ROSS's hyperSPARC/sup TM/ architecture, the module sets a new standard for performance in the SPARC marketplace. The MCM is packaged in a 45mm-square 256-lead, ceramic quad flatpack carrier, and is footprint-compatible with ROSS' current SPARC MCM, the CYM6111. However, the new module runs at clock speeds in excess of 80 MHz, more than twice that of the CYM6111, and will offer 3-5 times the performance in most applications. The full module contains six CMOS chips: a CPU containing both integer and floating point ALUs, a cache controller/memory management unit, and four cache RAM chips. Each chip uses both 3.3 and 5.0 volt power supplies, so the MCM substrate incorporates a split power plane. The chips are interconnected using nCHIP's nC1000 substrate technology which incorporates aluminum interconnect, SiO/sub 2/ dielectric, and an integral decoupling capacitor. ROSS's multichip design strategy does not depend on massive integration or complex fabrication processes; similarly, the nCHIP nC1000 substrate process is based on a robust, IC-like technology. This combination provides excellent manufacturability and allows a fast production ramp into high volume.
{"title":"A High-Performance Second-Generation Sparc Mcm","authors":"D. Tuckerman, D. Benson, H. Moore, J. Horner, J. Gibbons","doi":"10.1109/ICMCM.1994.753568","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753568","url":null,"abstract":"ROSS Technology, Inc., and nCHIP, Inc., have successfully produced a second-generation SPARC processor multichip module (MCM). Based on ROSS's hyperSPARC/sup TM/ architecture, the module sets a new standard for performance in the SPARC marketplace. The MCM is packaged in a 45mm-square 256-lead, ceramic quad flatpack carrier, and is footprint-compatible with ROSS' current SPARC MCM, the CYM6111. However, the new module runs at clock speeds in excess of 80 MHz, more than twice that of the CYM6111, and will offer 3-5 times the performance in most applications. The full module contains six CMOS chips: a CPU containing both integer and floating point ALUs, a cache controller/memory management unit, and four cache RAM chips. Each chip uses both 3.3 and 5.0 volt power supplies, so the MCM substrate incorporates a split power plane. The chips are interconnected using nCHIP's nC1000 substrate technology which incorporates aluminum interconnect, SiO/sub 2/ dielectric, and an integral decoupling capacitor. ROSS's multichip design strategy does not depend on massive integration or complex fabrication processes; similarly, the nCHIP nC1000 substrate process is based on a robust, IC-like technology. This combination provides excellent manufacturability and allows a fast production ramp into high volume.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128234345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753617
R. Pearson
A new approach to build multi-chip modules (MCMs) using active silicon substrate (ASIS) technology is being developed by Lockheed for future sensor signal processing and control applications. The ASIS MCM inherently offers a functional platform versus other approaches using a passive nonfunctional substrate. The Lockheed ASIS design uses benzocyclobutene (BCB) for a low dielectric and copper for interconnect over an active substrate. Support chips are attached to the interconnect over the substrate by solder bumps. This provides a versatile manufacturing concept for easy rework. Bare die testing and bum-in of support chips should eliminate most rework. The result is a dense, high performance, three-dimensional MCM of closely placed functional elements. Unique architectures are possible with optimized active substrates and support chips, but this approach also allows MCMs to be developed sooner with standard integrated circuits.
{"title":"Active Silicon Substrate Multi-Chip Module Technology for Sensor Signal Processing and Control","authors":"R. Pearson","doi":"10.1109/ICMCM.1994.753617","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753617","url":null,"abstract":"A new approach to build multi-chip modules (MCMs) using active silicon substrate (ASIS) technology is being developed by Lockheed for future sensor signal processing and control applications. The ASIS MCM inherently offers a functional platform versus other approaches using a passive nonfunctional substrate. The Lockheed ASIS design uses benzocyclobutene (BCB) for a low dielectric and copper for interconnect over an active substrate. Support chips are attached to the interconnect over the substrate by solder bumps. This provides a versatile manufacturing concept for easy rework. Bare die testing and bum-in of support chips should eliminate most rework. The result is a dense, high performance, three-dimensional MCM of closely placed functional elements. Unique architectures are possible with optimized active substrates and support chips, but this approach also allows MCMs to be developed sooner with standard integrated circuits.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124702674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753610
B. Miller, N. Volkringer, L. Su, Y.-M. Ting, M. Loo, R. Kumar, B. Smith
A 50 MHz processor multichip module, comprised of OEM die bumped for flip chip interconnect, was designed and fabricated for Sun Microsystems, Inc. by IBM Microelectronics. The MCM was implemented in a 44mm x 64mm MCM-C package with a pin grid array (PGA) module attachment to a card designed and fabricated by Sun Microsystems, Inc.. The MCM design was accepted from Sun Microsystems, Inc. via a completed logic design into the IBM Packaging Foundry using Cadence Allegro 7.0. Application achievements include bumping die on an OEM wafer after signal redistribution for flip chip interconnect and the release of an MCM design into the IBM Foundry using Cadence Allegro 7.0 design system. The functional performance testing will be provided by Sun Microsystems, Inc.. This paper discusses all aspects of the MCM development including physical and electrical design, rapid prototype build, thermal management, module assembly, module interconnect test and module functional performance.
{"title":"A 50mhz Multichip Processor Module With Flip Chip Technology","authors":"B. Miller, N. Volkringer, L. Su, Y.-M. Ting, M. Loo, R. Kumar, B. Smith","doi":"10.1109/ICMCM.1994.753610","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753610","url":null,"abstract":"A 50 MHz processor multichip module, comprised of OEM die bumped for flip chip interconnect, was designed and fabricated for Sun Microsystems, Inc. by IBM Microelectronics. The MCM was implemented in a 44mm x 64mm MCM-C package with a pin grid array (PGA) module attachment to a card designed and fabricated by Sun Microsystems, Inc.. The MCM design was accepted from Sun Microsystems, Inc. via a completed logic design into the IBM Packaging Foundry using Cadence Allegro 7.0. Application achievements include bumping die on an OEM wafer after signal redistribution for flip chip interconnect and the release of an MCM design into the IBM Foundry using Cadence Allegro 7.0 design system. The functional performance testing will be provided by Sun Microsystems, Inc.. This paper discusses all aspects of the MCM development including physical and electrical design, rapid prototype build, thermal management, module assembly, module interconnect test and module functional performance.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115993604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753572
C. Murphy, R. Kodnani, D. Peterson
The goal of the Reliability without Hermeticity (RwoH) Project is to find non-hermetic coatings for use on MCMs. As a means of down-selecting coating materials, Sandia ATC01 test chips in 40 pin DIPs were coated with non-hermetic, polymer materials, including silicone gel, filled epoxy, and polyimide. After preconditioning through temperature cycling and atmosphere, the parts were subjected to one of three different temperature, humidity, and bias conditions: HAST (140/spl deg/C, 85% RH, +40V), 85/85 (85/spl deg/C, 85% RH, +40V), or PCT (121/spl deg/C, 99.6% RH). No universal relationship between lifetime in HAST and 85/85 testing was observed-the effects appear to be material dependent. Electrical test data suggest that failures on coated parts (with standard SiN chip passivation) do not occur on die circuitry (triple tracks) and instead occur on bond-wires and bond-pads.
{"title":"Evaluation of Non-Hermetic Coatings for Mcm Applications through Hast, 85/85 and Pct","authors":"C. Murphy, R. Kodnani, D. Peterson","doi":"10.1109/ICMCM.1994.753572","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753572","url":null,"abstract":"The goal of the Reliability without Hermeticity (RwoH) Project is to find non-hermetic coatings for use on MCMs. As a means of down-selecting coating materials, Sandia ATC01 test chips in 40 pin DIPs were coated with non-hermetic, polymer materials, including silicone gel, filled epoxy, and polyimide. After preconditioning through temperature cycling and atmosphere, the parts were subjected to one of three different temperature, humidity, and bias conditions: HAST (140/spl deg/C, 85% RH, +40V), 85/85 (85/spl deg/C, 85% RH, +40V), or PCT (121/spl deg/C, 99.6% RH). No universal relationship between lifetime in HAST and 85/85 testing was observed-the effects appear to be material dependent. Electrical test data suggest that failures on coated parts (with standard SiN chip passivation) do not occur on die circuitry (triple tracks) and instead occur on bond-wires and bond-pads.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122969074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753573
T. Hodge, S. Bidstrup, P. Kohl, J. Lee, M. Allen
In MCM-D applications, interlayer dielectrics separate and insulate metal conductors to form a threedimensional interconnection structure. Due to the three-dimensional nature of these structures, the electrical and mechanical properties of the dielectric materials must be known in all directions for proper device design. The most commonly used polymer in microelectronics, polyimide, exists in formulations which have been shown to have a high degree of orientation and exhibit anisotropic properties. mechanical proprties of thin films is diftidt due to the high resolution required to measure the small thickness changes. Existing techniques require either stacked thin films or a single cast thick film of 100 micrometers or more to achieve dimensionat changes large enough to be measwabie.740 In addition, most existing techniques require removing a large area of film, if not the whole film, from a supporting substrate to perfom the measurement. These techniques neglect the effects of the dielectric-substrate interaction, such as Poisson's effm and adhesive effects. Since most MCM-D structures utilize thin films adhered to a substrate, the measured through-plane CTEs from these other techniques may not reflect the true thermal expansion expected in real devices. Measurement of through-plane
{"title":"An In-Situ Measurement Technique for Through-Plane Thermal Properties of Thin Dielectric Films","authors":"T. Hodge, S. Bidstrup, P. Kohl, J. Lee, M. Allen","doi":"10.1109/ICMCM.1994.753573","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753573","url":null,"abstract":"In MCM-D applications, interlayer dielectrics separate and insulate metal conductors to form a threedimensional interconnection structure. Due to the three-dimensional nature of these structures, the electrical and mechanical properties of the dielectric materials must be known in all directions for proper device design. The most commonly used polymer in microelectronics, polyimide, exists in formulations which have been shown to have a high degree of orientation and exhibit anisotropic properties. mechanical proprties of thin films is diftidt due to the high resolution required to measure the small thickness changes. Existing techniques require either stacked thin films or a single cast thick film of 100 micrometers or more to achieve dimensionat changes large enough to be measwabie.740 In addition, most existing techniques require removing a large area of film, if not the whole film, from a supporting substrate to perfom the measurement. These techniques neglect the effects of the dielectric-substrate interaction, such as Poisson's effm and adhesive effects. Since most MCM-D structures utilize thin films adhered to a substrate, the measured through-plane CTEs from these other techniques may not reflect the true thermal expansion expected in real devices. Measurement of through-plane","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122162398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753529
P. Harper
When selecting die attach material for hermetic packaging the user has been limited to two options; gold-silicon eutectic ribbon and silver/glass paste. Recently, new developments in high temperature polymer technology have opened up new options for hermetic die attach. New high temperature thermoplastic adhesives have been developed that can be bonded in seconds and offer the ability to rework the die attach by re-melting the adhesive. The process window and functional performance of two thermoplastic die attach materials were evaluated for their suitability for use in solder sealed cofired pin grid array ceramic and glass sealed ceramic quad flat packages. The process parameters of Time, Temperature, Pressure, and Scrub were investigated to determine the optimal manufacturing conditions.
{"title":"Thermoplastic Die Attach for Hermetic Packaging","authors":"P. Harper","doi":"10.1109/ICMCM.1994.753529","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753529","url":null,"abstract":"When selecting die attach material for hermetic packaging the user has been limited to two options; gold-silicon eutectic ribbon and silver/glass paste. Recently, new developments in high temperature polymer technology have opened up new options for hermetic die attach. New high temperature thermoplastic adhesives have been developed that can be bonded in seconds and offer the ability to rework the die attach by re-melting the adhesive. The process window and functional performance of two thermoplastic die attach materials were evaluated for their suitability for use in solder sealed cofired pin grid array ceramic and glass sealed ceramic quad flat packages. The process parameters of Time, Temperature, Pressure, and Scrub were investigated to determine the optimal manufacturing conditions.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"026 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128992497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753591
R. Fillion, R.J. Wojnarowski, W. Bicknell, W. Daum, G. Forman
The GE/Martin Marietta/Texas Instruments embedded chip multichip technology was developed for high performance digital circuits used in aerospace applications. The HDI process involves the placement of bare chips into cavities formed into a base substrate, lamination of a polymer dielectric film over the chips and the substrate, and the formation of vias and interconnect metallization on the polymer film. Multiple levels of interconnect are formed by repeating the film lamination, via formation and metallization steps. The direct metallization to the chip I/O pads eliminates the need for normal chip I/O wire bonds, TAB, or solder bumps. The elimination of these chip connections and the high electrical performance of the polymer/copper interconnect structure result in the superior speed of such embedded chip MCMs. The technology also features high current carrying capability, high reliability in harsh mechanical and thermal environments and high thermal dissipation capability. The inherently high performance features of the embedded chip MCM technology have been exploited in non-digital electronics such as: mixed analog and digital circuits, power conversion and conditioning, microwave transmit and receive (TIR) modules, and optoelectronic modules. The ability of embedded chip HDI to fully shield high frequency devices in a module from other components and the complete elimination of the discontinuities associated with chip I/O attach, makes it ideal for mixed mode operation. Current non digital examples making use of this unique capability are a >400 MHz GaAs 128 X 128 crosspoint switch, a 50 Watt, 85% efficient DC-to-DC converter, a 14 Bit voice / data modem circuit, and a 54 channel 12 Bit instrumentation A/D converter module. All of these unique examples of non-digital extensions of the embedded chip HDI MCM interconnect process will be described along with their unique features, processing and/or structures.
{"title":"Non-Digital Extensions of an Embedded Chip MCM Technology","authors":"R. Fillion, R.J. Wojnarowski, W. Bicknell, W. Daum, G. Forman","doi":"10.1109/ICMCM.1994.753591","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753591","url":null,"abstract":"The GE/Martin Marietta/Texas Instruments embedded chip multichip technology was developed for high performance digital circuits used in aerospace applications. The HDI process involves the placement of bare chips into cavities formed into a base substrate, lamination of a polymer dielectric film over the chips and the substrate, and the formation of vias and interconnect metallization on the polymer film. Multiple levels of interconnect are formed by repeating the film lamination, via formation and metallization steps. The direct metallization to the chip I/O pads eliminates the need for normal chip I/O wire bonds, TAB, or solder bumps. The elimination of these chip connections and the high electrical performance of the polymer/copper interconnect structure result in the superior speed of such embedded chip MCMs. The technology also features high current carrying capability, high reliability in harsh mechanical and thermal environments and high thermal dissipation capability. The inherently high performance features of the embedded chip MCM technology have been exploited in non-digital electronics such as: mixed analog and digital circuits, power conversion and conditioning, microwave transmit and receive (TIR) modules, and optoelectronic modules. The ability of embedded chip HDI to fully shield high frequency devices in a module from other components and the complete elimination of the discontinuities associated with chip I/O attach, makes it ideal for mixed mode operation. Current non digital examples making use of this unique capability are a >400 MHz GaAs 128 X 128 crosspoint switch, a 50 Watt, 85% efficient DC-to-DC converter, a 14 Bit voice / data modem circuit, and a 54 channel 12 Bit instrumentation A/D converter module. All of these unique examples of non-digital extensions of the embedded chip HDI MCM interconnect process will be described along with their unique features, processing and/or structures.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117340497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753566
J. Norén, P. Brofman
A complex hybrid (mixed interconnect) MCM is described wherein wire bonded and flip chipped IC's are attached to a thin film MCM. Additionally, a TAB IC and soldered discretes are also attached. For purpose of card-level assembly, the populated thin film MCM is mechanically, thermally, and electrically enclosed in a large alumina cavity-down PGA, and hermetically sealed. The design concept enables each of the inter connection schemes to be assessed either separately or synergistically. While the design point is unlikely to be used in production, the test vehicle offers a remarkable opportunity to assess viable combinations of hybrid MCM technology that are planned for production in various forms. Several of the technology challenges associated with such hybridization at the MCM level are discussed, along with preliminary results of stress testing from this vehicle. Feasability for combining flip chip, wire bond, TAB, and soldered discretes on a thin film carrier is demonstrated.
{"title":"Interconnection Considerations for a Hybrid Mcm","authors":"J. Norén, P. Brofman","doi":"10.1109/ICMCM.1994.753566","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753566","url":null,"abstract":"A complex hybrid (mixed interconnect) MCM is described wherein wire bonded and flip chipped IC's are attached to a thin film MCM. Additionally, a TAB IC and soldered discretes are also attached. For purpose of card-level assembly, the populated thin film MCM is mechanically, thermally, and electrically enclosed in a large alumina cavity-down PGA, and hermetically sealed. The design concept enables each of the inter connection schemes to be assessed either separately or synergistically. While the design point is unlikely to be used in production, the test vehicle offers a remarkable opportunity to assess viable combinations of hybrid MCM technology that are planned for production in various forms. Several of the technology challenges associated with such hybridization at the MCM level are discussed, along with preliminary results of stress testing from this vehicle. Feasability for combining flip chip, wire bond, TAB, and soldered discretes on a thin film carrier is demonstrated.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123347948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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