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Boundary Scan Techniques in an Mcm-D Application Mcm-D应用中的边界扫描技术
Pub Date : 1994-04-13 DOI: 10.1109/ICMCM.1994.753554
S. C. Hilla
The development of multichip modules (MCMs) is confronted by many challenges in the area of testing. This paper details the solutions to some of these challenges which resulted in the successful development of a wafer scale, silicon-on silicon multichip module. The end product is a 4" silicon substrate mounted on a SEM-E frame. The SEM-E module was designed to perform image processing and is one of many modules making up a high performance image processing computer. Through the extensive use of boundary scan to perform both interconnect testing and functional testing, the wafer scale MCM was inserted into the target system rack and worked correctly the first time.
多芯片模块(mcm)的发展在测试领域面临着许多挑战。本文详细介绍了这些挑战的解决方案,从而成功开发了晶圆规模的硅上硅多芯片模块。最终产品是安装在SEM-E框架上的4英寸硅衬底。SEM-E模块设计用于执行图像处理,是组成高性能图像处理计算机的众多模块之一。通过广泛使用边界扫描来执行互连测试和功能测试,晶圆级MCM被插入目标系统机架并首次正常工作。
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引用次数: 2
Mcm Substrate with High Capacitance 高电容的Mcm衬底
Pub Date : 1994-04-13 DOI: 10.1109/ICMCM.1994.753542
R. Kambe, R. Imai, T. Takada, M. Arakawa, M. Kuroda
It is well established that thin film capacitors have good electrical characteristics and for that reason are often used in high frequency applications. Unfortunately, it is also very difficult to form thin film capacitors on the relatively rough surface of cofired ceramics. We have investigated planarization of bottom capacitive electrodes which must make direct contact with a cofired ceramic surface, and adjustment and control of the T.C.E. difference between high dielectric constant material and the bass MCM ceramic substrate. Combining thin film capacitors with MCM substrates can result in high frequency decoupling capacitors (with 100X the capacitance of comparable cofired thin layer alumina constructions); space saving, and significant improvements in performance over conventional discrete chip capacitors.
众所周知,薄膜电容器具有良好的电特性,因此常用于高频应用。不幸的是,在相对粗糙的共烧陶瓷表面上形成薄膜电容器也是非常困难的。我们研究了必须与共烧陶瓷表面直接接触的底部电容电极的平面化,以及高介电常数材料与低MCM陶瓷衬底之间的T.C.E.差的调节和控制。将薄膜电容器与MCM衬底相结合可以产生高频去耦电容器(具有可比共烧薄层氧化铝结构的100倍电容);节省空间,并显著提高性能优于传统的分立芯片电容器。
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引用次数: 17
A High-Performance Second-Generation Sparc Mcm 高性能第二代Sparc Mcm
Pub Date : 1994-04-13 DOI: 10.1109/ICMCM.1994.753568
D. Tuckerman, D. Benson, H. Moore, J. Horner, J. Gibbons
ROSS Technology, Inc., and nCHIP, Inc., have successfully produced a second-generation SPARC processor multichip module (MCM). Based on ROSS's hyperSPARC/sup TM/ architecture, the module sets a new standard for performance in the SPARC marketplace. The MCM is packaged in a 45mm-square 256-lead, ceramic quad flatpack carrier, and is footprint-compatible with ROSS' current SPARC MCM, the CYM6111. However, the new module runs at clock speeds in excess of 80 MHz, more than twice that of the CYM6111, and will offer 3-5 times the performance in most applications. The full module contains six CMOS chips: a CPU containing both integer and floating point ALUs, a cache controller/memory management unit, and four cache RAM chips. Each chip uses both 3.3 and 5.0 volt power supplies, so the MCM substrate incorporates a split power plane. The chips are interconnected using nCHIP's nC1000 substrate technology which incorporates aluminum interconnect, SiO/sub 2/ dielectric, and an integral decoupling capacitor. ROSS's multichip design strategy does not depend on massive integration or complex fabrication processes; similarly, the nCHIP nC1000 substrate process is based on a robust, IC-like technology. This combination provides excellent manufacturability and allows a fast production ramp into high volume.
ROSS科技公司和nCHIP公司成功生产了第二代SPARC处理器多芯片模块(MCM)。该模块基于ROSS的hyperSPARC/sup TM/架构,为SPARC市场的性能设定了新的标准。MCM封装在一个45mm平方的256引线陶瓷四平面包装载体中,与ROSS目前的SPARC MCM CYM6111兼容。然而,新模块的时钟速度超过80 MHz,是CYM6111的两倍多,并且在大多数应用中提供3-5倍的性能。整个模块包含六个CMOS芯片:一个包含整数和浮点alu的CPU,一个缓存控制器/内存管理单元,以及四个缓存RAM芯片。每个芯片都使用3.3伏和5.0伏电源,因此MCM基板包含一个分离的电源平面。这些芯片采用nCHIP的nC1000衬底技术互连,该技术集成了铝互连,SiO/sub 2/介电和集成去耦电容器。ROSS的多芯片设计策略不依赖于大规模集成或复杂的制造工艺;同样,nCHIP nC1000基板工艺基于强大的类似ic的技术。这种组合提供了出色的可制造性,并允许快速生产进入大批量。
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引用次数: 6
Active Silicon Substrate Multi-Chip Module Technology for Sensor Signal Processing and Control 传感器信号处理与控制的有源硅衬底多芯片模块技术
Pub Date : 1994-04-13 DOI: 10.1109/ICMCM.1994.753617
R. Pearson
A new approach to build multi-chip modules (MCMs) using active silicon substrate (ASIS) technology is being developed by Lockheed for future sensor signal processing and control applications. The ASIS MCM inherently offers a functional platform versus other approaches using a passive nonfunctional substrate. The Lockheed ASIS design uses benzocyclobutene (BCB) for a low dielectric and copper for interconnect over an active substrate. Support chips are attached to the interconnect over the substrate by solder bumps. This provides a versatile manufacturing concept for easy rework. Bare die testing and bum-in of support chips should eliminate most rework. The result is a dense, high performance, three-dimensional MCM of closely placed functional elements. Unique architectures are possible with optimized active substrates and support chips, but this approach also allows MCMs to be developed sooner with standard integrated circuits.
洛克希德公司正在开发一种利用有源硅衬底(ASIS)技术构建多芯片模块(mcm)的新方法,用于未来的传感器信号处理和控制应用。与使用无源无功能基板的其他方法相比,ASIS MCM本身提供了一个功能平台。洛克希德ASIS设计使用苯并环丁烯(BCB)作为低介电介质,铜作为在有源衬底上的互连。支撑芯片通过焊料凸起连接到衬底上的互连上。这为易于返工提供了一个通用的制造概念。裸模测试和支持芯片的磨合应该可以消除大部分的返工。其结果是一个密集,高性能,三维MCM紧密放置的功能元素。通过优化的有源基板和支持芯片,可以实现独特的架构,但这种方法也允许mcm更快地与标准集成电路一起开发。
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引用次数: 1
A 50mhz Multichip Processor Module With Flip Chip Technology 采用倒装芯片技术的50mhz多芯片处理器模块
Pub Date : 1994-04-13 DOI: 10.1109/ICMCM.1994.753610
B. Miller, N. Volkringer, L. Su, Y.-M. Ting, M. Loo, R. Kumar, B. Smith
A 50 MHz processor multichip module, comprised of OEM die bumped for flip chip interconnect, was designed and fabricated for Sun Microsystems, Inc. by IBM Microelectronics. The MCM was implemented in a 44mm x 64mm MCM-C package with a pin grid array (PGA) module attachment to a card designed and fabricated by Sun Microsystems, Inc.. The MCM design was accepted from Sun Microsystems, Inc. via a completed logic design into the IBM Packaging Foundry using Cadence Allegro 7.0. Application achievements include bumping die on an OEM wafer after signal redistribution for flip chip interconnect and the release of an MCM design into the IBM Foundry using Cadence Allegro 7.0 design system. The functional performance testing will be provided by Sun Microsystems, Inc.. This paper discusses all aspects of the MCM development including physical and electrical design, rapid prototype build, thermal management, module assembly, module interconnect test and module functional performance.
IBM微电子公司为Sun Microsystems公司设计并制造了一种50 MHz处理器多芯片模块,该模块由用于倒装芯片互连的OEM凸模组成。MCM在一个44mm x 64mm的MCM- c封装中实现,其引脚网格阵列(PGA)模块连接到由Sun Microsystems, Inc.设计和制造的卡片上。MCM设计通过使用Cadence Allegro 7.0完成的逻辑设计从Sun Microsystems, Inc.接受到IBM Packaging Foundry。应用成果包括在倒装互连的信号重新分配后在OEM晶圆上碰撞芯片,以及使用Cadence Allegro 7.0设计系统将MCM设计发布到IBM代工厂。功能性能测试将由Sun Microsystems公司提供。本文讨论了MCM开发的各个方面,包括物理和电气设计、快速原型构建、热管理、模块组装、模块互连测试和模块功能性能。
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引用次数: 0
Evaluation of Non-Hermetic Coatings for Mcm Applications through Hast, 85/85 and Pct 通过Hast、85/85和Pct对Mcm应用的非密封涂层进行评价
Pub Date : 1994-04-13 DOI: 10.1109/ICMCM.1994.753572
C. Murphy, R. Kodnani, D. Peterson
The goal of the Reliability without Hermeticity (RwoH) Project is to find non-hermetic coatings for use on MCMs. As a means of down-selecting coating materials, Sandia ATC01 test chips in 40 pin DIPs were coated with non-hermetic, polymer materials, including silicone gel, filled epoxy, and polyimide. After preconditioning through temperature cycling and atmosphere, the parts were subjected to one of three different temperature, humidity, and bias conditions: HAST (140/spl deg/C, 85% RH, +40V), 85/85 (85/spl deg/C, 85% RH, +40V), or PCT (121/spl deg/C, 99.6% RH). No universal relationship between lifetime in HAST and 85/85 testing was observed-the effects appear to be material dependent. Electrical test data suggest that failures on coated parts (with standard SiN chip passivation) do not occur on die circuitry (triple tracks) and instead occur on bond-wires and bond-pads.
无密封性可靠性(RwoH)项目的目标是寻找用于mcm的非密封性涂层。作为一种向下选择涂层材料的方法,Sandia ATC01测试芯片在40针的dip中涂覆了非密封的聚合物材料,包括硅凝胶,填充环氧树脂和聚酰亚胺。在通过温度循环和气氛进行预处理后,零件受到三种不同温度,湿度和偏置条件中的一种:HAST (140/spl℃,85% RH, +40V), 85/85 (85/spl℃,85% RH, +40V)或PCT (121/spl℃,99.6% RH)。未观察到在HAST测试和85/85测试中寿命之间的普遍关系-效果似乎是物质依赖的。电气测试数据表明,涂层部件(采用标准SiN芯片钝化)的故障不会发生在模具电路(三道)上,而是发生在连接线和连接垫上。
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引用次数: 5
An In-Situ Measurement Technique for Through-Plane Thermal Properties of Thin Dielectric Films 介质薄膜通过平面热性能的原位测量技术
Pub Date : 1994-04-13 DOI: 10.1109/ICMCM.1994.753573
T. Hodge, S. Bidstrup, P. Kohl, J. Lee, M. Allen
In MCM-D applications, interlayer dielectrics separate and insulate metal conductors to form a threedimensional interconnection structure. Due to the three-dimensional nature of these structures, the electrical and mechanical properties of the dielectric materials must be known in all directions for proper device design. The most commonly used polymer in microelectronics, polyimide, exists in formulations which have been shown to have a high degree of orientation and exhibit anisotropic properties. mechanical proprties of thin films is diftidt due to the high resolution required to measure the small thickness changes. Existing techniques require either stacked thin films or a single cast thick film of 100 micrometers or more to achieve dimensionat changes large enough to be measwabie.740 In addition, most existing techniques require removing a large area of film, if not the whole film, from a supporting substrate to perfom the measurement. These techniques neglect the effects of the dielectric-substrate interaction, such as Poisson's effm and adhesive effects. Since most MCM-D structures utilize thin films adhered to a substrate, the measured through-plane CTEs from these other techniques may not reflect the true thermal expansion expected in real devices. Measurement of through-plane
在MCM-D应用中,层间介质分离和绝缘金属导体,形成三维互连结构。由于这些结构具有三维性质,因此必须在所有方向上了解介电材料的电气和机械性能,以便进行适当的器件设计。微电子学中最常用的聚合物聚酰亚胺存在于已被证明具有高度取向和表现出各向异性的配方中。由于测量微小的厚度变化需要高分辨率,因此薄膜的机械性能很难测量。现有的技术要么需要堆叠的薄膜,要么需要一个100微米或更厚的单层浇铸薄膜,以实现足够大的可测量的尺寸变化此外,大多数现有技术需要从支撑基板上去除大面积的薄膜,如果不是整个薄膜,来进行测量。这些技术忽略了介电-衬底相互作用的影响,如泊松effm和粘接效应。由于大多数MCM-D结构使用粘附在衬底上的薄膜,因此从这些其他技术中测量的通平面cte可能无法反映实际设备中预期的真实热膨胀。通平面的测量
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引用次数: 1
Thermoplastic Die Attach for Hermetic Packaging 用于密封包装的热塑性模具附件
Pub Date : 1994-04-13 DOI: 10.1109/ICMCM.1994.753529
P. Harper
When selecting die attach material for hermetic packaging the user has been limited to two options; gold-silicon eutectic ribbon and silver/glass paste. Recently, new developments in high temperature polymer technology have opened up new options for hermetic die attach. New high temperature thermoplastic adhesives have been developed that can be bonded in seconds and offer the ability to rework the die attach by re-melting the adhesive. The process window and functional performance of two thermoplastic die attach materials were evaluated for their suitability for use in solder sealed cofired pin grid array ceramic and glass sealed ceramic quad flat packages. The process parameters of Time, Temperature, Pressure, and Scrub were investigated to determine the optimal manufacturing conditions.
在选择密封包装的贴模材料时,用户只有两种选择;金硅共晶带和银/玻璃糊。最近,在高温聚合物技术的新发展开辟了新的选择密封模具连接。新的高温热塑性胶粘剂已经开发出来,可以在几秒钟内粘合,并提供通过重新熔化胶粘剂来重新加工模具的能力。对两种热塑性贴片材料的工艺窗口和功能性能进行了评价,以确定其在焊接密封共烧引脚网格阵列陶瓷和玻璃密封陶瓷四平面封装中的适用性。研究了时间、温度、压力、擦洗等工艺参数,确定了最佳工艺条件。
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引用次数: 5
Non-Digital Extensions of an Embedded Chip MCM Technology 嵌入式芯片MCM技术的非数字扩展
Pub Date : 1994-04-13 DOI: 10.1109/ICMCM.1994.753591
R. Fillion, R.J. Wojnarowski, W. Bicknell, W. Daum, G. Forman
The GE/Martin Marietta/Texas Instruments embedded chip multichip technology was developed for high performance digital circuits used in aerospace applications. The HDI process involves the placement of bare chips into cavities formed into a base substrate, lamination of a polymer dielectric film over the chips and the substrate, and the formation of vias and interconnect metallization on the polymer film. Multiple levels of interconnect are formed by repeating the film lamination, via formation and metallization steps. The direct metallization to the chip I/O pads eliminates the need for normal chip I/O wire bonds, TAB, or solder bumps. The elimination of these chip connections and the high electrical performance of the polymer/copper interconnect structure result in the superior speed of such embedded chip MCMs. The technology also features high current carrying capability, high reliability in harsh mechanical and thermal environments and high thermal dissipation capability. The inherently high performance features of the embedded chip MCM technology have been exploited in non-digital electronics such as: mixed analog and digital circuits, power conversion and conditioning, microwave transmit and receive (TIR) modules, and optoelectronic modules. The ability of embedded chip HDI to fully shield high frequency devices in a module from other components and the complete elimination of the discontinuities associated with chip I/O attach, makes it ideal for mixed mode operation. Current non digital examples making use of this unique capability are a >400 MHz GaAs 128 X 128 crosspoint switch, a 50 Watt, 85% efficient DC-to-DC converter, a 14 Bit voice / data modem circuit, and a 54 channel 12 Bit instrumentation A/D converter module. All of these unique examples of non-digital extensions of the embedded chip HDI MCM interconnect process will be described along with their unique features, processing and/or structures.
GE/Martin Marietta/Texas Instruments嵌入式芯片多芯片技术是为航空航天应用中使用的高性能数字电路而开发的。HDI工艺包括将裸芯片放置到形成基板的空腔中,在芯片和基板上层压聚合物介电膜,并在聚合物膜上形成通孔和互连金属化。通过形成和金属化步骤,通过重复薄膜层压形成多层互连。芯片I/O焊盘的直接金属化消除了正常芯片I/O线键、TAB或焊料凸起的需要。这些芯片连接的消除和聚合物/铜互连结构的高电性能导致这种嵌入式芯片mcm的优越速度。该技术还具有载流能力大,在恶劣的机械和热环境下具有高可靠性和高散热能力。嵌入式芯片MCM技术固有的高性能特性已经在非数字电子产品中得到了利用,例如:混合模拟和数字电路、功率转换和调理、微波发射和接收(TIR)模块以及光电模块。嵌入式芯片HDI能够完全屏蔽模块中的高频器件,使其不受其他组件的影响,并完全消除与芯片I/O连接相关的不连续,使其成为混合模式操作的理想选择。目前使用这种独特功能的非数字示例包括>400 MHz GaAs 128 X 128交叉点开关,50瓦,85%效率的dc - dc转换器,14位语音/数据调制解调器电路和54通道12位仪表a /D转换器模块。所有这些嵌入式芯片HDI MCM互连过程的非数字扩展的独特示例将与其独特的功能,处理和/或结构一起描述。
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引用次数: 7
Interconnection Considerations for a Hybrid Mcm 混合Mcm的互连考虑
Pub Date : 1994-04-13 DOI: 10.1109/ICMCM.1994.753566
J. Norén, P. Brofman
A complex hybrid (mixed interconnect) MCM is described wherein wire bonded and flip chipped IC's are attached to a thin film MCM. Additionally, a TAB IC and soldered discretes are also attached. For purpose of card-level assembly, the populated thin film MCM is mechanically, thermally, and electrically enclosed in a large alumina cavity-down PGA, and hermetically sealed. The design concept enables each of the inter connection schemes to be assessed either separately or synergistically. While the design point is unlikely to be used in production, the test vehicle offers a remarkable opportunity to assess viable combinations of hybrid MCM technology that are planned for production in various forms. Several of the technology challenges associated with such hybridization at the MCM level are discussed, along with preliminary results of stress testing from this vehicle. Feasability for combining flip chip, wire bond, TAB, and soldered discretes on a thin film carrier is demonstrated.
描述了一种复杂的混合(混合互连)MCM,其中线键合和倒装IC连接到薄膜MCM上。此外,一个标签IC和焊接分立也附上。为了卡级组装的目的,填充的薄膜MCM在机械上、热上和电上被封闭在一个大的氧化铝空腔向下的PGA中,并密封。设计理念使每个互连方案可以单独评估或协同评估。虽然设计点不太可能用于生产,但测试车提供了一个很好的机会来评估混合MCM技术的可行组合,这些组合计划以各种形式用于生产。讨论了与MCM级杂交相关的几个技术挑战,以及该车辆压力测试的初步结果。演示了在薄膜载体上结合倒装芯片、线键、TAB和焊接分立器件的可行性。
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引用次数: 3
期刊
Proceedings of the International Conference on Multichip Modules
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