Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753558
Y. Kondoh, T. Ueno
We propose a new type of membrane probe, which might be called a Universal Membrane Probe (UMP), as a standard Known-Good Die (KGD) solution for Multi Chip Module (MCM) manufacture. In this paper we will give an outline of this new probe, describe the newly developed manufacturing process for it, and evaluate the performance of a prototype probe. The features of this probe are firstly that it is disposable and based on low-cost materials such as Tape Automated Bonding (TAB) tape; secondly, it is non-customized and so applicable to a wide variety of die sizes and pad configurations; and finally it potentially offers a new standard for wafer probing.
{"title":"Universal Membrane Probe for Known Good Die","authors":"Y. Kondoh, T. Ueno","doi":"10.1109/ICMCM.1994.753558","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753558","url":null,"abstract":"We propose a new type of membrane probe, which might be called a Universal Membrane Probe (UMP), as a standard Known-Good Die (KGD) solution for Multi Chip Module (MCM) manufacture. In this paper we will give an outline of this new probe, describe the newly developed manufacturing process for it, and evaluate the performance of a prototype probe. The features of this probe are firstly that it is disposable and based on low-cost materials such as Tape Automated Bonding (TAB) tape; secondly, it is non-customized and so applicable to a wide variety of die sizes and pad configurations; and finally it potentially offers a new standard for wafer probing.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127928476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753561
T. Dudderar, Y. Degani, J. G. Spadafora, K. Tai, R. Frye
The realization of a high speed, high-yield flip-chip assembly capability is essential to the development of a practical, cost effective MCM technology because it supports large volume, relatively inexpensive product applications in which equipment costs per unit can be minimized. This paper describes a novel assembly technique for flip-chip silicon-on-silicon Multi-Chip Module (MCM-D) tiles which readily meets the above criteria. This new hybrid technique, which is called AT&T /spl mu/SMT, involves stencil printing a custom AT&T ultra-fine pitch solder paste directly onto a silicon fabric wafer which is then populated with bare die and reflowed, much as surface mount packaged components would be assembled onto a circuit board. This approach is capable of achieving higher component and interconnection densities than can be achieved with any fine-pitch SMT design - and at a lower unit cost at large production volumes than can be achieved with any other MCM assembly technology.
{"title":"AT&T spl mu/Surface Mount Assembly: A New Technology for the Large Volume Fabrication of Cost Effective Flip-Chip MCMs","authors":"T. Dudderar, Y. Degani, J. G. Spadafora, K. Tai, R. Frye","doi":"10.1109/ICMCM.1994.753561","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753561","url":null,"abstract":"The realization of a high speed, high-yield flip-chip assembly capability is essential to the development of a practical, cost effective MCM technology because it supports large volume, relatively inexpensive product applications in which equipment costs per unit can be minimized. This paper describes a novel assembly technique for flip-chip silicon-on-silicon Multi-Chip Module (MCM-D) tiles which readily meets the above criteria. This new hybrid technique, which is called AT&T /spl mu/SMT, involves stencil printing a custom AT&T ultra-fine pitch solder paste directly onto a silicon fabric wafer which is then populated with bare die and reflowed, much as surface mount packaged components would be assembled onto a circuit board. This approach is capable of achieving higher component and interconnection densities than can be achieved with any fine-pitch SMT design - and at a lower unit cost at large production volumes than can be achieved with any other MCM assembly technology.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126627591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753565
A. B. Frazier, R. Powers, M. Allen
A new low cost material is presented for the realization of thin film programmable interconnect arrays for selective switching of chip to substrate interconnects from a high impedance state to a low impedance state. The programmable interconnect arrays are realized using a tri-level graphite-filled polyimide system as an interlayer material between metallic electrodes. The interconnects are switched from a high impedance to a low impedance state using an activation current to heat the material between the electrodes. This current causes an irreversible change of material resistivity which persists even after the current is removed. The graphite loading of the individual layers is varied in order to obtain the optimal interconnect characteristics. The characteristics of interest at this time are the dc levels of the interconnect initial resistance and the final resistance as well as the magnitude of the change in resistance between the initial and final states. Results of various layer combinations including 5/30/30, 0/18/0 and 3/3/3 wt% graphite are presented.
{"title":"Thin Film Programmable Interconnect Arrays","authors":"A. B. Frazier, R. Powers, M. Allen","doi":"10.1109/ICMCM.1994.753565","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753565","url":null,"abstract":"A new low cost material is presented for the realization of thin film programmable interconnect arrays for selective switching of chip to substrate interconnects from a high impedance state to a low impedance state. The programmable interconnect arrays are realized using a tri-level graphite-filled polyimide system as an interlayer material between metallic electrodes. The interconnects are switched from a high impedance to a low impedance state using an activation current to heat the material between the electrodes. This current causes an irreversible change of material resistivity which persists even after the current is removed. The graphite loading of the individual layers is varied in order to obtain the optimal interconnect characteristics. The characteristics of interest at this time are the dc levels of the interconnect initial resistance and the final resistance as well as the magnitude of the change in resistance between the initial and final states. Results of various layer combinations including 5/30/30, 0/18/0 and 3/3/3 wt% graphite are presented.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116371863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753541
S. Sasaki, T. Kishimoto, K. Genda, K. Endo, K. Kaizu
High-performance, compact multichip modules (MCMs) using a copper polyimide multi-layer substrate are used to make a 40-Gb/s-throughput ATM switching module. The MCM substrate has 392 high-speed signal I/0 channels, thin-film termination resistors, and 50 /spl mu/m laminated capacitance layers. We made a sub switching element module using these MCMs, new high-speed FPC cables, and heat pipes fins. This sub-switching element module can operate at 80 Gb/s throughput.
{"title":"Multichip module technologies for high-speed ATM switching systems","authors":"S. Sasaki, T. Kishimoto, K. Genda, K. Endo, K. Kaizu","doi":"10.1109/ICMCM.1994.753541","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753541","url":null,"abstract":"High-performance, compact multichip modules (MCMs) using a copper polyimide multi-layer substrate are used to make a 40-Gb/s-throughput ATM switching module. The MCM substrate has 392 high-speed signal I/0 channels, thin-film termination resistors, and 50 /spl mu/m laminated capacitance layers. We made a sub switching element module using these MCMs, new high-speed FPC cables, and heat pipes fins. This sub-switching element module can operate at 80 Gb/s throughput.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114684419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753563
M. Oppermannm, E. Feurer, B. Holl
A doubleface populated transmit/receive (TR) multichip module for radar applications has been implemented with multilayer integration technology. The multilayer is designed and fabricated in thin film technology on A1203 ceramic substrates and offers a high order of complexity for high frequency (hf/rf) circuits up to 20 GHz. 100 /spl mu/m striplines with integrated thin film resistors in combination with the dielectric spaced ground layer on the opposite side define the hf layer on top of the substrate. The multilayer logic control unit on the backside consists of three metal layers (ground-, x-, y conductor plane), each seperated by patterned polymeric dielectrics (Polyimide, Benzocyclobutene). This paper describes the necessary technological steps for high performance in thin film technology. Metallization is done in semi-additive technology and the structured dielectric layers are realized with spin coated materials. Through-holes metallization in the substrate allows communication between the two sides and very short interconnections between the GaAs-MMIC's and the logic control unit.
{"title":"Development and Realization of a Doubleface Populated Multichip Module in Thin Film Technology for High Frequency Application","authors":"M. Oppermannm, E. Feurer, B. Holl","doi":"10.1109/ICMCM.1994.753563","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753563","url":null,"abstract":"A doubleface populated transmit/receive (TR) multichip module for radar applications has been implemented with multilayer integration technology. The multilayer is designed and fabricated in thin film technology on A1203 ceramic substrates and offers a high order of complexity for high frequency (hf/rf) circuits up to 20 GHz. 100 /spl mu/m striplines with integrated thin film resistors in combination with the dielectric spaced ground layer on the opposite side define the hf layer on top of the substrate. The multilayer logic control unit on the backside consists of three metal layers (ground-, x-, y conductor plane), each seperated by patterned polymeric dielectrics (Polyimide, Benzocyclobutene). This paper describes the necessary technological steps for high performance in thin film technology. Metallization is done in semi-additive technology and the structured dielectric layers are realized with spin coated materials. Through-holes metallization in the substrate allows communication between the two sides and very short interconnections between the GaAs-MMIC's and the logic control unit.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"30 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129467869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753581
J. Cazenave, G. Dupenloup
This paper describes a large MCM developed for space applications. Design constraints were extremely severe: low volume, low weight, high signal speed, minimum power consumption, high pressure, exposition to space vacuum. The MCM includes 1.2 million of transistors. It required the design of 8 different types of ASICs in 3 different technologies: CMOS, ECL, mixed-signal bipolar. The substrate has been fabricated using Dassault Electronique's high-density photo-imageable thick-film process (PCM technology), that is briefly described in this paper. An Aluminium package was used to save weight and improve thermal conduction. Stand-offs sustaining the lid were used to handle high pressure. The MCM and the ASICs were concurrently designed to simplify the layout of the MCM as much as possible. Despite high routing density, only 4 layers were used. Heavy traffic was "pushed" into ASICs where there is no significant extra cost associated with connections. The ASIC pads were arranged to match MCM wires. A global Design-For-Test strategy has been implemented. The ASICs include internal and external Built-In Self Test (BIST) resources, that allow to test the ASICs and the MCM connections at full speed and with no external test vectors. Test modes can be controlled and defaults can be located through a single test bus based on the IEEE 1149.1 (JTAG) standard. The MCM can be fully tested with no other test equipment than a standard PC connected to its test bus.
{"title":"Global Optimization of MCMs with ASICs Using Concurrent Engineering","authors":"J. Cazenave, G. Dupenloup","doi":"10.1109/ICMCM.1994.753581","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753581","url":null,"abstract":"This paper describes a large MCM developed for space applications. Design constraints were extremely severe: low volume, low weight, high signal speed, minimum power consumption, high pressure, exposition to space vacuum. The MCM includes 1.2 million of transistors. It required the design of 8 different types of ASICs in 3 different technologies: CMOS, ECL, mixed-signal bipolar. The substrate has been fabricated using Dassault Electronique's high-density photo-imageable thick-film process (PCM technology), that is briefly described in this paper. An Aluminium package was used to save weight and improve thermal conduction. Stand-offs sustaining the lid were used to handle high pressure. The MCM and the ASICs were concurrently designed to simplify the layout of the MCM as much as possible. Despite high routing density, only 4 layers were used. Heavy traffic was \"pushed\" into ASICs where there is no significant extra cost associated with connections. The ASIC pads were arranged to match MCM wires. A global Design-For-Test strategy has been implemented. The ASICs include internal and external Built-In Self Test (BIST) resources, that allow to test the ASICs and the MCM connections at full speed and with no external test vectors. Test modes can be controlled and defaults can be located through a single test bus based on the IEEE 1149.1 (JTAG) standard. The MCM can be fully tested with no other test equipment than a standard PC connected to its test bus.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129500686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753523
M. Salatino, R. Nolan, T. Bishop, C. Bieber
The success of nearly every multichip electronic system depends on the availability of functional, reliable chips. As chip counts in a multichip system increase, this dependency is critical. In most cases, "known good" die (KGD) are not readily available in an unpackaged form. This was a prime consideration in MCC's. Flip Chip Development Project. As part of this project, MCC was chartered with developing a method for high speed test and dynamic burn-in of single, bare IC chips. The method developed can be implemented by bare die users using "off-the-shelf" technology. It can also be implemented by bare chip suppliers without modification to the existing fabrication processes. The heart of this process is a TAB tape-based carrier. TAB tape is used to contact the chip bond pads (without actual metallurgical bonding) at about 10 grams per lead contact force. The chip is clamped to the TAB leads, and held in place so that the tape site (in its JEDEC-standard slide carrier) can be transported, tested, and burned-in just like TAB chip-on-tape. Upon test completion, the chip is removed, and is ready for wire bonding, flip chip attach, etc. The carrier has been characterized with aluminum, gold, and solder-bumped chip bond pads, and is compatible with these pad metallizations. Four re-uses of the carrier through 168 hours/150"C of burn-in have been demonstrated. In this paper, the results of MCC's initial prototype testing are discussed. Data includes contact resistance vs. pressure, chip metallurgy, and time. The cost of this approach is presented for a wide range of production volumes. In addition, preliminary results from beta-site testing (by a bare chip supplier) of this method are presented.
{"title":"Implementing a Tab Tape-based Known Good Die Method","authors":"M. Salatino, R. Nolan, T. Bishop, C. Bieber","doi":"10.1109/ICMCM.1994.753523","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753523","url":null,"abstract":"The success of nearly every multichip electronic system depends on the availability of functional, reliable chips. As chip counts in a multichip system increase, this dependency is critical. In most cases, \"known good\" die (KGD) are not readily available in an unpackaged form. This was a prime consideration in MCC's. Flip Chip Development Project. As part of this project, MCC was chartered with developing a method for high speed test and dynamic burn-in of single, bare IC chips. The method developed can be implemented by bare die users using \"off-the-shelf\" technology. It can also be implemented by bare chip suppliers without modification to the existing fabrication processes. The heart of this process is a TAB tape-based carrier. TAB tape is used to contact the chip bond pads (without actual metallurgical bonding) at about 10 grams per lead contact force. The chip is clamped to the TAB leads, and held in place so that the tape site (in its JEDEC-standard slide carrier) can be transported, tested, and burned-in just like TAB chip-on-tape. Upon test completion, the chip is removed, and is ready for wire bonding, flip chip attach, etc. The carrier has been characterized with aluminum, gold, and solder-bumped chip bond pads, and is compatible with these pad metallizations. Four re-uses of the carrier through 168 hours/150\"C of burn-in have been demonstrated. In this paper, the results of MCC's initial prototype testing are discussed. Data includes contact resistance vs. pressure, chip metallurgy, and time. The cost of this approach is presented for a wide range of production volumes. In addition, preliminary results from beta-site testing (by a bare chip supplier) of this method are presented.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130880060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753613
A. L. Kovacs, D. Elwell
{"title":"Integrated Brazed Ltcc Packages","authors":"A. L. Kovacs, D. Elwell","doi":"10.1109/ICMCM.1994.753613","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753613","url":null,"abstract":"","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121692567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753588
P. Thompson
In Motorola's experience with commercial MCM customers, system size and cost reduction are the largest factors for interest in MCMs. Performance improvement is generally of secondary interest. Development and qualification can add significantly to the total cost of an MCM, so in addition to the normal desire to provide reliable products, the cost of doing so has gained increased importance. A new product introduction (NPI) process for low-cost MCMs has been implemented to rapidly provide cost-effective, reliable MCM solutions for cost-sensitive MCM users. The NPI process is based on three attributes: leverage single chip package (SCP) experience and technology, perform product family qualifications and use only previously qualified silicon in MCMs. Application of the NPI process to the development and qualification of the 28mm MCML/sup TM/ Series package is presented in this paper.
{"title":"Mcm-L Product Development Process for Low-Cost Mcms","authors":"P. Thompson","doi":"10.1109/ICMCM.1994.753588","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753588","url":null,"abstract":"In Motorola's experience with commercial MCM customers, system size and cost reduction are the largest factors for interest in MCMs. Performance improvement is generally of secondary interest. Development and qualification can add significantly to the total cost of an MCM, so in addition to the normal desire to provide reliable products, the cost of doing so has gained increased importance. A new product introduction (NPI) process for low-cost MCMs has been implemented to rapidly provide cost-effective, reliable MCM solutions for cost-sensitive MCM users. The NPI process is based on three attributes: leverage single chip package (SCP) experience and technology, perform product family qualifications and use only previously qualified silicon in MCMs. Application of the NPI process to the development and qualification of the 28mm MCML/sup TM/ Series package is presented in this paper.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117234609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753578
M. Michaud, J. Rameš
INTRODUCTION The main electronic activity of MATRA DEFENSE is the development and production of pilot and guidance equipments for air to air missiles. In the mid 80's MATRA DEFENSE qualified a double sided Surface Mount Technology in order to reduce the size and cost of the electronic equipments. This technology is based on polyimide multilayer ( 10 to 14 layers) printed circuit with 2 sheets of Copper / Invar/ Copper. Components are packaged in Leadless Ceramic Chip Carriers and vapor phase is used for the soldering process. In 1990 MATRA DEFENSE started an R&D programme on MCM. We decided not to build the substrate in house, but to concentrate our efforts on the design and the assembly technology for MCM. The two first modules developed were memory modules ( SRAM and EEPROM ) but these modules were nevers build in series because they didn't fit our needs in terms of size and production cost in comparison with the monolithic components. Our first real application was a complex MCM standard module for using in different applications to be produced in "large" series.
{"title":"Development of a Dsp Function Using a Mcm Technology","authors":"M. Michaud, J. Rameš","doi":"10.1109/ICMCM.1994.753578","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753578","url":null,"abstract":"INTRODUCTION The main electronic activity of MATRA DEFENSE is the development and production of pilot and guidance equipments for air to air missiles. In the mid 80's MATRA DEFENSE qualified a double sided Surface Mount Technology in order to reduce the size and cost of the electronic equipments. This technology is based on polyimide multilayer ( 10 to 14 layers) printed circuit with 2 sheets of Copper / Invar/ Copper. Components are packaged in Leadless Ceramic Chip Carriers and vapor phase is used for the soldering process. In 1990 MATRA DEFENSE started an R&D programme on MCM. We decided not to build the substrate in house, but to concentrate our efforts on the design and the assembly technology for MCM. The two first modules developed were memory modules ( SRAM and EEPROM ) but these modules were nevers build in series because they didn't fit our needs in terms of size and production cost in comparison with the monolithic components. Our first real application was a complex MCM standard module for using in different applications to be produced in \"large\" series.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121593626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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