Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753576
C. N. Lazaridis, D. K. Flattery, W. J. Lautenberger, Y. Yamamoto, K. Imai
The excellent film properties given by BPDA/PPD make it a prime candidate for the dielectric material in MCM-D fabrications, and photodefinable versions offer the additional advantages of reduced labor and material costs. However, less than adequate adhesion to the preferred copper metallurgy coupled with prolonged development times may limit widespread adoption of this chemistry. Modifications to the BPDA/PPD backbone were made in a series of photodefinable polyimides prepared as the ionic salt precursors, and key performance and processing parameters were determined. Significant adhesion of the highly rigid BPDA/PPD backbone to copper metal was only achieved after substantial incorporation of either more flexible co-monomers, especially those containing fluorine substituents, or by incorporation of an assumed surface reactive, hydroxyl-substituted co-monomer. These modifications generally also resulted in reduced development times. Self-adhesion of polyimide to polyimide layers was optimized by using a partial cure process for the bottom polyimide layer, and appropriate cure temperatures were determined for each structure to prevent solvent-induced cracking of the bottom layer upon application of the top layer while retaining self-adhesion. Operable processing windows were found for several candidates which maximized adhesion and minimized cracking.
{"title":"Evaluation of Ionic Salt Photodefinable Polyimides As Mcm-D Dielectrics with Copper Metallization","authors":"C. N. Lazaridis, D. K. Flattery, W. J. Lautenberger, Y. Yamamoto, K. Imai","doi":"10.1109/ICMCM.1994.753576","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753576","url":null,"abstract":"The excellent film properties given by BPDA/PPD make it a prime candidate for the dielectric material in MCM-D fabrications, and photodefinable versions offer the additional advantages of reduced labor and material costs. However, less than adequate adhesion to the preferred copper metallurgy coupled with prolonged development times may limit widespread adoption of this chemistry. Modifications to the BPDA/PPD backbone were made in a series of photodefinable polyimides prepared as the ionic salt precursors, and key performance and processing parameters were determined. Significant adhesion of the highly rigid BPDA/PPD backbone to copper metal was only achieved after substantial incorporation of either more flexible co-monomers, especially those containing fluorine substituents, or by incorporation of an assumed surface reactive, hydroxyl-substituted co-monomer. These modifications generally also resulted in reduced development times. Self-adhesion of polyimide to polyimide layers was optimized by using a partial cure process for the bottom polyimide layer, and appropriate cure temperatures were determined for each structure to prevent solvent-induced cracking of the bottom layer upon application of the top layer while retaining self-adhesion. Operable processing windows were found for several candidates which maximized adhesion and minimized cracking.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114123246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753546
T. Houston, H. Heck, J. Knight
As the electronics packaging industry turns toward MCM-L technology to provide higher performance, lower cost packaging solutions the demands on laminate technology increase. Increasing chip I/O places more challenging requirements on the laminate wiring density. The design considerations that drive circuit density are I/O escape and global interconnect. This paper discusses IBM Endicott's approach to addressing the escape requirements using a set of hi density laminate technologies. IBM's laminate carriers were designed to target a spectrum of chip I/O requirements. Of particular interest is the ability to escape multiple rows of flip chip I/O. Access to multiple wiring layers is necessary when the I/O are arranged in an array or perimeter array configuration. The key to accessing internal laminate layers is the capability to provide fine pitch vias with small capture lands. This paper discusses the approaches that IBM Microelectronics takes to provide the appropriate laminate solution for a given chip I/O configuration. Specific examples are presented to show how chip I/O density affects the physical characteristics of the laminate technology. Additional factors that must be carefully weighed include material properties, processing requirements, electrical and thermal performance, and connection to the next level of packaging. IBM's laminate carriers were designed to target a spectrum of chip I/O requirements. Of particular interest is the ability to escape multiple rows of flip chip I/O. Access to multiple wiring layers is necessary when the I/O are arranged in an array or perimeter array configuration. The key to accessing internal laminate layers is the capability to provide fine pitch vias with small capture lands. This paper discusses the approaches that IBM Microelectronics takes to provide the appropriate laminate solution for a given chip I/O configuration. Specific examples are presented to show how chip I/O density affects the physical characteristics of the laminate technology. Additional factors that must be carefully weighed include material properties, processing requirements, electrical and thermal performance, and connection to the next level of packaging.
{"title":"An Application Strategy for Scm-L and Mcm-L Using High Density Laminate Technologies","authors":"T. Houston, H. Heck, J. Knight","doi":"10.1109/ICMCM.1994.753546","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753546","url":null,"abstract":"As the electronics packaging industry turns toward MCM-L technology to provide higher performance, lower cost packaging solutions the demands on laminate technology increase. Increasing chip I/O places more challenging requirements on the laminate wiring density. The design considerations that drive circuit density are I/O escape and global interconnect. This paper discusses IBM Endicott's approach to addressing the escape requirements using a set of hi density laminate technologies. IBM's laminate carriers were designed to target a spectrum of chip I/O requirements. Of particular interest is the ability to escape multiple rows of flip chip I/O. Access to multiple wiring layers is necessary when the I/O are arranged in an array or perimeter array configuration. The key to accessing internal laminate layers is the capability to provide fine pitch vias with small capture lands. This paper discusses the approaches that IBM Microelectronics takes to provide the appropriate laminate solution for a given chip I/O configuration. Specific examples are presented to show how chip I/O density affects the physical characteristics of the laminate technology. Additional factors that must be carefully weighed include material properties, processing requirements, electrical and thermal performance, and connection to the next level of packaging. IBM's laminate carriers were designed to target a spectrum of chip I/O requirements. Of particular interest is the ability to escape multiple rows of flip chip I/O. Access to multiple wiring layers is necessary when the I/O are arranged in an array or perimeter array configuration. The key to accessing internal laminate layers is the capability to provide fine pitch vias with small capture lands. This paper discusses the approaches that IBM Microelectronics takes to provide the appropriate laminate solution for a given chip I/O configuration. Specific examples are presented to show how chip I/O density affects the physical characteristics of the laminate technology. Additional factors that must be carefully weighed include material properties, processing requirements, electrical and thermal performance, and connection to the next level of packaging.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114172080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753541
S. Sasaki, T. Kishimoto, K. Genda, K. Endo, K. Kaizu
High-performance, compact multichip modules (MCMs) using a copper polyimide multi-layer substrate are used to make a 40-Gb/s-throughput ATM switching module. The MCM substrate has 392 high-speed signal I/0 channels, thin-film termination resistors, and 50 /spl mu/m laminated capacitance layers. We made a sub switching element module using these MCMs, new high-speed FPC cables, and heat pipes fins. This sub-switching element module can operate at 80 Gb/s throughput.
{"title":"Multichip module technologies for high-speed ATM switching systems","authors":"S. Sasaki, T. Kishimoto, K. Genda, K. Endo, K. Kaizu","doi":"10.1109/ICMCM.1994.753541","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753541","url":null,"abstract":"High-performance, compact multichip modules (MCMs) using a copper polyimide multi-layer substrate are used to make a 40-Gb/s-throughput ATM switching module. The MCM substrate has 392 high-speed signal I/0 channels, thin-film termination resistors, and 50 /spl mu/m laminated capacitance layers. We made a sub switching element module using these MCMs, new high-speed FPC cables, and heat pipes fins. This sub-switching element module can operate at 80 Gb/s throughput.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114684419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753588
P. Thompson
In Motorola's experience with commercial MCM customers, system size and cost reduction are the largest factors for interest in MCMs. Performance improvement is generally of secondary interest. Development and qualification can add significantly to the total cost of an MCM, so in addition to the normal desire to provide reliable products, the cost of doing so has gained increased importance. A new product introduction (NPI) process for low-cost MCMs has been implemented to rapidly provide cost-effective, reliable MCM solutions for cost-sensitive MCM users. The NPI process is based on three attributes: leverage single chip package (SCP) experience and technology, perform product family qualifications and use only previously qualified silicon in MCMs. Application of the NPI process to the development and qualification of the 28mm MCML/sup TM/ Series package is presented in this paper.
{"title":"Mcm-L Product Development Process for Low-Cost Mcms","authors":"P. Thompson","doi":"10.1109/ICMCM.1994.753588","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753588","url":null,"abstract":"In Motorola's experience with commercial MCM customers, system size and cost reduction are the largest factors for interest in MCMs. Performance improvement is generally of secondary interest. Development and qualification can add significantly to the total cost of an MCM, so in addition to the normal desire to provide reliable products, the cost of doing so has gained increased importance. A new product introduction (NPI) process for low-cost MCMs has been implemented to rapidly provide cost-effective, reliable MCM solutions for cost-sensitive MCM users. The NPI process is based on three attributes: leverage single chip package (SCP) experience and technology, perform product family qualifications and use only previously qualified silicon in MCMs. Application of the NPI process to the development and qualification of the 28mm MCML/sup TM/ Series package is presented in this paper.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117234609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753613
A. L. Kovacs, D. Elwell
{"title":"Integrated Brazed Ltcc Packages","authors":"A. L. Kovacs, D. Elwell","doi":"10.1109/ICMCM.1994.753613","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753613","url":null,"abstract":"","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121692567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753565
A. B. Frazier, R. Powers, M. Allen
A new low cost material is presented for the realization of thin film programmable interconnect arrays for selective switching of chip to substrate interconnects from a high impedance state to a low impedance state. The programmable interconnect arrays are realized using a tri-level graphite-filled polyimide system as an interlayer material between metallic electrodes. The interconnects are switched from a high impedance to a low impedance state using an activation current to heat the material between the electrodes. This current causes an irreversible change of material resistivity which persists even after the current is removed. The graphite loading of the individual layers is varied in order to obtain the optimal interconnect characteristics. The characteristics of interest at this time are the dc levels of the interconnect initial resistance and the final resistance as well as the magnitude of the change in resistance between the initial and final states. Results of various layer combinations including 5/30/30, 0/18/0 and 3/3/3 wt% graphite are presented.
{"title":"Thin Film Programmable Interconnect Arrays","authors":"A. B. Frazier, R. Powers, M. Allen","doi":"10.1109/ICMCM.1994.753565","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753565","url":null,"abstract":"A new low cost material is presented for the realization of thin film programmable interconnect arrays for selective switching of chip to substrate interconnects from a high impedance state to a low impedance state. The programmable interconnect arrays are realized using a tri-level graphite-filled polyimide system as an interlayer material between metallic electrodes. The interconnects are switched from a high impedance to a low impedance state using an activation current to heat the material between the electrodes. This current causes an irreversible change of material resistivity which persists even after the current is removed. The graphite loading of the individual layers is varied in order to obtain the optimal interconnect characteristics. The characteristics of interest at this time are the dc levels of the interconnect initial resistance and the final resistance as well as the magnitude of the change in resistance between the initial and final states. Results of various layer combinations including 5/30/30, 0/18/0 and 3/3/3 wt% graphite are presented.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116371863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753558
Y. Kondoh, T. Ueno
We propose a new type of membrane probe, which might be called a Universal Membrane Probe (UMP), as a standard Known-Good Die (KGD) solution for Multi Chip Module (MCM) manufacture. In this paper we will give an outline of this new probe, describe the newly developed manufacturing process for it, and evaluate the performance of a prototype probe. The features of this probe are firstly that it is disposable and based on low-cost materials such as Tape Automated Bonding (TAB) tape; secondly, it is non-customized and so applicable to a wide variety of die sizes and pad configurations; and finally it potentially offers a new standard for wafer probing.
{"title":"Universal Membrane Probe for Known Good Die","authors":"Y. Kondoh, T. Ueno","doi":"10.1109/ICMCM.1994.753558","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753558","url":null,"abstract":"We propose a new type of membrane probe, which might be called a Universal Membrane Probe (UMP), as a standard Known-Good Die (KGD) solution for Multi Chip Module (MCM) manufacture. In this paper we will give an outline of this new probe, describe the newly developed manufacturing process for it, and evaluate the performance of a prototype probe. The features of this probe are firstly that it is disposable and based on low-cost materials such as Tape Automated Bonding (TAB) tape; secondly, it is non-customized and so applicable to a wide variety of die sizes and pad configurations; and finally it potentially offers a new standard for wafer probing.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127928476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753561
T. Dudderar, Y. Degani, J. G. Spadafora, K. Tai, R. Frye
The realization of a high speed, high-yield flip-chip assembly capability is essential to the development of a practical, cost effective MCM technology because it supports large volume, relatively inexpensive product applications in which equipment costs per unit can be minimized. This paper describes a novel assembly technique for flip-chip silicon-on-silicon Multi-Chip Module (MCM-D) tiles which readily meets the above criteria. This new hybrid technique, which is called AT&T /spl mu/SMT, involves stencil printing a custom AT&T ultra-fine pitch solder paste directly onto a silicon fabric wafer which is then populated with bare die and reflowed, much as surface mount packaged components would be assembled onto a circuit board. This approach is capable of achieving higher component and interconnection densities than can be achieved with any fine-pitch SMT design - and at a lower unit cost at large production volumes than can be achieved with any other MCM assembly technology.
{"title":"AT&T spl mu/Surface Mount Assembly: A New Technology for the Large Volume Fabrication of Cost Effective Flip-Chip MCMs","authors":"T. Dudderar, Y. Degani, J. G. Spadafora, K. Tai, R. Frye","doi":"10.1109/ICMCM.1994.753561","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753561","url":null,"abstract":"The realization of a high speed, high-yield flip-chip assembly capability is essential to the development of a practical, cost effective MCM technology because it supports large volume, relatively inexpensive product applications in which equipment costs per unit can be minimized. This paper describes a novel assembly technique for flip-chip silicon-on-silicon Multi-Chip Module (MCM-D) tiles which readily meets the above criteria. This new hybrid technique, which is called AT&T /spl mu/SMT, involves stencil printing a custom AT&T ultra-fine pitch solder paste directly onto a silicon fabric wafer which is then populated with bare die and reflowed, much as surface mount packaged components would be assembled onto a circuit board. This approach is capable of achieving higher component and interconnection densities than can be achieved with any fine-pitch SMT design - and at a lower unit cost at large production volumes than can be achieved with any other MCM assembly technology.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126627591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753563
M. Oppermannm, E. Feurer, B. Holl
A doubleface populated transmit/receive (TR) multichip module for radar applications has been implemented with multilayer integration technology. The multilayer is designed and fabricated in thin film technology on A1203 ceramic substrates and offers a high order of complexity for high frequency (hf/rf) circuits up to 20 GHz. 100 /spl mu/m striplines with integrated thin film resistors in combination with the dielectric spaced ground layer on the opposite side define the hf layer on top of the substrate. The multilayer logic control unit on the backside consists of three metal layers (ground-, x-, y conductor plane), each seperated by patterned polymeric dielectrics (Polyimide, Benzocyclobutene). This paper describes the necessary technological steps for high performance in thin film technology. Metallization is done in semi-additive technology and the structured dielectric layers are realized with spin coated materials. Through-holes metallization in the substrate allows communication between the two sides and very short interconnections between the GaAs-MMIC's and the logic control unit.
{"title":"Development and Realization of a Doubleface Populated Multichip Module in Thin Film Technology for High Frequency Application","authors":"M. Oppermannm, E. Feurer, B. Holl","doi":"10.1109/ICMCM.1994.753563","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753563","url":null,"abstract":"A doubleface populated transmit/receive (TR) multichip module for radar applications has been implemented with multilayer integration technology. The multilayer is designed and fabricated in thin film technology on A1203 ceramic substrates and offers a high order of complexity for high frequency (hf/rf) circuits up to 20 GHz. 100 /spl mu/m striplines with integrated thin film resistors in combination with the dielectric spaced ground layer on the opposite side define the hf layer on top of the substrate. The multilayer logic control unit on the backside consists of three metal layers (ground-, x-, y conductor plane), each seperated by patterned polymeric dielectrics (Polyimide, Benzocyclobutene). This paper describes the necessary technological steps for high performance in thin film technology. Metallization is done in semi-additive technology and the structured dielectric layers are realized with spin coated materials. Through-holes metallization in the substrate allows communication between the two sides and very short interconnections between the GaAs-MMIC's and the logic control unit.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"30 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129467869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753530
C. Proietti-Bowne, P. Elenius
The rework of wire bonded devices on MCMs (Multi Chip Modules) has historically been a manual procedure that has been time consuming and prone to operator error. This paper describes a complete rework process from the removal of the wires and device to the die attach material. The wires are removed using the Harmonicair/sup TM/. The Harmonicair leaves a very repeatable wire remnant on the substrate bond pad to facilitate the bonding of the next wire. The device is removed with a tensile process and the die attach material is then removed through a controlled shaving process.
{"title":"Rework of Wire Bonded Devices on Mcms","authors":"C. Proietti-Bowne, P. Elenius","doi":"10.1109/ICMCM.1994.753530","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753530","url":null,"abstract":"The rework of wire bonded devices on MCMs (Multi Chip Modules) has historically been a manual procedure that has been time consuming and prone to operator error. This paper describes a complete rework process from the removal of the wires and device to the die attach material. The wires are removed using the Harmonicair/sup TM/. The Harmonicair leaves a very repeatable wire remnant on the substrate bond pad to facilitate the bonding of the next wire. The device is removed with a tensile process and the die attach material is then removed through a controlled shaving process.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"217 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132053708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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