Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753523
M. Salatino, R. Nolan, T. Bishop, C. Bieber
The success of nearly every multichip electronic system depends on the availability of functional, reliable chips. As chip counts in a multichip system increase, this dependency is critical. In most cases, "known good" die (KGD) are not readily available in an unpackaged form. This was a prime consideration in MCC's. Flip Chip Development Project. As part of this project, MCC was chartered with developing a method for high speed test and dynamic burn-in of single, bare IC chips. The method developed can be implemented by bare die users using "off-the-shelf" technology. It can also be implemented by bare chip suppliers without modification to the existing fabrication processes. The heart of this process is a TAB tape-based carrier. TAB tape is used to contact the chip bond pads (without actual metallurgical bonding) at about 10 grams per lead contact force. The chip is clamped to the TAB leads, and held in place so that the tape site (in its JEDEC-standard slide carrier) can be transported, tested, and burned-in just like TAB chip-on-tape. Upon test completion, the chip is removed, and is ready for wire bonding, flip chip attach, etc. The carrier has been characterized with aluminum, gold, and solder-bumped chip bond pads, and is compatible with these pad metallizations. Four re-uses of the carrier through 168 hours/150"C of burn-in have been demonstrated. In this paper, the results of MCC's initial prototype testing are discussed. Data includes contact resistance vs. pressure, chip metallurgy, and time. The cost of this approach is presented for a wide range of production volumes. In addition, preliminary results from beta-site testing (by a bare chip supplier) of this method are presented.
{"title":"Implementing a Tab Tape-based Known Good Die Method","authors":"M. Salatino, R. Nolan, T. Bishop, C. Bieber","doi":"10.1109/ICMCM.1994.753523","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753523","url":null,"abstract":"The success of nearly every multichip electronic system depends on the availability of functional, reliable chips. As chip counts in a multichip system increase, this dependency is critical. In most cases, \"known good\" die (KGD) are not readily available in an unpackaged form. This was a prime consideration in MCC's. Flip Chip Development Project. As part of this project, MCC was chartered with developing a method for high speed test and dynamic burn-in of single, bare IC chips. The method developed can be implemented by bare die users using \"off-the-shelf\" technology. It can also be implemented by bare chip suppliers without modification to the existing fabrication processes. The heart of this process is a TAB tape-based carrier. TAB tape is used to contact the chip bond pads (without actual metallurgical bonding) at about 10 grams per lead contact force. The chip is clamped to the TAB leads, and held in place so that the tape site (in its JEDEC-standard slide carrier) can be transported, tested, and burned-in just like TAB chip-on-tape. Upon test completion, the chip is removed, and is ready for wire bonding, flip chip attach, etc. The carrier has been characterized with aluminum, gold, and solder-bumped chip bond pads, and is compatible with these pad metallizations. Four re-uses of the carrier through 168 hours/150\"C of burn-in have been demonstrated. In this paper, the results of MCC's initial prototype testing are discussed. Data includes contact resistance vs. pressure, chip metallurgy, and time. The cost of this approach is presented for a wide range of production volumes. In addition, preliminary results from beta-site testing (by a bare chip supplier) of this method are presented.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130880060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753614
M. Gorniak, D.F. Fayette, J. P. Farrell
The reliability of systems and equipment is critical for both customer satisfaction and system supportability. As a technology evolves, it cannot be inserted into new systems without knowledge of the implication it has on reliability. Specifications and standards which support the insertion of new technology must be cost effective, practical and acceptable to vendors and users while assuring quality and reliability. This paper describes the strategy and status of a new initiative to develop an industry microelectronic manufacturing specification, using best commercial practices, for silicon (Si), gallium arsenide (GaAs) and hybrid microcircuits as well as multichip modules (MCMs), including chip-on-board (COB), in hermetic or plastic packaging. The intent is to establish a national (ANSI) specification that has worldwide acceptance similar to that of I S 0 9000 l , and is used by the DoD, NASA and commercial industries (i.e., automotive, telecommunications, medical, computer).
{"title":"Dual-use Microelectronics Manufacturing Specification for Single and Multichip Packaging Technologies","authors":"M. Gorniak, D.F. Fayette, J. P. Farrell","doi":"10.1109/ICMCM.1994.753614","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753614","url":null,"abstract":"The reliability of systems and equipment is critical for both customer satisfaction and system supportability. As a technology evolves, it cannot be inserted into new systems without knowledge of the implication it has on reliability. Specifications and standards which support the insertion of new technology must be cost effective, practical and acceptable to vendors and users while assuring quality and reliability. This paper describes the strategy and status of a new initiative to develop an industry microelectronic manufacturing specification, using best commercial practices, for silicon (Si), gallium arsenide (GaAs) and hybrid microcircuits as well as multichip modules (MCMs), including chip-on-board (COB), in hermetic or plastic packaging. The intent is to establish a national (ANSI) specification that has worldwide acceptance similar to that of I S 0 9000 l , and is used by the DoD, NASA and commercial industries (i.e., automotive, telecommunications, medical, computer).","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132745967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753531
M. Interrante, H. Clearfield, K. Beckham, L. Economikos
The performance of multichip modules (MCM's) is ultimately governed by the signal propagation delay between its components. With both increasing 1/0 counts on dice and higher operating frequencies, it is critical to develop fine pitch interconnection techniques. Additionally, as multichip modules gain acceptance in commercial applications, it will be necessary to combine dice obtained from various sources on a single substrate. Such dice may have differing interconnection techniques. As part of ARPA's program for application-specific electronic modules, we have designed and built a thin film substrate that incorporates (solder) flip chip, wirebond, TAB and discrete components. In this abstract, we describe the unique interconnection aspects of the module. This includes the use of lasersonic bonding (LSB) to attach a fine (outer lead bond) pitch TAB die, a simultaneous wire microconnection technique that allows customizing the function of certain features on the module, and a top surface metallurgy compatible with the three most common interconnection technologies.
{"title":"Implementation of Advanced Micro-Interconnection Technologies on a Thin-Film Multichip Module","authors":"M. Interrante, H. Clearfield, K. Beckham, L. Economikos","doi":"10.1109/ICMCM.1994.753531","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753531","url":null,"abstract":"The performance of multichip modules (MCM's) is ultimately governed by the signal propagation delay between its components. With both increasing 1/0 counts on dice and higher operating frequencies, it is critical to develop fine pitch interconnection techniques. Additionally, as multichip modules gain acceptance in commercial applications, it will be necessary to combine dice obtained from various sources on a single substrate. Such dice may have differing interconnection techniques. As part of ARPA's program for application-specific electronic modules, we have designed and built a thin film substrate that incorporates (solder) flip chip, wirebond, TAB and discrete components. In this abstract, we describe the unique interconnection aspects of the module. This includes the use of lasersonic bonding (LSB) to attach a fine (outer lead bond) pitch TAB die, a simultaneous wire microconnection technique that allows customizing the function of certain features on the module, and a top surface metallurgy compatible with the three most common interconnection technologies.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133595751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753552
L. Economikos, S. Chiang, A. Halperin
As metal interconnections in multichip modules (MCM) are getting narrower and thinner, latent open defects such as notches, nicks, weak connections, etc., will have a greater chance to occur under normal manufacturing processes. We have applied a phase-sensitive nonlinearity detection technique to detect such latent open defects in MCM-D and MCM-C substrates. Use of this technique for qualifying opens repair techniques and wire bonding process control is reported.
{"title":"Applications of Latent Open Test","authors":"L. Economikos, S. Chiang, A. Halperin","doi":"10.1109/ICMCM.1994.753552","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753552","url":null,"abstract":"As metal interconnections in multichip modules (MCM) are getting narrower and thinner, latent open defects such as notches, nicks, weak connections, etc., will have a greater chance to occur under normal manufacturing processes. We have applied a phase-sensitive nonlinearity detection technique to detect such latent open defects in MCM-D and MCM-C substrates. Use of this technique for qualifying opens repair techniques and wire bonding process control is reported.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115070397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753609
R. Amerson, P. Kuekes
As systems become larger with more chips, multichip modules are an attractive alternative to single chip modules on printed circuit boards for achieving high density systems. Using low density design rules necessary for especially large modules presents significant challenges to achieving high density interconnect. A module with twenty-seven large chips is described with particular emphasis on the methods used to achieve extremely high density.
{"title":"A Twenty-Seven Chip MCM-C","authors":"R. Amerson, P. Kuekes","doi":"10.1109/ICMCM.1994.753609","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753609","url":null,"abstract":"As systems become larger with more chips, multichip modules are an attractive alternative to single chip modules on printed circuit boards for achieving high density systems. Using low density design rules necessary for especially large modules presents significant challenges to achieving high density interconnect. A module with twenty-seven large chips is described with particular emphasis on the methods used to achieve extremely high density.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125252591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753544
P. Zabinski, B. Gilbert, P. J. Zucarelli, D. Weninger, T. Keller
Under an Advanced Research Projects Agency program (NRaD contract N66001-89-C-0104), the Special Purpose Processor Development Group, Mayo Foundation and the Government and Systems Technology Group, Motorola, have developed a fully functional Global Positioning System (GPS) receiver using Laminated Multichip Modules (MCM-Ls) fabricated by Acsist Associates. Though the many facets of GPS are of interest in themselves, this paper will use this particular module design as an example of a more generic mixed-signal (i.e., containing both analog and digital electronic elements) system, concentrating on the design, assembly, and test aspects related to typical mixed-signal MCM problems. Topics include system requirements, design constraints, substrate selection and description, design approach, assembly, and test.
{"title":"Mixed-Signal Mcm-L Design Using a Global Positioning System (gps) Receiver as an Example","authors":"P. Zabinski, B. Gilbert, P. J. Zucarelli, D. Weninger, T. Keller","doi":"10.1109/ICMCM.1994.753544","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753544","url":null,"abstract":"Under an Advanced Research Projects Agency program (NRaD contract N66001-89-C-0104), the Special Purpose Processor Development Group, Mayo Foundation and the Government and Systems Technology Group, Motorola, have developed a fully functional Global Positioning System (GPS) receiver using Laminated Multichip Modules (MCM-Ls) fabricated by Acsist Associates. Though the many facets of GPS are of interest in themselves, this paper will use this particular module design as an example of a more generic mixed-signal (i.e., containing both analog and digital electronic elements) system, concentrating on the design, assembly, and test aspects related to typical mixed-signal MCM problems. Topics include system requirements, design constraints, substrate selection and description, design approach, assembly, and test.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122718684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753559
A. Singh
The high cost associated with replacing faulty die in many MCM technologies suggests that die used in their manufacture be known to be good with high confidence. This requires some burn-in of the die since significant "infant mortality" failures are observed for semiconductor parts. Burn-in generally involves mounting the die on temporary die carriers so that signals can be applied to activate the circuits. In this paper we present a more efficient strategy that allows the burn-in of the die on the wafer before they are diced. Our proposed approach requires that power, ground and clock connections to each die be fabricated on the wafer so that all the circuits can be powered up and clocked using only a few probe connects to the wafer. These extra connections use the space between die, and are lost once the wafer is diced into individual circuits. During burn-in, the circuits are activated in the built-in self test (BIST) mode. Here inputs to subcircuits within each die is provided by linear feedback shift registers. Power dissipation and thermal stress during burn-in is managed by controlling the air flow over the wafer surface and by appropriate selection of the thermal conduction properties of the temporary wafer carrier system employed. It is also possible to selectively power up subsets of the die to manage power dissipation. Wafer level burn-in promises to be a cost effective approach for delivering known good die.
{"title":"On Wafer Burn-in Strategies for MCM Die","authors":"A. Singh","doi":"10.1109/ICMCM.1994.753559","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753559","url":null,"abstract":"The high cost associated with replacing faulty die in many MCM technologies suggests that die used in their manufacture be known to be good with high confidence. This requires some burn-in of the die since significant \"infant mortality\" failures are observed for semiconductor parts. Burn-in generally involves mounting the die on temporary die carriers so that signals can be applied to activate the circuits. In this paper we present a more efficient strategy that allows the burn-in of the die on the wafer before they are diced. Our proposed approach requires that power, ground and clock connections to each die be fabricated on the wafer so that all the circuits can be powered up and clocked using only a few probe connects to the wafer. These extra connections use the space between die, and are lost once the wafer is diced into individual circuits. During burn-in, the circuits are activated in the built-in self test (BIST) mode. Here inputs to subcircuits within each die is provided by linear feedback shift registers. Power dissipation and thermal stress during burn-in is managed by controlling the air flow over the wafer surface and by appropriate selection of the thermal conduction properties of the temporary wafer carrier system employed. It is also possible to selectively power up subsets of the die to manage power dissipation. Wafer level burn-in promises to be a cost effective approach for delivering known good die.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124631281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753542
R. Kambe, R. Imai, T. Takada, M. Arakawa, M. Kuroda
It is well established that thin film capacitors have good electrical characteristics and for that reason are often used in high frequency applications. Unfortunately, it is also very difficult to form thin film capacitors on the relatively rough surface of cofired ceramics. We have investigated planarization of bottom capacitive electrodes which must make direct contact with a cofired ceramic surface, and adjustment and control of the T.C.E. difference between high dielectric constant material and the bass MCM ceramic substrate. Combining thin film capacitors with MCM substrates can result in high frequency decoupling capacitors (with 100X the capacitance of comparable cofired thin layer alumina constructions); space saving, and significant improvements in performance over conventional discrete chip capacitors.
{"title":"Mcm Substrate with High Capacitance","authors":"R. Kambe, R. Imai, T. Takada, M. Arakawa, M. Kuroda","doi":"10.1109/ICMCM.1994.753542","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753542","url":null,"abstract":"It is well established that thin film capacitors have good electrical characteristics and for that reason are often used in high frequency applications. Unfortunately, it is also very difficult to form thin film capacitors on the relatively rough surface of cofired ceramics. We have investigated planarization of bottom capacitive electrodes which must make direct contact with a cofired ceramic surface, and adjustment and control of the T.C.E. difference between high dielectric constant material and the bass MCM ceramic substrate. Combining thin film capacitors with MCM substrates can result in high frequency decoupling capacitors (with 100X the capacitance of comparable cofired thin layer alumina constructions); space saving, and significant improvements in performance over conventional discrete chip capacitors.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124212396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753592
R. Crowley, E. J. Vardaman
High density memory packaging is important for high performance computing systems and for small size memory systems. Smaller single chip packages as well as multichip packages have been developed for these applications. Three-dimensional (3-D) packaging is another technique that provides size and performance benefits. Memory chips are well suited to 3-D stacking techniques due to the relatively low number of I/O terminals, the ability to share many common signal lines, and low power dissipation. This paper presents an analysis of recent worldwide developments in 3-D multichip packaging for memory modules, including analyses of assembly processes and vertical interconnection.
{"title":"3-D Multichip Packaging for Memory Modules","authors":"R. Crowley, E. J. Vardaman","doi":"10.1109/ICMCM.1994.753592","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753592","url":null,"abstract":"High density memory packaging is important for high performance computing systems and for small size memory systems. Smaller single chip packages as well as multichip packages have been developed for these applications. Three-dimensional (3-D) packaging is another technique that provides size and performance benefits. Memory chips are well suited to 3-D stacking techniques due to the relatively low number of I/O terminals, the ability to share many common signal lines, and low power dissipation. This paper presents an analysis of recent worldwide developments in 3-D multichip packaging for memory modules, including analyses of assembly processes and vertical interconnection.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116883654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753568
D. Tuckerman, D. Benson, H. Moore, J. Horner, J. Gibbons
ROSS Technology, Inc., and nCHIP, Inc., have successfully produced a second-generation SPARC processor multichip module (MCM). Based on ROSS's hyperSPARC/sup TM/ architecture, the module sets a new standard for performance in the SPARC marketplace. The MCM is packaged in a 45mm-square 256-lead, ceramic quad flatpack carrier, and is footprint-compatible with ROSS' current SPARC MCM, the CYM6111. However, the new module runs at clock speeds in excess of 80 MHz, more than twice that of the CYM6111, and will offer 3-5 times the performance in most applications. The full module contains six CMOS chips: a CPU containing both integer and floating point ALUs, a cache controller/memory management unit, and four cache RAM chips. Each chip uses both 3.3 and 5.0 volt power supplies, so the MCM substrate incorporates a split power plane. The chips are interconnected using nCHIP's nC1000 substrate technology which incorporates aluminum interconnect, SiO/sub 2/ dielectric, and an integral decoupling capacitor. ROSS's multichip design strategy does not depend on massive integration or complex fabrication processes; similarly, the nCHIP nC1000 substrate process is based on a robust, IC-like technology. This combination provides excellent manufacturability and allows a fast production ramp into high volume.
{"title":"A High-Performance Second-Generation Sparc Mcm","authors":"D. Tuckerman, D. Benson, H. Moore, J. Horner, J. Gibbons","doi":"10.1109/ICMCM.1994.753568","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753568","url":null,"abstract":"ROSS Technology, Inc., and nCHIP, Inc., have successfully produced a second-generation SPARC processor multichip module (MCM). Based on ROSS's hyperSPARC/sup TM/ architecture, the module sets a new standard for performance in the SPARC marketplace. The MCM is packaged in a 45mm-square 256-lead, ceramic quad flatpack carrier, and is footprint-compatible with ROSS' current SPARC MCM, the CYM6111. However, the new module runs at clock speeds in excess of 80 MHz, more than twice that of the CYM6111, and will offer 3-5 times the performance in most applications. The full module contains six CMOS chips: a CPU containing both integer and floating point ALUs, a cache controller/memory management unit, and four cache RAM chips. Each chip uses both 3.3 and 5.0 volt power supplies, so the MCM substrate incorporates a split power plane. The chips are interconnected using nCHIP's nC1000 substrate technology which incorporates aluminum interconnect, SiO/sub 2/ dielectric, and an integral decoupling capacitor. ROSS's multichip design strategy does not depend on massive integration or complex fabrication processes; similarly, the nCHIP nC1000 substrate process is based on a robust, IC-like technology. This combination provides excellent manufacturability and allows a fast production ramp into high volume.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128234345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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