Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753614
M. Gorniak, D.F. Fayette, J. P. Farrell
The reliability of systems and equipment is critical for both customer satisfaction and system supportability. As a technology evolves, it cannot be inserted into new systems without knowledge of the implication it has on reliability. Specifications and standards which support the insertion of new technology must be cost effective, practical and acceptable to vendors and users while assuring quality and reliability. This paper describes the strategy and status of a new initiative to develop an industry microelectronic manufacturing specification, using best commercial practices, for silicon (Si), gallium arsenide (GaAs) and hybrid microcircuits as well as multichip modules (MCMs), including chip-on-board (COB), in hermetic or plastic packaging. The intent is to establish a national (ANSI) specification that has worldwide acceptance similar to that of I S 0 9000 l , and is used by the DoD, NASA and commercial industries (i.e., automotive, telecommunications, medical, computer).
{"title":"Dual-use Microelectronics Manufacturing Specification for Single and Multichip Packaging Technologies","authors":"M. Gorniak, D.F. Fayette, J. P. Farrell","doi":"10.1109/ICMCM.1994.753614","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753614","url":null,"abstract":"The reliability of systems and equipment is critical for both customer satisfaction and system supportability. As a technology evolves, it cannot be inserted into new systems without knowledge of the implication it has on reliability. Specifications and standards which support the insertion of new technology must be cost effective, practical and acceptable to vendors and users while assuring quality and reliability. This paper describes the strategy and status of a new initiative to develop an industry microelectronic manufacturing specification, using best commercial practices, for silicon (Si), gallium arsenide (GaAs) and hybrid microcircuits as well as multichip modules (MCMs), including chip-on-board (COB), in hermetic or plastic packaging. The intent is to establish a national (ANSI) specification that has worldwide acceptance similar to that of I S 0 9000 l , and is used by the DoD, NASA and commercial industries (i.e., automotive, telecommunications, medical, computer).","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132745967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753530
C. Proietti-Bowne, P. Elenius
The rework of wire bonded devices on MCMs (Multi Chip Modules) has historically been a manual procedure that has been time consuming and prone to operator error. This paper describes a complete rework process from the removal of the wires and device to the die attach material. The wires are removed using the Harmonicair/sup TM/. The Harmonicair leaves a very repeatable wire remnant on the substrate bond pad to facilitate the bonding of the next wire. The device is removed with a tensile process and the die attach material is then removed through a controlled shaving process.
{"title":"Rework of Wire Bonded Devices on Mcms","authors":"C. Proietti-Bowne, P. Elenius","doi":"10.1109/ICMCM.1994.753530","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753530","url":null,"abstract":"The rework of wire bonded devices on MCMs (Multi Chip Modules) has historically been a manual procedure that has been time consuming and prone to operator error. This paper describes a complete rework process from the removal of the wires and device to the die attach material. The wires are removed using the Harmonicair/sup TM/. The Harmonicair leaves a very repeatable wire remnant on the substrate bond pad to facilitate the bonding of the next wire. The device is removed with a tensile process and the die attach material is then removed through a controlled shaving process.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"217 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132053708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753531
M. Interrante, H. Clearfield, K. Beckham, L. Economikos
The performance of multichip modules (MCM's) is ultimately governed by the signal propagation delay between its components. With both increasing 1/0 counts on dice and higher operating frequencies, it is critical to develop fine pitch interconnection techniques. Additionally, as multichip modules gain acceptance in commercial applications, it will be necessary to combine dice obtained from various sources on a single substrate. Such dice may have differing interconnection techniques. As part of ARPA's program for application-specific electronic modules, we have designed and built a thin film substrate that incorporates (solder) flip chip, wirebond, TAB and discrete components. In this abstract, we describe the unique interconnection aspects of the module. This includes the use of lasersonic bonding (LSB) to attach a fine (outer lead bond) pitch TAB die, a simultaneous wire microconnection technique that allows customizing the function of certain features on the module, and a top surface metallurgy compatible with the three most common interconnection technologies.
{"title":"Implementation of Advanced Micro-Interconnection Technologies on a Thin-Film Multichip Module","authors":"M. Interrante, H. Clearfield, K. Beckham, L. Economikos","doi":"10.1109/ICMCM.1994.753531","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753531","url":null,"abstract":"The performance of multichip modules (MCM's) is ultimately governed by the signal propagation delay between its components. With both increasing 1/0 counts on dice and higher operating frequencies, it is critical to develop fine pitch interconnection techniques. Additionally, as multichip modules gain acceptance in commercial applications, it will be necessary to combine dice obtained from various sources on a single substrate. Such dice may have differing interconnection techniques. As part of ARPA's program for application-specific electronic modules, we have designed and built a thin film substrate that incorporates (solder) flip chip, wirebond, TAB and discrete components. In this abstract, we describe the unique interconnection aspects of the module. This includes the use of lasersonic bonding (LSB) to attach a fine (outer lead bond) pitch TAB die, a simultaneous wire microconnection technique that allows customizing the function of certain features on the module, and a top surface metallurgy compatible with the three most common interconnection technologies.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133595751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753559
A. Singh
The high cost associated with replacing faulty die in many MCM technologies suggests that die used in their manufacture be known to be good with high confidence. This requires some burn-in of the die since significant "infant mortality" failures are observed for semiconductor parts. Burn-in generally involves mounting the die on temporary die carriers so that signals can be applied to activate the circuits. In this paper we present a more efficient strategy that allows the burn-in of the die on the wafer before they are diced. Our proposed approach requires that power, ground and clock connections to each die be fabricated on the wafer so that all the circuits can be powered up and clocked using only a few probe connects to the wafer. These extra connections use the space between die, and are lost once the wafer is diced into individual circuits. During burn-in, the circuits are activated in the built-in self test (BIST) mode. Here inputs to subcircuits within each die is provided by linear feedback shift registers. Power dissipation and thermal stress during burn-in is managed by controlling the air flow over the wafer surface and by appropriate selection of the thermal conduction properties of the temporary wafer carrier system employed. It is also possible to selectively power up subsets of the die to manage power dissipation. Wafer level burn-in promises to be a cost effective approach for delivering known good die.
{"title":"On Wafer Burn-in Strategies for MCM Die","authors":"A. Singh","doi":"10.1109/ICMCM.1994.753559","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753559","url":null,"abstract":"The high cost associated with replacing faulty die in many MCM technologies suggests that die used in their manufacture be known to be good with high confidence. This requires some burn-in of the die since significant \"infant mortality\" failures are observed for semiconductor parts. Burn-in generally involves mounting the die on temporary die carriers so that signals can be applied to activate the circuits. In this paper we present a more efficient strategy that allows the burn-in of the die on the wafer before they are diced. Our proposed approach requires that power, ground and clock connections to each die be fabricated on the wafer so that all the circuits can be powered up and clocked using only a few probe connects to the wafer. These extra connections use the space between die, and are lost once the wafer is diced into individual circuits. During burn-in, the circuits are activated in the built-in self test (BIST) mode. Here inputs to subcircuits within each die is provided by linear feedback shift registers. Power dissipation and thermal stress during burn-in is managed by controlling the air flow over the wafer surface and by appropriate selection of the thermal conduction properties of the temporary wafer carrier system employed. It is also possible to selectively power up subsets of the die to manage power dissipation. Wafer level burn-in promises to be a cost effective approach for delivering known good die.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124631281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753544
P. Zabinski, B. Gilbert, P. J. Zucarelli, D. Weninger, T. Keller
Under an Advanced Research Projects Agency program (NRaD contract N66001-89-C-0104), the Special Purpose Processor Development Group, Mayo Foundation and the Government and Systems Technology Group, Motorola, have developed a fully functional Global Positioning System (GPS) receiver using Laminated Multichip Modules (MCM-Ls) fabricated by Acsist Associates. Though the many facets of GPS are of interest in themselves, this paper will use this particular module design as an example of a more generic mixed-signal (i.e., containing both analog and digital electronic elements) system, concentrating on the design, assembly, and test aspects related to typical mixed-signal MCM problems. Topics include system requirements, design constraints, substrate selection and description, design approach, assembly, and test.
{"title":"Mixed-Signal Mcm-L Design Using a Global Positioning System (gps) Receiver as an Example","authors":"P. Zabinski, B. Gilbert, P. J. Zucarelli, D. Weninger, T. Keller","doi":"10.1109/ICMCM.1994.753544","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753544","url":null,"abstract":"Under an Advanced Research Projects Agency program (NRaD contract N66001-89-C-0104), the Special Purpose Processor Development Group, Mayo Foundation and the Government and Systems Technology Group, Motorola, have developed a fully functional Global Positioning System (GPS) receiver using Laminated Multichip Modules (MCM-Ls) fabricated by Acsist Associates. Though the many facets of GPS are of interest in themselves, this paper will use this particular module design as an example of a more generic mixed-signal (i.e., containing both analog and digital electronic elements) system, concentrating on the design, assembly, and test aspects related to typical mixed-signal MCM problems. Topics include system requirements, design constraints, substrate selection and description, design approach, assembly, and test.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122718684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753609
R. Amerson, P. Kuekes
As systems become larger with more chips, multichip modules are an attractive alternative to single chip modules on printed circuit boards for achieving high density systems. Using low density design rules necessary for especially large modules presents significant challenges to achieving high density interconnect. A module with twenty-seven large chips is described with particular emphasis on the methods used to achieve extremely high density.
{"title":"A Twenty-Seven Chip MCM-C","authors":"R. Amerson, P. Kuekes","doi":"10.1109/ICMCM.1994.753609","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753609","url":null,"abstract":"As systems become larger with more chips, multichip modules are an attractive alternative to single chip modules on printed circuit boards for achieving high density systems. Using low density design rules necessary for especially large modules presents significant challenges to achieving high density interconnect. A module with twenty-seven large chips is described with particular emphasis on the methods used to achieve extremely high density.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125252591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753592
R. Crowley, E. J. Vardaman
High density memory packaging is important for high performance computing systems and for small size memory systems. Smaller single chip packages as well as multichip packages have been developed for these applications. Three-dimensional (3-D) packaging is another technique that provides size and performance benefits. Memory chips are well suited to 3-D stacking techniques due to the relatively low number of I/O terminals, the ability to share many common signal lines, and low power dissipation. This paper presents an analysis of recent worldwide developments in 3-D multichip packaging for memory modules, including analyses of assembly processes and vertical interconnection.
{"title":"3-D Multichip Packaging for Memory Modules","authors":"R. Crowley, E. J. Vardaman","doi":"10.1109/ICMCM.1994.753592","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753592","url":null,"abstract":"High density memory packaging is important for high performance computing systems and for small size memory systems. Smaller single chip packages as well as multichip packages have been developed for these applications. Three-dimensional (3-D) packaging is another technique that provides size and performance benefits. Memory chips are well suited to 3-D stacking techniques due to the relatively low number of I/O terminals, the ability to share many common signal lines, and low power dissipation. This paper presents an analysis of recent worldwide developments in 3-D multichip packaging for memory modules, including analyses of assembly processes and vertical interconnection.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116883654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753552
L. Economikos, S. Chiang, A. Halperin
As metal interconnections in multichip modules (MCM) are getting narrower and thinner, latent open defects such as notches, nicks, weak connections, etc., will have a greater chance to occur under normal manufacturing processes. We have applied a phase-sensitive nonlinearity detection technique to detect such latent open defects in MCM-D and MCM-C substrates. Use of this technique for qualifying opens repair techniques and wire bonding process control is reported.
{"title":"Applications of Latent Open Test","authors":"L. Economikos, S. Chiang, A. Halperin","doi":"10.1109/ICMCM.1994.753552","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753552","url":null,"abstract":"As metal interconnections in multichip modules (MCM) are getting narrower and thinner, latent open defects such as notches, nicks, weak connections, etc., will have a greater chance to occur under normal manufacturing processes. We have applied a phase-sensitive nonlinearity detection technique to detect such latent open defects in MCM-D and MCM-C substrates. Use of this technique for qualifying opens repair techniques and wire bonding process control is reported.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115070397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753536
H. G. Muller, Yanrong Yuan, R. Sheets
A new type of photolithography tool has been developed, addressing the specific needs of MCM manufacture. It is based on scanning projection exposure. It can expose panels at variable sizes up to 500 mm by 600 mm (typical laminate size), with an optical resolution of less than 5 gm and an overlay accuracy of 2 /spl mu/m (typical thin film design rules). With the exposure being a mask projection, mask damage and subsequent yield problems are generally avoided.
{"title":"Large Area Fine Line Patterning by Scanning Projection Lithography","authors":"H. G. Muller, Yanrong Yuan, R. Sheets","doi":"10.1109/ICMCM.1994.753536","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753536","url":null,"abstract":"A new type of photolithography tool has been developed, addressing the specific needs of MCM manufacture. It is based on scanning projection exposure. It can expose panels at variable sizes up to 500 mm by 600 mm (typical laminate size), with an optical resolution of less than 5 gm and an overlay accuracy of 2 /spl mu/m (typical thin film design rules). With the exposure being a mask projection, mask damage and subsequent yield problems are generally avoided.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126558693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-13DOI: 10.1109/ICMCM.1994.753608
E. Fulcher, S. Patil
A ceramic MCM was designed and put into volume production. Four identical 15MM per side ASIC devices with 370 bond pads each are wirebonded into a four cavity, cofired, alumina PGA with 383 pins. All materials and processes were selected following the "KISS' (Keep It Super Simple) principle in order to minimize risk and. insure meeting schedule requirements. The results are smaller size, better electrical performance and lower cost than four single chip CPGAs.
设计了一种陶瓷MCM，并进行了批量生产。四个相同的每侧15MM的ASIC器件，每个都有370个键垫，通过导线连接到四个腔，共烧，氧化铝PGA, 383个引脚。所有材料和工艺的选择都遵循“KISS”(Keep It Super Simple)原则，以最大限度地降低风险和成本。确保满足计划要求。与4个单片CPGAs相比，具有体积更小、电性能更好、成本更低的优点。
{"title":"A Four Asic Mcm-c, the \"Kiss\" Principle, and the Next Generation Silicon","authors":"E. Fulcher, S. Patil","doi":"10.1109/ICMCM.1994.753608","DOIUrl":"https://doi.org/10.1109/ICMCM.1994.753608","url":null,"abstract":"A ceramic MCM was designed and put into volume production. Four identical 15MM per side ASIC devices with 370 bond pads each are wirebonded into a four cavity, cofired, alumina PGA with 383 pins. All materials and processes were selected following the \"KISS' (Keep It Super Simple) principle in order to minimize risk and. insure meeting schedule requirements. The results are smaller size, better electrical performance and lower cost than four single chip CPGAs.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126158830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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