Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272107
S. Pearton, C. Abernathy, B. Gila, F. Ren, J. Zavada, S. Chu
Some examples of recent advances in enhancing or adding functionality to GaN and SiC devices through the use of novel processing techniques are discussed. The first example is the use of ion implantation to incorporate transition metals such as Mn, Cr and Co at atomic percent levels in the wide bandgap semiconductors to produce room temperature ferromagnetism. A discussion is given of the phase space within which single-phase material can be obtained and the requirements for demonstrating the presence of a true dilute magnetic semiconductor. The ability to make GaN and SiC ferromagnetic leads to the possibility of magnetic devices with gain, spin fets operating at low voltages and spin polarized light emitters. The second example is the use of novel oxides such as Sc/sub 2/O/sub 3/ and MgO as gate dielectrics or surface passivants on GaN. True inversion behavior has been demonstrated in gated MOS-GaN diodes with implanted n-regions supplying the minority carriers need for inversion. These oxide layers also effectively mitigate current collapse in AlGaN/GaN HEMTs through their passivation of surface states in the gate-drain region. The third example is the use of laser drilling to make through-wafer via holes in SiC, sapphire and GaN. The ablation rate is sufficiently high that this maskless, serial process appears capable of achieving similar throughput to the more conventional approach of plasma etching of vias. The fourth example is the use of either ungated AlGaN/GaN HEMTs or simple GaN and SiC Schottky diodes as sensors for chemicals, biogens, radiation, combustion gases or strain. The sensitivity of either the channel carrier density or the barrier height to changes in surface condition make these materials systems ideal for compact, robust sensors capable of operating at elevated temperatures.
{"title":"Enhanced functionality in GaN and SiC devices by using novel processing","authors":"S. Pearton, C. Abernathy, B. Gila, F. Ren, J. Zavada, S. Chu","doi":"10.1109/ISDRS.2003.1272107","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272107","url":null,"abstract":"Some examples of recent advances in enhancing or adding functionality to GaN and SiC devices through the use of novel processing techniques are discussed. The first example is the use of ion implantation to incorporate transition metals such as Mn, Cr and Co at atomic percent levels in the wide bandgap semiconductors to produce room temperature ferromagnetism. A discussion is given of the phase space within which single-phase material can be obtained and the requirements for demonstrating the presence of a true dilute magnetic semiconductor. The ability to make GaN and SiC ferromagnetic leads to the possibility of magnetic devices with gain, spin fets operating at low voltages and spin polarized light emitters. The second example is the use of novel oxides such as Sc/sub 2/O/sub 3/ and MgO as gate dielectrics or surface passivants on GaN. True inversion behavior has been demonstrated in gated MOS-GaN diodes with implanted n-regions supplying the minority carriers need for inversion. These oxide layers also effectively mitigate current collapse in AlGaN/GaN HEMTs through their passivation of surface states in the gate-drain region. The third example is the use of laser drilling to make through-wafer via holes in SiC, sapphire and GaN. The ablation rate is sufficiently high that this maskless, serial process appears capable of achieving similar throughput to the more conventional approach of plasma etching of vias. The fourth example is the use of either ungated AlGaN/GaN HEMTs or simple GaN and SiC Schottky diodes as sensors for chemicals, biogens, radiation, combustion gases or strain. The sensitivity of either the channel carrier density or the barrier height to changes in surface condition make these materials systems ideal for compact, robust sensors capable of operating at elevated temperatures.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115828433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272041
C. Shih, Yi-Min Chen, C. Lien
This article presents an analytical short-channel effect model without any fitting parameter for the MOSFET with insulated shallow extension (ISE). The effect of ISE structure for the highly improved short-channel effect of sub-100 nm MOSFET is demonstrated in this model. Both sidewall-oxide thickness (T/sub side/) and shallow-extension depth (X/sub e/) play the major roles in containing the short-channel effect. The short-channel threshold-voltage equation is derived from the knowledge of the channel potential. The channel potential is obtained by the scale-length approach to solve 2D Poisson's equation. Excellent agreements between the numerical simulated results and this model are obtained.
{"title":"Effect of insulated shallow extension for the improved short-channel effect of sub-100 nm MOSFET","authors":"C. Shih, Yi-Min Chen, C. Lien","doi":"10.1109/ISDRS.2003.1272041","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272041","url":null,"abstract":"This article presents an analytical short-channel effect model without any fitting parameter for the MOSFET with insulated shallow extension (ISE). The effect of ISE structure for the highly improved short-channel effect of sub-100 nm MOSFET is demonstrated in this model. Both sidewall-oxide thickness (T/sub side/) and shallow-extension depth (X/sub e/) play the major roles in containing the short-channel effect. The short-channel threshold-voltage equation is derived from the knowledge of the channel potential. The channel potential is obtained by the scale-length approach to solve 2D Poisson's equation. Excellent agreements between the numerical simulated results and this model are obtained.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123393391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272000
W. Jadwisienczak, H. Lozykowski, A. Bensaoula, O. Monteiro
In this presentation, we report on the cathodoluminescence and photoluminescence (PL) properties of Pr and Tm ions implanted into AlN films grown by plasma source molecular beam epitaxy. To optically activate incorporated impurities and remove ion implantation-induced damages, the RE-implanted AlN samples were given isochronal thermal annealing treatments at a temperature of 1050 /spl deg/C in NH/sub 3/.
{"title":"Luminescence of Pr and Tm ions implanted into AlN thin films","authors":"W. Jadwisienczak, H. Lozykowski, A. Bensaoula, O. Monteiro","doi":"10.1109/ISDRS.2003.1272000","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272000","url":null,"abstract":"In this presentation, we report on the cathodoluminescence and photoluminescence (PL) properties of Pr and Tm ions implanted into AlN films grown by plasma source molecular beam epitaxy. To optically activate incorporated impurities and remove ion implantation-induced damages, the RE-implanted AlN samples were given isochronal thermal annealing treatments at a temperature of 1050 /spl deg/C in NH/sub 3/.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121928918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272165
A. J. de Marco, J. Melngailis
The creation of active devices utilizing solely FIB fabrication is investigated in this paper. JFETs are constructed using FIB techniques on a mesa of n-type silicon situated atop a layer of silicon dioxide. The source and drain regions are implanted using a beam of singly-charged arsenic ions accelerated to 120 kV. The gate is implanted with singly-charged boron ions at 10 kV. The source, gate, and drain contacts are directly written by FIB using a 30 kV gallium ion beam. FIB deposited platinum forms an ohmic contact to heavily doped silicon, with an average contact resistance of 9.17/spl times/10/sup -3/ /spl Omega/-cm/sup 2/. The CV characteristics of JFET with FIB-fabricated dopants and contacts are illustrated.
{"title":"Maskless fabrication of JFETs via focused ion beams","authors":"A. J. de Marco, J. Melngailis","doi":"10.1109/ISDRS.2003.1272165","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272165","url":null,"abstract":"The creation of active devices utilizing solely FIB fabrication is investigated in this paper. JFETs are constructed using FIB techniques on a mesa of n-type silicon situated atop a layer of silicon dioxide. The source and drain regions are implanted using a beam of singly-charged arsenic ions accelerated to 120 kV. The gate is implanted with singly-charged boron ions at 10 kV. The source, gate, and drain contacts are directly written by FIB using a 30 kV gallium ion beam. FIB deposited platinum forms an ohmic contact to heavily doped silicon, with an average contact resistance of 9.17/spl times/10/sup -3/ /spl Omega/-cm/sup 2/. The CV characteristics of JFET with FIB-fabricated dopants and contacts are illustrated.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124087652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272156
H.-M. Wu, J. Lin, L. Peng, C. Lee, J. Chyi, E. Chen
The authors investigate the annealing effects on the interfacial properties of gallium oxide (Ga/sub 2/O/sub 3/) grown on gallium nitride (GaN) by the photo-enhanced wet oxidation technique. The depth profile resolved XPS analysis indicates an interfacial layer as thin as 20nm can be maintained at the Ga/sub 2/O/sub 3//GaN interface when subject to a rapid thermal annealing in an oxygen ambient at 800/spl deg/C. The authors I-V and C-V analysis on the MOS device reveals a low interfacial density of state /spl sim/5/spl times/10/sup 10/ cm/sup -2/eV/sup -1/ and high breakdown field above 3MV/cm. These results suggest the photo-grown Ga/sub 2/O/sub 3/ with post O/sub 2/ annealing is suitable for power device application.
{"title":"Annealing effects on the interfacial properties of GaN MOS prepared by photo-enhanced wet oxidation","authors":"H.-M. Wu, J. Lin, L. Peng, C. Lee, J. Chyi, E. Chen","doi":"10.1109/ISDRS.2003.1272156","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272156","url":null,"abstract":"The authors investigate the annealing effects on the interfacial properties of gallium oxide (Ga/sub 2/O/sub 3/) grown on gallium nitride (GaN) by the photo-enhanced wet oxidation technique. The depth profile resolved XPS analysis indicates an interfacial layer as thin as 20nm can be maintained at the Ga/sub 2/O/sub 3//GaN interface when subject to a rapid thermal annealing in an oxygen ambient at 800/spl deg/C. The authors I-V and C-V analysis on the MOS device reveals a low interfacial density of state /spl sim/5/spl times/10/sup 10/ cm/sup -2/eV/sup -1/ and high breakdown field above 3MV/cm. These results suggest the photo-grown Ga/sub 2/O/sub 3/ with post O/sub 2/ annealing is suitable for power device application.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126176697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272037
A. Breed, K. Roenker
The continued downward scaling of silicon MOSFET device dimensions below one tenth micron has presented new and serious challenges for future integrated circuit applications. Accordingly, new MOSFET structures, such as the dual-gate (FinFET) and the tri-Gate transistor, have been proposed to replace the conventional planar MOSFET. These devices are compatible with conventional silicon integrated circuit processing, but offer superior performance as the device is scaled into the nanometer range. However, the physics of the MOSFET's operation in these new device structures is somewhat different. This study aims to investigate the differences in performance of these two devices and their device design using a commercial, three-dimensional numerical simulator ATLAS from Silvaco International.
{"title":"Dual-gate (FinFET) and tri-Gate MOSFETs: simulation and design","authors":"A. Breed, K. Roenker","doi":"10.1109/ISDRS.2003.1272037","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272037","url":null,"abstract":"The continued downward scaling of silicon MOSFET device dimensions below one tenth micron has presented new and serious challenges for future integrated circuit applications. Accordingly, new MOSFET structures, such as the dual-gate (FinFET) and the tri-Gate transistor, have been proposed to replace the conventional planar MOSFET. These devices are compatible with conventional silicon integrated circuit processing, but offer superior performance as the device is scaled into the nanometer range. However, the physics of the MOSFET's operation in these new device structures is somewhat different. This study aims to investigate the differences in performance of these two devices and their device design using a commercial, three-dimensional numerical simulator ATLAS from Silvaco International.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129767975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272092
M.J. Kumar, V. Parihar
In order to improve driver performance of PNP transistor high current gain is required but PNP transistor exhibits low current gain due to poor hole mobility. In this paper a novel high current gain lateral PNP transistor on SOI for complementary bipolar technology is presented. The paper also presents the demonstration of a significant current gain enhancement in a PNP transistor using simple surface accumulation layer transistor that is compatible with standard BiCMOS technology.
{"title":"A novel high current gain lateral PNP transistor on SOI for complementary bipolar technology","authors":"M.J. Kumar, V. Parihar","doi":"10.1109/ISDRS.2003.1272092","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272092","url":null,"abstract":"In order to improve driver performance of PNP transistor high current gain is required but PNP transistor exhibits low current gain due to poor hole mobility. In this paper a novel high current gain lateral PNP transistor on SOI for complementary bipolar technology is presented. The paper also presents the demonstration of a significant current gain enhancement in a PNP transistor using simple surface accumulation layer transistor that is compatible with standard BiCMOS technology.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128658732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272170
M. Manfra
We report on the growth and power performance of GaN/AlGaN/GaN high electron mobility transistors (HEMTs) grown by plasma-assisted molecular beam epitaxy (MBE) on semi-insulating SiC substrates. We detail the MBE growth conditions that consistently produce high mobility two-dimensional electron gases (2DEGs) with room temperature mobility of /spl sim/1400 cm/sup 2//Vs at a sheet density of 1.2/spl times/10/sup 13/ cm/sup -2/. Transistors fabricated from these layers have demonstrated power densities in excess of 8 W/mm at 2 GHz, 6 W/mm at 7 GHz, and 3 W/mm at 25 GHz. All power data is achieved without the use of a SiN surface passivation layer. Central to the achievement of high power operation is the reduction of RF dispersion. Our growth studies have focused on the suppression of RF dispersion and maximizing RF output power. Pulsed IV and gate lag measurements are used to quantify the amount of dispersion in different heterostructure designs and to elucidate the trapping mechanisms responsible for gate lag.
{"title":"High power GaN/AlGaN/GaN HEMTs operating at 2 to 25 GHz grown by plasma-assisted molecular beam epitaxy","authors":"M. Manfra","doi":"10.1109/ISDRS.2003.1272170","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272170","url":null,"abstract":"We report on the growth and power performance of GaN/AlGaN/GaN high electron mobility transistors (HEMTs) grown by plasma-assisted molecular beam epitaxy (MBE) on semi-insulating SiC substrates. We detail the MBE growth conditions that consistently produce high mobility two-dimensional electron gases (2DEGs) with room temperature mobility of /spl sim/1400 cm/sup 2//Vs at a sheet density of 1.2/spl times/10/sup 13/ cm/sup -2/. Transistors fabricated from these layers have demonstrated power densities in excess of 8 W/mm at 2 GHz, 6 W/mm at 7 GHz, and 3 W/mm at 25 GHz. All power data is achieved without the use of a SiN surface passivation layer. Central to the achievement of high power operation is the reduction of RF dispersion. Our growth studies have focused on the suppression of RF dispersion and maximizing RF output power. Pulsed IV and gate lag measurements are used to quantify the amount of dispersion in different heterostructure designs and to elucidate the trapping mechanisms responsible for gate lag.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132391227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272149
S. Mitra, A. Salman, D. Ioannou, C. Tretz, D. Ioannou
This paper investigates the possibility of using SDG (symmetric double gate) device intrinsically on structure as a load device for DG-SOI based ratioed logic, To establish the feasibility and superiority of this approach an inverter and a NOR gate were designed, which exhibits considerable advantages. The work is then extented to show how the approach can also be used to built NAND and XOR gates to create a complete logic family. All the simulations are done for 50 nm gate length devices using SILVACO tools. Voltage transfer characteristics are studied for both SDG load and ADG (asymmetric double gate) inverter. The transient characteristics obtained with a 1.25 GHz pulse on the n/sup +/-poly gate and a 500 MHz on the p/sup +/-poly gate are also studied.
{"title":"DG-SOI ratioed logic with symmetric DG load - a novel approach for sub 50 nm LV/LP circuit design","authors":"S. Mitra, A. Salman, D. Ioannou, C. Tretz, D. Ioannou","doi":"10.1109/ISDRS.2003.1272149","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272149","url":null,"abstract":"This paper investigates the possibility of using SDG (symmetric double gate) device intrinsically on structure as a load device for DG-SOI based ratioed logic, To establish the feasibility and superiority of this approach an inverter and a NOR gate were designed, which exhibits considerable advantages. The work is then extented to show how the approach can also be used to built NAND and XOR gates to create a complete logic family. All the simulations are done for 50 nm gate length devices using SILVACO tools. Voltage transfer characteristics are studied for both SDG load and ADG (asymmetric double gate) inverter. The transient characteristics obtained with a 1.25 GHz pulse on the n/sup +/-poly gate and a 500 MHz on the p/sup +/-poly gate are also studied.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132099468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-10DOI: 10.1109/ISDRS.2003.1272197
T. McNutt, A. Hefner, A. Mantooth, D. Berning, R. Singh
In order for circuit designers to fully utilize the advantages of the new SiC power device technologies, compact models are needed in circuit and system simulation tools. Models of silicon carbide power device characteristics were presented in this paper. Physics based models of VDMOSFET, output characteristics and switching vs gate resistance characteristics of SiC DiMOSFET were presented in this paper.
{"title":"Compact models for silicon carbide power devices","authors":"T. McNutt, A. Hefner, A. Mantooth, D. Berning, R. Singh","doi":"10.1109/ISDRS.2003.1272197","DOIUrl":"https://doi.org/10.1109/ISDRS.2003.1272197","url":null,"abstract":"In order for circuit designers to fully utilize the advantages of the new SiC power device technologies, compact models are needed in circuit and system simulation tools. Models of silicon carbide power device characteristics were presented in this paper. Physics based models of VDMOSFET, output characteristics and switching vs gate resistance characteristics of SiC DiMOSFET were presented in this paper.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126649214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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